dc.contributor.author | Salvesen, Peter | |
dc.contributor.author | Jahre, Magnus | |
dc.date.accessioned | 2023-01-23T13:05:22Z | |
dc.date.available | 2023-01-23T13:05:22Z | |
dc.date.created | 2022-09-28T13:40:01Z | |
dc.date.issued | 2022 | |
dc.identifier.citation | IEEE computer architecture letters. 2022, 21 (2), 97-100. | en_US |
dc.identifier.issn | 1556-6056 | |
dc.identifier.uri | https://hdl.handle.net/11250/3045367 | |
dc.description.abstract | Multi-core processors suffer from inter-application interference which makes the performance of an application depend on the behavior of the applications it happens to be co-scheduled with. This results in performance variability, which is undesirable, and researchers have hence proposed numerous schemes for predicting the performance slowdown caused by inter-application interference. While a slowdown predictor's primary objective is to achieve high accuracy, it must typically also respect resource constraints. It is hence beneficial to be able to scale the resource consumption of the predictor, but state-of-the-art slowdown predictors are not resource-scalable. We hence propose to construct predictors using Linear Model Trees (LMTs) which we show to be accurate and resource-scalable. More specifically, our 40-leaf-node LMT-40 predictor yields a 6.6% prediction error compared the 8.4% error of state-of-the-art GDP at similar storage overhead. In contrast, our LMT-10 predictor reduces storage overhead by 34.6% compared to GDP while only increasing prediction error to 9.4%. | en_US |
dc.language.iso | eng | en_US |
dc.publisher | IEEE | en_US |
dc.title | LMT: Accurate and Resource-Scalable Slowdown Prediction | en_US |
dc.title.alternative | LMT: Accurate and Resource-Scalable Slowdown Prediction | en_US |
dc.type | Peer reviewed | en_US |
dc.type | Journal article | en_US |
dc.description.version | acceptedVersion | en_US |
dc.rights.holder | © IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | en_US |
dc.subject.nsi | VDP::Datateknologi: 551 | en_US |
dc.subject.nsi | VDP::Computer technology: 551 | en_US |
dc.source.pagenumber | 97-100 | en_US |
dc.source.volume | 21 | en_US |
dc.source.journal | IEEE computer architecture letters | en_US |
dc.source.issue | 2 | en_US |
dc.identifier.doi | 10.1109/LCA.2022.3203483 | |
dc.identifier.cristin | 2056396 | |
dc.relation.project | Norges forskningsråd: 286596 | en_US |
cristin.ispublished | true | |
cristin.fulltext | postprint | |
cristin.qualitycode | 1 | |