| dc.description.abstract | A typical microcontroller unit (MCU) has limited capabilities for processing and displaying graphics, due to power and size constraints. An increasing demand for rich graphical user interface (GUI) applications in battery powered systems motivates microcontroller vendors to include additional hardware to accelerate graphics processing. The goal of this master thesis was to analyze the graphics processing capability of a typical microcontroller and to explore different architectures for improving performance. A RISC-V ISA based simulator of a generic, heterogeneous, and multi-core system on chip (SoC) with shared memory and I/O written using SystemC + TLM provided the hardware environment needed for the analysis and exploration. LVGL which is a embedded graphics library was used for writing the application code for this hardware simulator.
The main phases of the thesis were - setting up the hardware simulator environment, setting up a benchmarking framework on the application code, doing baseline performance analysis and arriving at possible areas for improvement, designing architectural improvements and exploring various scenarios. The two improvements which were analyzed and performed were adding direct memory access (DMA) capability to the basic display controller, and designing a hardware accelerator for offloading fill and blend operations from the CPU, also with DMA. When these two were used together for drawing different scenes, an average 68\% reduction in the cycles was obtained compared to the cycles taken to render it in the baseline scenario, thus increasing the processing speed of the application. In addition to this reduction, an average of 18\% of the cycles taken were saved, thus freeing up the CPU to do something else during these cycles.
Keywords: MCU, RISC-V, Hardware Accelerator, TLM, Graphics Processing | |
