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dc.contributor.authorIordan, Alexandru Ciprian
dc.contributor.authorJahre, Magnus
dc.contributor.authorNatvig, Lasse
dc.date.accessioned2016-06-16T09:45:30Z
dc.date.accessioned2016-06-17T06:58:49Z
dc.date.available2016-06-16T09:45:30Z
dc.date.available2016-06-17T06:58:49Z
dc.date.issued2015-11
dc.identifier.citationJournal of systems architecture 2015, 61(10):584-591nb_NO
dc.identifier.issn1383-7621
dc.identifier.urihttp://hdl.handle.net/11250/2392984
dc.description.abstractThe wide adoption of Chip Multiprocessors (CMPs) in almost all ICT segments has triggered a change in the way software needs to be developed. Parallel programming maximizes the performance and energy efficiency of CMPs, but also comes with a new set of challenges. Parallelization overheads can account for sub-linear speedups and can increase the energy consumption of applications. In past experiments we looked at specific operations such as spawning new tasks, dequeuing the task queue and task stealing for Intel TBB. Our results showed that failed steals account for the largest overhead. In this work, we focus on TBB’s victim selection policy. We implement a new occupancy-aware policy and we improve the implementation of the pseudo-random policy we proposed in a previous paper. We compare the results of our new policies against an “oracle scheme” as well as against TBB’s random victim selection approach. Our results show improvements in execution times and energy-efficiency of up to 11.23% and 14.72% respectively when compared to TBB’s default policy.nb_NO
dc.language.isoengnb_NO
dc.publisherElseviernb_NO
dc.relation.urihttp://www.sciencedirect.com/science/article/pii/S1383762115000740
dc.titleTuning the victim selection policy of Intel TBBnb_NO
dc.typeJournal articlenb_NO
dc.typePeer reviewednb_NO
dc.date.updated2016-06-16T09:45:30Z
dc.source.pagenumber584-591nb_NO
dc.source.volume61nb_NO
dc.source.journalJournal of systems architecturenb_NO
dc.source.issue10nb_NO
dc.identifier.doi10.1016/j.sysarc.2015.07.004
dc.identifier.cristin1297481
dc.relation.projectNotur/NorStore: NN4650Knb_NO
dc.description.localcodeThis document is the unedited Author's version of a Submitted Work that was subsequently accepted for publication in Journal of systems architecture , copyright (c) Elsevier after peer review. To access the final edited and published work see http://dx.doi.org/10.1016/j.sysarc.2015.07.004nb_NO


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