| dc.description.abstract | In this thesis a virtual layer for running self-cloning state machines on FPGAs has been developed. The goal has been to connect software with hardware resources, and to make partial reconfigurability more available. Previous work has been done on defining self-cloning state machines that can run on an FPGA, but was not tested with partial runtime reconfiguration. A framework for reconfiguration has been used in this thesis, which had previous shown some difficulties regarding synchronous designs.
Specifications for the virtual layer were defined, and the different modules constructed. The virtual layer was implemented on a Virtex-4 FPGA, with an embedded PorwerPC microprocessor running a Linux operating system. The virtual layer gives software application an interface for defining state machines, which will be mapped to the FPGA and executed. The modules on the FPGA are separated into two parts, one reconfigurable region and one static region. The static region contains a back-end that handles the control of the NFSM and communication with the processor. The reconfigurable region contains the NFSM, which is divided into several clones. The clones can be inserted or removed by using partial runtime reconfiguration.
Many difficulties were experienced when trying to implement the virtual layer with support for partial runtime reconfiguration. The tool support was lacking and the space on the FPGA became a problem. Only one clone could be fitted on the FPGA. Therefore the verification of the system was divided in two. A state machine with four clones was tested and verified. The virtual layer was able to take input from software and map this into a functional self-cloning state machine. Some limitations had to be put on the system to make it possible to implement. A second test was performed with partial runtime reconfiguration to show that clones could be added or removed from the design at runtime. The test was successful, but could only be done with one active clone. The limitations of the Virtex-4 platform can be avoided by implementing the virtual layer on a more state of the art FPGA. The system defined in this thesis should work on any FPGA, but will require a lot of work, especially porting of the framework for reconfiguration. | |
