Integration of hardware accelerators on the SHMAC platform

Abstract

The historical trend of rampant processor performance gain has slowed down in recent years due to the Dark Silicon Effect, which arises when Moore's law meets the breakdown in Dennard scaling for sub-130nm architectures. This effect has caused the industry to move into heterogeneous multicore architectures in an attempt to utilize this "dark silicon". Heterogeneous systems offer the ability to increase performance in applications by implementing accelerators specifically designed to the application. The SHMAC project aims to create a platform for research into heterogeneous systems, where an FPGA platform can provide quick implementation of systems for evaluation.This thesis proposes a system where an accelerator quickly can be implemented into the SHMAC platform through a set of three different Interface Modules(IFM), and be controlled by the Amber Core through instructions in the ARM ISA. Furthermore the thesis proposes a script based system that generates an accelerated Amber Tile ready for integration into the SHMAC platform. Accelerators that are to be implemented with the IFMs need to meet specific criteria for interface. In order to define these, this thesis proposes a General Accelerator Interface designed to accommodate a wide range of diverse accelerators.