Configurable Floating-Point Unit for the SHMAC Platform

Abstract

The use of floating-point hardware in FPGAs has long been considered infeasible or related to use in expensive devices and platforms. However, floating-point operations are crucial for many scientic computations and for efficient programming, floating-point is preferred. The IEEE Standard 754 for floating-point arithmetic provides a method that will yield the same results whether the processing is done in hardware, software or the combination of the two. However, the scope of this standard is much more comprehensivethan what is needed for many systems and can cause a lot of overhead. This thesis presents ways to lower the power consumption, area usage and latency by using a congurable floating-point unit (FPU) with variable bit-width.There is a linear relation between the bit-width of floating-point numbers and the dynamic power consumption, while there is an exponential relation between the bit-width and area consumption. If only a limited range and precision are needed, using a tailored FPU design can reduce the area and dynamic power consumption by up to 96%. Choosing the right FPU can also reduce the number of clock cycles per operation with up to 98%. For the applications analyzed, a maximum of 33% of the bit-width in floating-point numbers are unnecessary, and removing these leads to great performance and area gains. By analyzing the frequency the dierent operations are used in applications, some floating-point operations can be emulated in software and greater area and power savings can be accomplished.