Browsing NTNU Open by Author "Svarstad, Kjetil"
Now showing items 41-60 of 81
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FPGA Implementation of Hyperspectral Anomaly Detection Algorithm
Haukali, Martin (Master thesis, 2018)On-board processing of hyperspectral data in satellites is done to perform a wide variety of tasks. Field-Programmable Gate Arrays (FPGAs) are often used for such tasks due to their reconfigurability and efficiency, ... -
FPGA Video Stream Communication System
Shallari, Irida (Master thesis, 2016)Video processing systems consist mostly of large designs highly critical in synchronisation and delays of data transfers. In this thesis is introduced the design of an FPGA Video Stream Communication System. It will provide ... -
FPGA virtualization layer for non-deterministic state machines
Heimark, Tormod (Master thesis, 2015)In this thesis a virtual layer for running self-cloning state machines on FPGAs has been developed. The goal has been to connect software with hardware resources, and to make partial reconfigurability more available. ... -
FPGA-plattform for AHEAD
Arntsen, Stian Reiersen (Master thesis, 2006)Denne rapporten bygger på arbeidet som er gjort i forbindelse med en FPGA plattform for AHEAD prosjektet. Teori og arbeid i rapporten er bygd rundt den valgte FPGA utviklingsplattformen Suzaku-S. Rapporten begynner med ... -
Framework for self reconfigurable system on a Xilinx FPGA.
Hamre, Sverre (Master thesis, 2009)Partial self reconfigurable hardware has not yet become main stream, even though the technology is available. Currently FPGA manufacturer like Xilinx has FPGA devices that can do partial self reconfiguration. These and ... -
Hardware Acceleration of a Deep Neural Network on a FPGA
Hordnes, Vebjørn (Master thesis, 2019)Maskinlæring har blitt et populært emne i nyere tid, siden det viser seg å ha et betydelig fortrinn over tradisjonelle håndskrevede algoritmer i bestemte applikasjoner. Et mangfold av forskjellig modeller er nå i bruk i ... -
Hardware implementation of a target detection algorithm for hyperspectral images
Boskovic, Dordije (Master thesis, 2019)Hyper-Spectral Imager for Oceanographic Applications (HYPSO) is being developed as a part of SmallSat laboratory at NTNU. The satellite capable of capturing and processing of hyperspectral images will be equipped with ... -
Hardware-software intercommunication in reconfigurable systems
Endresen, Vegard Haugen (Master thesis, 2010)In this thesis hardware-software intercommunication in a reconfigurable system has been investigated based on a framework for run time reconfiguration. The goal has been to develop a fast and flexible link between applications ... -
High-level implementation of a partial DSP algorithm chain used in a digital radio using functional programming
Torsvik, Kristoffer Hove (Master thesis, 2016)This thesis investigates the advantages of using functional programming as a hardware description tool. The functional programming paradigm shares a lot of similarities with hardware, as it is highly parallel in nature and ... -
High-Level Synthesis for Application-Specific Integrated Circuit Implementation using LegUp
Holmefjord, Jørgen F (Master thesis, 2016)Low power and small area are becoming increasingly important and highly demanded in large System-on-Chip (SoC) designs, incorporating billions of transistors. This entails that the typical design methodology is no longer ... -
Implementering av GSM-R kommunikasjon
Moen, Thomas Andre (Master thesis, 2006)Jernbaneverket bygger i disse dager ut ett GSM-R nett som benyttes til nødkommunikasjon. I forbindelse med diplomoppgaven på NTNU har min oppgave vært å realisere ett system som benytte GSM-R nettet til å oversende meldinger ... -
Improving side channel attack resilience for IoT devices
Prestegård, Håkon (Master thesis, 2018)Security in Internet of Things (IoT) applications is more important than ever. New devices are pushed to the market every day. The world is, and will be more connected then ever before. This thesis focus side channel ... -
Instruction Set for Bit-Banging Operations - Increasing flexibility for low power communication
Solvang, Henrik Olav (Master thesis, 2016)A microcontroller can only offer a limited amount of communication interfaces. When designing an ASIC targeted for high volume production, flexibility must often give way to increased energy efficiency. The limitation in ... -
JPEG2000 Compression Software/Hardware Codesign
Bolstad, Lars Henrik (Master thesis, 2018)This report details development, verification and results for implementation of JPEG 2000 compression on a Zynq-7000~\cite{zynq7000} system-on-chip. Software/hardware co-development of the system is intended for on-board ... -
Konstruksjon av digital heltallsaritmetikk: Kompakte initialverditabeller for multiplikative divisjons algoritmer
Rognerud, Martin (Master thesis, 2007)Jeg har i denne oppgaven jobbet med digital heltallsaritmetikk, og da sett spesielt på feltet deling. Deling er en meget ressurskrevende opperasjon i digitalteknikk, det er derfor mye tid og areal å spare på å forbedre ... -
Konstruksjon av digital heltallsaritmetikk: Multiplikativ divisjon
Stafto, Karl Marius (Master thesis, 2008)Denne oppgaven beskriver hvilke algoritmer og metoder som kan benyttes til å utføre regneoperasjonen multiplikativ divisjon i maskinvare. Videre beskrives arkitekturen til de mest egnete metodene for å beregne divisorens ... -
Lossless video compression in an FPGA for reducing DDR memory bandwidth usage
Fagerheim, Fredrik Jacobsen (Master thesis, 2013)We show that a hardware implementation of a lossless image compression schemecan be used as means for lowering DDR memory bandwidth usage from a videostream. A prediction scheme based on LOCO-I is used to reduce correlative ... -
Low power/high performance dynamic reconfigurable filter-design
Bystrøm, Vebjørn (Master thesis, 2008)The main idea behind this thesis was to optimize the multipliers in a finite impulse response (FIR) filter. The project was chosen because digital filters are very common in digital signal processing and is an exciting ... -
Minimizing Latency in Stream-Based Compression with the use of FPGA Dynamic Partial Reconfiguration: Hardware Parallelism Analysis
Gerstle, Nicholas Olav (Master thesis, 2014)Dynamic partial reconfiguration is a relatively new technique that permits the reconfiguration of portions of an FPGA without stopping all on-chip logic. The confluence of the additional adaptability of dynamic partial ... -
Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions
Najafiuchevler, Bahram; Svarstad, Kjetil (Journal article; Peer reviewed, 2018)With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A ...