Prosthetic Device Communication Protocol
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00001 /***********************************************************************/ 00011 #ifndef MCP2515_CAN_CONTROL_H_ 00012 #define MCP2515_CAN_CONTROL_H_ 00013 00014 /* INCLUDES =========================================== */ 00015 //#include <stdint.h> 00016 00017 00018 /* PUBLIC TYPES =========================================== */ 00022 #define MSG_ENABLE ((uint8_t)(0)) 00023 #define SET_BIT 1 00024 #define CLR_BIT 0 00025 00026 00030 /* ================================= */ 00031 00032 /* MACRO DEFINES ================================= */ 00033 /* Macro defines for TXBnCTRL ================================= */ 00045 #define TXBCTRL_ABTF ((uint8_t)(6)) 00046 00049 #define TXBCTRL_MLOA ((uint8_t)(5)) 00050 00053 #define TXBCTRL_TXERR ((uint8_t)(4)) 00054 00056 #define TXBCTRL_TXREQ ((uint8_t)(3)) 00057 00059 #define TXBCTRL_TXP ((uint8_t)(0)) 00060 00061 00062 00063 /* Enum: MCP2515 - TXBnCTRL TXP */ 00066 typedef enum { 00067 TXBCTRL_TXP_LOWEST_MSG_PRIORITY = 0, 00068 TXBCTRL_TXP_LOW_INTERMEDIATE_MSG_PRIORITY, 00069 TXP_HIGH_INTERMEDIATE_MSG_PRIORITY, 00070 TXP_HIGHEST_MSG_PRIORITY 00071 } TXB_CONTROL_TXP; 00072 00076 /* ================================= */ 00077 00078 00079 00080 00081 /* Macro defines for RXB0CTRL ================================= */ 00090 #define RXB0CTRL_RXM1 ((uint8_t)(6)) 00091 00093 #define RXB0CTRL_RXM0 ((uint8_t)(5)) 00094 00096 #define RXB0CTRL_RXRTR ((uint8_t)(3)) 00097 00100 #define RXB0CTRL_BUKT ((uint8_t)(2)) 00101 00103 #define RXB0CTRL_BUKT1 ((uint8_t)(1)) 00104 00110 #define RXB0_FILHIT ((uint8_t)(0)) 00111 #define RXB0_FILHIT_MASK ((uint8_t)((1<<0))) 00112 00113 00114 /* Enum: MCP2515 - RXB0CTRL RXM */ 00117 typedef enum { 00118 RXB0CTRL_RXM_ALL_MSG_STAND_EXT_ID = 0, 00119 RXB0CTRL_RXM_ONLY_VALID_STAND_ID, 00120 RXB0CTRL_RXM_ONLY_VALID_EXT_ID, 00121 RXB0CTRL_RXM_TURN_OFF_FIL_MASK_ALL_MSG 00122 } RXB0_CONTROL_RXM; 00123 00124 00125 00126 00130 /* ================================= */ 00131 00132 00133 /* Macro defines for RXB1CTRL ================================= */ 00142 #define RXB1CTRL_RXM1 ((uint8_t)(6)) 00143 00145 #define RXB1CTRL_RXM0 ((uint8_t)(5)) 00146 00148 #define RXB1CTRL_RXRTR ((uint8_t)(3)) 00149 00159 #define RXB1CTRL_FILHIT_MASK ((uint8_t) ((1<<2)|(1<<1)|(1<<0))) 00160 00161 00162 /* Enum: MCP2515 - RXB1CTRL RXM */ 00165 typedef enum { 00166 RXB1CTRL_RXM_ALL_MSG_STAND_EXT_ID = 0, 00167 RXB1CTRL_RXM_ONLY_VALID_STAND_ID, 00168 RXB1CTRL_RXM_ONLY_VALID_EXT_ID, 00169 RXB1CTRL_RXM_TURN_OFF_FIL_MASK_ALL_MSG 00170 } RXB1_CONTROL_RXM; 00171 00175 /* ================================= */ 00176 00177 00178 00179 00180 /* Macro defines for RXBnDLC ================================= */ 00191 #define RXB_DLC_RTR ((uint8_t)(6)) 00192 00195 #define RXB_DLC_MASK ((uint8_t)((1<<3)|(1<<2)|(1<<1)|(1<<0))) 00196 00200 /* ================================= */ 00201 00202 00203 00204 00205 /* Macro defines for EFLG ================================= */ 00217 #define EFLG_RX1OVR ((uint8_t)(7)) 00218 00223 #define EFLG_RX0OVR ((uint8_t)(6)) 00224 00229 #define EFLG_TXBO ((uint8_t)(5)) 00230 00235 #define EFLG_TXEP ((uint8_t)(4)) 00236 00241 #define EFLG_RXEP ((uint8_t)(3)) 00242 00247 #define EFLG_TXWAR ((uint8_t)(2)) 00248 00253 #define EFLG_RXWAR ((uint8_t)(1)) 00254 00259 #define EFLG_EWARN ((uint8_t)(0)) 00260 00264 /* ================================= */ 00265 00266 00267 /* Macro defines for CANINTE ================================= */ 00280 #define CANINTE_MERRE ((uint8_t)(7)) 00281 00287 #define CANINTE_WAKIE ((uint8_t)(6)) 00288 00294 #define CANINTE_ERRIE ((uint8_t)(5)) 00295 00301 #define CANINTE_TX2IE ((uint8_t)(4)) 00302 00308 #define CANINTE_TX1IE ((uint8_t)(3)) 00309 00315 #define CANINTE_TX0IE ((uint8_t)(2)) 00316 00322 #define CANINTE_RX1IE ((uint8_t)(1)) 00323 00329 #define CANINTE_RX0IE ((uint8_t)(0)) 00330 00334 /* ================================= */ 00335 00336 /* Macro defines for CANINTF ================================= */ 00349 #define CANINTF_FLAG_MERRF ((uint8_t)(7)) 00350 00356 #define CANINTF_FLAG_WAKIF ((uint8_t)(6)) 00357 00363 #define CANINTF_FLAG_ERRIF ((uint8_t)(5)) 00364 00370 #define CANINTF_FLAG_TX2IF ((uint8_t)(4)) 00371 00377 #define CANINTF_FLAG_TX1IF ((uint8_t)(3)) 00378 00384 #define CANINTF_FLAG_TX0IF ((uint8_t)(2)) 00385 00391 #define CANINTF_FLAG_RX1IF ((uint8_t)(1)) 00392 00398 #define CANINTF_FLAG_RX0IF ((uint8_t)(0)) 00399 00403 /* ================================= */ 00404 00405 00406 00407 00408 00409 /* Macro defines for CANCTRL ================================= */ 00425 #define CANCTRL_REQOP_MASK ((uint8_t)( (1<<7)|(1<<6)|(1<<5) )) 00426 00429 #define CANCTRL_REQOP_SHIFT ((uint8_t)(5)) 00430 00431 00436 #define CANCTRL_ABAT ((uint8_t)(4)) 00437 00442 #define CANCTRL_OSM ((uint8_t)(3)) 00443 00448 #define CANCTRL_CLKEN ((uint8_t)(2)) 00449 00450 00457 #define CANCTRL_CLKPRE_MASK ((uint8_t)( (1<<1)|(1<<0) )) 00458 00459 00460 00461 /* Enum: MCP2515 - Operation Mode */ 00466 typedef enum { 00467 CANCTRL_REQOP_NORMAL = 0, 00468 CANCTRL_REQOP_SLEEP, 00469 CANCTRL_REQOP_LOOPBACK, 00470 CANCTRL_REQOP_LISTEN_ONLY, 00471 CANCTRL_REQOP_CONFIGURATION 00472 } CONTROL_REQOP; 00473 00474 00475 00476 /* Macro defines for CANSTAT ================================= */ 00492 #define CANSTAT_OPMOD_MASK ((uint8_t)( (1<<7)|(1<<6)|(1<<5) )) 00493 00494 00506 #define CANSTAT_ICOD_MASK ((uint8_t)( (1<<3)|(1<<2)|(1<<1) )) 00507 00508 00509 /* Enum: MCP2515 - OPMOD */ 00513 typedef enum { 00514 CANSTAT_OPMOD_NORMAL = 0, 00515 CANSTAT_OPMOD_SLEEP, 00516 CANSTAT_OPMOD_LOOPBACK, 00517 CANSTAT_OPMOD_LISTEN_ONLY, 00518 CANSTAT_OPMOD_CONFIGURATION 00519 } STATUS_OPMOD; 00520 00521 00525 /* ================================= */ 00526 00527 00528 00529 00530 00531 /* Register Addresses ================================= */ 00541 #define TXB0CTRL ((uint8_t)(0x30)) 00542 00546 #define TXB1CTRL ((uint8_t)(0x40)) 00547 00551 #define TXB2CTRL ((uint8_t)(0x50)) 00552 00556 #define TXRTSCTRL ((uint8_t)(0x0D)) 00557 00560 #define TXB0SIDH ((uint8_t)(0x31)) 00561 00564 #define TXB1SIDH ((uint8_t)(0x41)) 00565 00568 #define TXB2SIDH ((uint8_t)(0x51)) 00569 00570 00573 #define TXB0SIDL ((uint8_t)(0x32)) 00574 00577 #define TXB1SIDL ((uint8_t)(0x42)) 00578 00581 #define TXB2SIDL ((uint8_t)(0x52)) 00582 00583 00586 #define TXB0EID8 ((uint8_t)(0x33)) 00587 00590 #define TXB1EID8 ((uint8_t)(0x43)) 00591 00594 #define TXB2EID8 ((uint8_t)(0x53)) 00595 00598 #define TXB0EID0 ((uint8_t)(0x34)) 00599 00602 #define TXB1EID0 ((uint8_t)(0x44)) 00603 00606 #define TXB2EID0 ((uint8_t)(0x54)) 00607 00610 #define TXB0DLC ((uint8_t)(0x35)) 00611 00614 #define TXB1DLC ((uint8_t)(0x45)) 00615 00618 #define TXB2DLC ((uint8_t)(0x55)) 00619 00620 00621 00624 #define TXB0D0 ((uint8_t)(0x36)) 00625 00626 00629 #define TXB1D0 ((uint8_t)(0x46)) 00630 00631 00634 #define TXB2D0 ((uint8_t)(0x56)) 00635 00636 00637 00638 //* RECEIVE buffer addresses 00642 #define RXB0CTRL ((uint8_t)(0x60)) 00643 00647 #define RXB1CTRL ((uint8_t)(0x70)) 00648 00651 #define BFPCTRL ((uint8_t)(0x0C)) 00652 00655 #define RXB0SIDH ((uint8_t)(0x61)) 00656 #define RXB1SIDH ((uint8_t)(0x71)) 00657 00660 #define RXB0SIDL ((uint8_t)(0x62)) 00661 #define RXB1SIDL ((uint8_t)(0x72)) 00662 00665 #define RXB0EID8 ((uint8_t)(0x63)) 00666 #define RXB1EID8 ((uint8_t)(0x73)) 00667 00670 #define RXB0EID0 ((uint8_t)(0x64)) 00671 #define RXB1EID0 ((uint8_t)(0x74)) 00672 00676 #define RXB0DLC ((uint8_t)(0x65)) 00677 #define RXB1DLC ((uint8_t)(0x75)) 00678 00682 #define RXB0D0 ((uint8_t)(0x66)) 00683 00684 00688 #define RXB1D0 ((uint8_t)(0x76)) 00689 #define RXB1D1 ((uint8_t)(0x77)) 00690 #define RXB1D2 ((uint8_t)(0x78)) 00691 #define RXB1D3 ((uint8_t)(0x79)) 00692 #define RXB1D4 ((uint8_t)(0x7A)) 00693 #define RXB1D5 ((uint8_t)(0x7B)) 00694 #define RXB1D6 ((uint8_t)(0x7C)) 00695 #define RXB1D7 ((uint8_t)(0x7D)) 00696 00697 //* filters 00700 #define RXF0SIDH ((uint8_t)(0x00)) 00701 #define RXF1SIDH ((uint8_t)(0x04)) 00702 #define RXF2SIDH ((uint8_t)(0x08)) 00703 #define RXF3SIDH ((uint8_t)(0x10)) 00704 #define RXF4SIDH ((uint8_t)(0x14)) 00705 #define RXF5SIDH ((uint8_t)(0x18)) 00706 00709 #define RXF0SIDL ((uint8_t)(0x01)) 00710 #define RXF1SIDL ((uint8_t)(0x05)) 00711 #define RXF2SIDL ((uint8_t)(0x09)) 00712 #define RXF3SIDL ((uint8_t)(0x11)) 00713 #define RXF4SIDL ((uint8_t)(0x15)) 00714 #define RXF5SIDL ((uint8_t)(0x19)) 00715 00718 #define RXF0EID8 ((uint8_t)(0x02)) 00719 #define RXF1EID8 ((uint8_t)(0x06)) 00720 #define RXF2EID8 ((uint8_t)(0x0A)) 00721 #define RXF3EID8 ((uint8_t)(0x12)) 00722 #define RXF4EID8 ((uint8_t)(0x16)) 00723 #define RXF5EID8 ((uint8_t)(0x1A)) 00724 00727 #define RXF0EID0 ((uint8_t)(0x03)) 00728 #define RXF1EID0 ((uint8_t)(0x07)) 00729 #define RXF2EID0 ((uint8_t)(0x0B)) 00730 #define RXF3EID0 ((uint8_t)(0x13)) 00731 #define RXF4EID0 ((uint8_t)(0x17)) 00732 #define RXF5EID0 ((uint8_t)(0x1B)) 00733 00734 //* masks 00737 #define RXM0SIDH ((uint8_t)(0x20)) 00738 #define RXM1SIDH ((uint8_t)(0x24)) 00739 00742 #define RXM0SIDL ((uint8_t)(0x21)) 00743 #define RXM1SIDL ((uint8_t)(0x25)) 00744 00747 #define RXM0EID8 ((uint8_t)(0x22)) 00748 #define RXM1EID8 ((uint8_t)(0x26)) 00749 00752 #define RXM0EID0 ((uint8_t)(0x23)) 00753 #define RXM1EID0 ((uint8_t)(0x27)) 00754 00755 00756 00757 00758 //* BIT TIMING 00761 #define CNF1 ((uint8_t)(0x2A)) 00762 #define CNF2 ((uint8_t)(0x29)) 00763 #define CNF3 ((uint8_t)(0x28)) 00764 00765 00766 00767 //* ERROR and INTERRUPT handling 00771 #define TEC ((uint8_t)(0x1C)) 00772 00776 #define REC ((uint8_t)(0x1D)) 00777 00781 #define EFLG ((uint8_t)(0x2D)) 00782 00786 #define CANINTE ((uint8_t)(0x2B)) 00787 00791 #define CANINTF ((uint8_t)(0x2C)) 00792 00796 #define CANCTRL ((uint8_t)(0x0F)) 00797 00801 #define CANSTAT ((uint8_t)(0xE)) 00802 00803 00804 00809 /* ================================= */ 00810 00811 00812 00813 /* Control Addresses ================================= */ 00819 #define MCP_RESET 0xC0 00820 #define MCP_READ_CMD 0x03 00821 #define MCP_WRITE_CMD 0x02 00822 00823 #define MCP_RECEIVE_RXB0SIDH 0x90 00824 #define MCP_RECEIVE_RXB0D0 0x91 00825 #define MCP_RECEIVE_RXB1SIDH 0x92 00826 #define MCP_RECEIVE_RXB1D0 0x93 00827 00828 00829 #define MCP_LOAD_TXB0SIDH 0x40 00830 #define MCP_LOAD_TXB0D0 0x41 00831 #define MCP_LOAD_TXB1SIDH 0x42 00832 #define MCP_LOAD_TXB1D0 0x43 00833 #define MCP_LOAD_TXB2SIDH 0x44 00834 #define MCP_LOAD_TXB2D0 0x45 00835 00836 #define MCP_READ_STATUS 0xA0 00837 #define MCP_RX_STATUS 0xB0 00838 #define MPC_BIT_MODIFY 0x05 00839 00847 #define REG_OFFSET 0x10 00848 #define REC_REG_0 0 00849 #define REC_REG_1 1 00850 #define SEND_REG_0 0 00851 #define SEND_REG_1 1 00852 #define SEND_REG_2 2 00853 00854 00855 #endif