Defines
MCP2515_INTERRUPT_HANDLING

Macro defines for CANINTE - Can Interrupt Enable (documentation p. 50) More...

Defines

#define CANINTE_MERRE   ((uint8_t)(7))
 MERRE.
#define CANINTE_WAKIE   ((uint8_t)(6))
 WAKIE.
#define CANINTE_ERRIE   ((uint8_t)(5))
 ERRIE.
#define CANINTE_TX2IE   ((uint8_t)(4))
 TX2IE.
#define CANINTE_TX1IE   ((uint8_t)(3))
 TX1IE.
#define CANINTE_TX0IE   ((uint8_t)(2))
 TX0IE.
#define CANINTE_RX1IE   ((uint8_t)(1))
 RX1IE.
#define CANINTE_RX0IE   ((uint8_t)(0))
 RX0IE.
#define CANINTF_FLAG_MERRF   ((uint8_t)(7))
 Macro defines for CANINTF - Can Interrupt Flag (documentation p. 51)
#define CANINTF_FLAG_WAKIF   ((uint8_t)(6))
 WAKIE.
#define CANINTF_FLAG_ERRIF   ((uint8_t)(5))
 ERRIF.
#define CANINTF_FLAG_TX2IF   ((uint8_t)(4))
 TX2IF.
#define CANINTF_FLAG_TX1IF   ((uint8_t)(3))
 TX1IF.
#define CANINTF_FLAG_TX0IF   ((uint8_t)(2))
 TX0IF.
#define CANINTF_FLAG_RX1IF   ((uint8_t)(1))
 RX1IF.
#define CANINTF_FLAG_RX0IF   ((uint8_t)(0))
 RX0IF.

Detailed Description

Macro defines for CANINTE - Can Interrupt Enable (documentation p. 50)

Address: 2Bh

Author:
AZ

Define Documentation

#define CANINTE_ERRIE   ((uint8_t)(5))

ERRIE.

Error Interrupt Enable bit (multiple sources in EFLG register) 1 - Interrupt on EFLG error condition change 0 - Disabled

Attention:
R/W
#define CANINTE_MERRE   ((uint8_t)(7))

MERRE.

Message Error Interrupt Enable bit 1 - Interrupt on error during message reception or transmission 0 - Disabled

Attention:
R/W
#define CANINTE_RX0IE   ((uint8_t)(0))

RX0IE.

Receive Buffer 0 Full Interrupt Enable bit 1 - Interrupt when message received in RXB0 0 - Disabled

Attention:
R/W
#define CANINTE_RX1IE   ((uint8_t)(1))

RX1IE.

Receive Buffer 1 Full Interrupt Enable bit 1 - Interrupt when message received in RXB1 0 - Disabled

Attention:
R/W
#define CANINTE_TX0IE   ((uint8_t)(2))

TX0IE.

Transmit Buffer 0 Empty Interrupt Enable bit 1 - Interrupt on TXB0 becoming empty 0 - Disabled

Attention:
R/W
#define CANINTE_TX1IE   ((uint8_t)(3))

TX1IE.

Transmit Buffer 1 Empty Interrupt Enable bit 1 - Interrupt on TXB1 becoming empty 0 - Disabled

Attention:
R/W
#define CANINTE_TX2IE   ((uint8_t)(4))

TX2IE.

Transmit Buffer 2 Empty Interrupt Enable bit 1 - Interrupt on TXB2 becoming empty 0 - Disabled

Attention:
R/W
#define CANINTE_WAKIE   ((uint8_t)(6))

WAKIE.

WakeUp Interrupt Enable bit 1 - Interrupt on CAN bus activity 0 - Disabled

Attention:
R/W
#define CANINTF_FLAG_ERRIF   ((uint8_t)(5))

ERRIF.

Error Interrupt Flag bit (multiple sources in EFLG register) 1 - Interrupt pending (must be cleared by MCU to reset interrupt conditions) 0 - No interrupt pending

Attention:
R/W
#define CANINTF_FLAG_MERRF   ((uint8_t)(7))

Macro defines for CANINTF - Can Interrupt Flag (documentation p. 51)

Address: 2Ch

Author:
AZMERRF

Message Error Interrupt Flag bit 1 - Interrupt pending (must be cleared by MCU to reset interrupt conditions) 0 - No interrupt pending

Attention:
R/W
#define CANINTF_FLAG_RX0IF   ((uint8_t)(0))

RX0IF.

Receive Buffer 0 Full Interrupt Flag bit 1 - Interrupt pending (must be cleared by MCU to reset interrupt conditions) 0 - No interrupt pending

Attention:
R/W
#define CANINTF_FLAG_RX1IF   ((uint8_t)(1))

RX1IF.

Receive Buffer 1 Full Interrupt Flag bit 1 - Interrupt pending (must be cleared by MCU to reset interrupt conditions) 0 - No interrupt pending

Attention:
R/W
#define CANINTF_FLAG_TX0IF   ((uint8_t)(2))

TX0IF.

Transmit Buffer 0 Empty Interrupt Flag bit 1 - Interrupt pending (must be cleared by MCU to reset interrupt conditions) 0 - No interrupt pending

Attention:
R/W
#define CANINTF_FLAG_TX1IF   ((uint8_t)(3))

TX1IF.

Transmit Buffer 1 Empty Interrupt Flag bit 1 - Interrupt pending (must be cleared by MCU to reset interrupt conditions) 0 - No interrupt pending

Attention:
R/W
#define CANINTF_FLAG_TX2IF   ((uint8_t)(4))

TX2IF.

Transmit Buffer 2 Empty Interrupt Flag bit 1 - Interrupt pending (must be cleared by MCU to reset interrupt conditions) 0 - No interrupt pending

Attention:
R/W
#define CANINTF_FLAG_WAKIF   ((uint8_t)(6))

WAKIE.

WakeUp Interrupt Flag bit 1 - Interrupt pending (must be cleared by MCU to reset interrupt conditions) 0 - No interrupt pending

Attention:
R/W
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