Prosthetic Device Communication Protocol
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00001 /***********************************************************************/ 00027 #ifndef MICROCONTROLLER_MASKING_FILE_H_ 00028 #define MICROCONTROLLER_MASKING_FILE_H_ 00029 00030 00031 /* INCLUDE =========================================== */ 00036 //* place for microcontroller header file 00037 00038 00039 //* libraries from AVR Lib 00040 00043 #include <avr/io.h> 00044 00046 #include <avr/interrupt.h> 00047 00048 /* END OF INCLUDE =========================================== */ 00049 00050 00052 #define USE_AVR_LIB 1 00053 #define DONT_USE_AVR_LIB 0 00054 #define LIBRARY_MODE USE_AVR_LIB 00055 00056 #define USE_AT90USB1287 1 00057 #define MICROCONTROLLER USE_AT90USB1287 00058 00059 #define USE_INT_EEPROM 1 00060 #define USE_EXT_EEPROM 0 00061 #define EEPROM_TYPE USE_INT_EEPROM 00062 00063 //* TU MOZE INLINE????????????????? 00064 #define INT_ENABLE() (__asm__ __volatile__ ("sei" ::)) 00065 #define INT_DISABLE ( cli() ) 00066 00067 00068 00069 /* I/O =========================================== */ 00075 #if ( LIBRARY_MODE ) 00076 00077 00078 //* PIN A - port input pin 00079 #define PORT_INPUT_PIN_A PINA 00080 #define A7 7 00081 #define A6 6 00082 #define A5 5 00083 #define A4 4 00084 #define A3 3 00085 #define A2 2 00086 #define A1 1 00087 #define A0 0 00088 00089 //* DDRA - port direction 00090 #define DATA_DIR_REG_A DDRA 00091 00092 00093 //* PORTA if OUTPUT PORTreg set value, if INPUT - decide about pull-up resistors 00094 #define DATA_PORT_A PORTA 00095 00096 00097 00098 //* PINB - port input pin 00099 #define PORT_INPUT_PIN_B PINB 00100 #define B7 7 00101 #define B6 6 00102 #define B5 5 00103 #define B4 4 00104 #define B3 3 00105 #define B2 2 00106 #define B1 1 00107 #define B0 0 00108 00109 //* DDRB - port direction 00110 #define DATA_DIR_REG_B DDRB 00111 00112 //* PORTB 00113 #define DATA_PORT_B PORTB 00114 00115 00116 //* PINC - port input pin 00117 #define PORT_INPUT_PIN_C PINC 00118 #define C7 7 00119 #define C6 6 00120 #define C5 5 00121 #define C4 4 00122 #define C3 3 00123 #define C2 2 00124 #define C1 1 00125 #define C0 0 00126 00127 //* DDRC - port direction 00128 #define DATA_DIR_REG_C DDRC 00129 00130 //* PORTC if OUTPUT PORTreg set value, if INPUT - decide about pull-up resistors 00131 #define DATA_PORT_C PORTC 00132 00133 00134 00135 //* PIND - port input pin 00136 #define PORT_INPUT_PIN_D PIND 00137 #define D7 7 00138 #define D6 6 00139 #define D5 5 00140 #define D4 4 00141 #define D3 3 00142 #define D2 2 00143 #define D1 1 00144 #define D0 0 00145 00146 //* DDRD - port direction 00147 #define DATA_DIR_REG_D DDRD 00148 00149 //* PORTD if OUTPUT PORTreg set value, if INPUT - decide about pull-up resistors 00150 #define DATA_PORT_D PORTD 00151 00152 00153 #if ( MICROCONTROLLER == USE_AT90USB1287 ) 00154 00155 //* PINE - port input pin 00156 #define PORT_INPUT_PIN_E PINE 00157 #define E7 7 00158 #define E6 6 00159 #define E5 5 00160 #define E4 4 00161 #define E3 3 00162 #define E2 2 00163 #define E1 1 00164 #define E0 0 00165 00166 //* DDRE - port direction 00167 #define DATA_DIR_REG_E DDRE 00168 00169 //* PORTE if OUTPUT PORTreg set value, if INPUT - decide about pull-up resistors 00170 #define DATA_PORT_E PORTE 00171 00172 00173 //* PINF - port input pin 00174 #define PORT_INPUT_PIN_F PINF 00175 #define F7 7 00176 #define F6 6 00177 #define F5 5 00178 #define F4 4 00179 #define F3 3 00180 #define F2 2 00181 #define F1 1 00182 #define F0 0 00183 00184 //* DDRF - port direction 00185 #define DATA_DIR_REG_F DDRF 00186 00187 //* PORTF if OUTPUT PORTreg set value, if INPUT - decide about pull-up resistors 00188 00189 #endif 00190 #endif 00191 00194 /* ================================= */ 00195 00196 00197 /* TIMERS =========================================== */ 00203 #if ( LIBRARY_MODE == USE_AVR_LIB ) 00204 00206 #define TIMER_GTCCR GTCCR 00207 #define TIMER_TSM TSM 00208 #define TIMER_PSRASY TIMER_PSRASY 00209 #define TIMER_PSRSYNC PSRSYNC 00210 00211 00213 #define TIMER0_TCNT TCNT0 00214 #define TIMER0_TCNTL TCNT0L 00215 #define TIMER0_TCNTH TCNT0H 00216 00217 #define TIMER0_TCCR0A TCCR0A 00218 #define TIMER0_TCCR0B TCCR0B 00219 #define TIMER0_COM0A1 COM0A1 00220 #define TIMER0_COM0A0 COM0A0 00221 #define TIMER0_COM0B1 COM0B1 00222 #define TIMER0_COM0B0 COM0B0 00223 #define TIMER0_WGM02 WGM02 00224 #define TIMER0_WGM01 WGM01 00225 #define TIMER0_WGM00 WGM00 00226 #define TIMER0_TIFR0 TIFR0 00227 #define TIMER0_OCF0B OCF0B 00228 #define TIMER0_OCF0A OCF0A 00229 #define TIMER0_TOV0 TOV0 00230 #define TIMER0_FOC0A FOC0A 00231 #define TIMER0_FOC0B FOC0B 00232 00233 #define TIMER0_CS02 CS02 00234 #define TIMER0_CS01 CS01 00235 #define TIMER0_CS00 CS00 00236 00237 #define TIMER0_TIMSK0 TIMSK0 00238 #define TIMER0_OCIE0B OCIE0B 00239 #define TIMER0_OCIE0A OCIE0A 00240 #define TIMER0_TOIE0 TOIE0 00241 #define TIMER0_TOIE0 TOIE0 00242 00243 #define TIMER0_OCR0A OCR0A 00244 #define TIMER0_OCR0B OCR0B 00245 00247 #define TIMER1_TCNT TCNT1 00248 #define TIMER1_TCNTL TCNT1L 00249 #define TIMER1_TCNTH TCNT1H 00250 #define TIMER1_OCR1A OCR1A 00251 #define TIMER1_OCR1AL OCR1AL 00252 #define TIMER1_OCR1AH OCR1AH 00253 #define TIMER1_OCR1B OCR1B 00254 #define TIMER1_OCR1BL OCR1BL 00255 #define TIMER1_OCR1BH OCR1BH 00256 #define TIMER1_OCR1C OCR1C 00257 #define TIMER1_OCR1CL OCR1CL 00258 #define TIMER1_OCR1CH OCR1CH 00259 00260 00261 #define TIMER1_TIFR1 TIFR1 00262 #define TIMER1_ICF1 ICF1 00263 #define TIMER1_OCF1C OCF1C 00264 #define TIMER1_OCF1B OCF1B 00265 #define TIMER1_OCF1A OCF1A 00266 #define TIMER1_TOV1 TOV1 00267 00268 #define TIMER1_TCCR1A TCCR1A 00269 #define TIMER1_COM1A1 COM1A1 00270 #define TIMER1_COM1A0 COM1A0 00271 #define TIMER1_COM1B1 COM1B1 00272 #define TIMER1_COM1B0 COM1B0 00273 #define TIMER1_COM1C1 COM1C1 00274 #define TIMER1_COM1C0 COM1C0 00275 #define TIMER1_WGM11 WGM11 00276 #define TIMER1_WGM10 WGM10 00277 00278 #define TIMER1_TCCR1B TCCR1B 00279 #define TIMER1_ICNC1 ICNC1 00280 #define TIMER1_ICES1 ICES1 00281 #define TIMER1_WGM13 WGM13 00282 #define TIMER1_WGM12 WGM12 00283 #define TIMER1_CS12 CS12 00284 #define TIMER1_CS11 CS11 00285 #define TIMER1_CS10 CS10 00286 00287 #define TIMER1_TCCR1C TCCR1C 00288 #define TIMER1_FOC1A FOC1A 00289 #define TIMER1_FOC1B FOC1B 00290 #define TIMER1_FOC1C FOC1C 00291 00292 00294 #if ( MICROCONTROLLER == USE_AT90USB1287 ) 00295 00296 00298 #define TIMER2_TCNT TCNT2 00299 #define TIMER2_TCNTL TCNT2L 00300 #define TIMER2_TCNTH TCNT2H 00301 #define TIMER2_OCR2A OCR2A 00302 #define TIMER2_OCR2B OCR2B 00303 00304 #define TIMER2_TIFR2 TIFR2 00305 #define TIMER2_OCF2B OCF2B 00306 #define TIMER2_OCF2A OCF2A 00307 #define TIMER2_TOV2 TOV2 00308 00309 #define TIMER2_COM2A1 COM2A1 00310 #define TIMER2_COM2A0 COM2A0 00311 #define TIMER2_COM2B1 COM2B1 00312 #define TIMER2_COM2B0 COM2B0 00313 #define TIMER2_WGM21 WGM21 00314 #define TIMER2_WGM20 WGM20 00315 00316 #define TIMER2_FOC2A FOC2A 00317 #define TIMER2_FOC2B FOC2B 00318 #define TIMER2_WGM22 WGM22 00319 #define TIMER2_CS22 CS22 00320 #define TIMER2_CS21 CS21 00321 #define TIMER2_CS20 CS20 00322 00323 00325 #define TIMER3_TCNT TCNT3 00326 #define TIMER3_TCNTL TCNT3L 00327 #define TIMER3_TCNTH TCNT3H 00328 00329 #define TIMER3_TIFR3 TIFR3 00330 #define TIMER3_ICF3 ICF3 00331 #define TIMER3_OCF3C OCF3C 00332 #define TIMER3_OCF3B OCF3B 00333 #define TIMER3_OCF3A OCF3A 00334 #define TIMER3_TOV3 TOV3 00335 #define TIMER3_OCR3A OCF3A 00336 #define TIMER3_OCR3AL OCF3AL 00337 #define TIMER3_OCR3AH OCF3AH 00338 #define TIMER3_OCR3B OCF3B 00339 #define TIMER3_OCR3BL OCF3BL 00340 #define TIMER3_OCR3BH OCF3BH 00341 #define TIMER3_OCR3C OCF3C 00342 #define TIMER3_OCR3CL OCF3CL 00343 #define TIMER3_OCR3CH OCF3CH 00344 #define TIMER3_ICR3 ICR3 00345 #define TIMER3_ICR3L ICR3L 00346 #define TIMER3_ICR3H ICR3H 00347 #define TIMER3_TCCR3A TCCR3A 00348 #define TIMER3_TCCR3B TCCR3B 00349 #define TIMER3_TCCR3C TCCR3C 00350 00351 #define TIMER3_COM3A1 COM3A1 00352 #define TIMER3_COM3A0 COM3A0 00353 #define TIMER3_COM3B1 COM3B1 00354 #define TIMER3_COM3B0 COM3B0 00355 #define TIMER3_COM3C1 COM3C1 00356 #define TIMER3_COM3C0 COM3C0 00357 #define TIMER3_WGM31 WGM31 00358 #define TIMER3_WGM30 WGM30 00359 00360 #define TIMER3_ICNC3 ICNC3 00361 #define TIMER3_ICES3 ICES3 00362 #define TIMER3_WGM33 WGM33 00363 #define TIMER3_WGM32 WGM32 00364 #define TIMER3_CS32 CS32 00365 #define TIMER3_CS31 CS31 00366 #define TIMER3_CS30 CS30 00367 00368 #define TIMER3_FOC3A FOC3 00369 #define TIMER3_FOC3B FOC3B 00370 #define TIMER3_FOC3C FOC3C 00371 00372 #endif 00373 #endif 00374 00377 /* ================================= */ 00378 00379 00380 /* INTERRUPTS =========================================== */ 00386 #if ( LIBRARY_MODE ) 00387 //* Pin Change Interrupt Flag Register 00389 #define EXT_INT_PCIFR PCIFR 00390 00391 //* External Interrupt Flags 00393 #define EXT_INT_EIFR EIFR 00394 00395 #define EXT_INTF_7 INTF7 00396 #define EXT_INTF_6 INTF6 00397 #define EXT_INTF_5 INTF5 00398 #define EXT_INTF_4 INTF4 00399 #define EXT_INTF_3 INTF3 00400 #define EXT_INTF_2 INTF2 00401 #define EXT_INTF_1 INTF1 00402 #define EXT_INTF_0 INTF0 00403 00404 //* External Interrupt Request 00406 #define EXT_INT_EIMSK EIMSK 00407 00408 #define EXT_INT_7 INT7 00409 #define EXT_INT_6 INT6 00410 #define EXT_INT_5 INT5 00411 #define EXT_INT_4 INT4 00412 #define EXT_INT_3 INT3 00413 #define EXT_INT_2 INT2 00414 #define EXT_INT_1 INT1 00415 #define EXT_INT_0 INT0 00416 00418 #define INT_PCIFR PCIFR 00419 #define INT_PCIF0 PCIF0 00420 00422 #define INT_PCICR PCICR 00423 #define INT_PCIE0 PCIE0 00424 00426 #define INT_PCMSK0 PCMSK0 00427 #define INT_PCINT_7 PCINT7 00428 #define INT_PCINT_6 PCINT6 00429 #define INT_PCINT_5 PCINT5 00430 #define INT_PCINT_4 PCINT4 00431 #define INT_PCINT_3 PCINT3 00432 #define INT_PCINT_2 PCINT2 00433 #define INT_PCINT_1 PCINT1 00434 #define INT_PCINT_0 PCINT0 00435 00437 #define EXT_EICRA EICRA 00438 #define EICRA_ISC31 ISC31 00439 #define EICRA_ISC30 ISC30 00440 #define EICRA_ISC21 ISC21 00441 #define EICRA_ISC20 ISC20 00442 #define EICRA_ISC11 ISC11 00443 #define EICRA_ISC10 ISC10 00444 #define EICRA_ISC01 ISC01 00445 #define EICRA_ISC00 ISC00 00446 00448 #define EXT_EICRB EICRB 00449 #define EICRB_ISC71 ISC71 00450 #define EICRB_ISC70 ISC70 00451 #define EICRB_ISC61 ISC61 00452 #define EICRB_ISC60 ISC60 00453 #define EICRB_ISC51 ISC51 00454 #define EICRB_ISC50 ISC50 00455 #define EICRB_ISC41 ISC41 00456 #define EICRB_ISC40 ISC40 00457 00458 00459 #endif 00460 00463 /* ================================= */ 00464 00465 00466 00467 /* SPI =========================================== */ 00473 #if ( LIBRARY_MODE ) 00474 #if ( MICROCONTROLLER == USE_AT90USB1287 ) 00475 00476 //* SPI Control Register */ 00478 #define SPI_SPCR SPCR 00479 #define SPCR_SPIE SPIE 00480 #define SPCR_SPE SPE 00481 #define SPCR_DORD DORD 00482 #define SPCR_MSTR MSTR 00483 #define SPCR_CPOL CPOL 00484 #define SPCR_CPHA CPHA 00485 #define SPCR_SPR1 SPR1 00486 #define SPCR_SPR0 SPR0 00487 00488 //* SPI Status Register */ 00490 #define SPI_SPSR SPSR 00491 #define SPSR_SPIF SPIF 00492 #define SPSR_WCOL WCOL 00493 #define SPSR_SPI2X SPI2X 00494 00495 //* SPI Data Register */ 00497 #define SPI_SPDR SPDR 00498 #define SPI_SPI2X SPI2X 00499 00500 00501 #endif 00502 #endif 00503 00506 /* ================================= */ 00507 00508 00509 /* UART =========================================== */ 00514 #if ( LIBRARY_MODE ) 00515 #if ( MICROCONTROLLER == USE_AT90USB1287 ) 00516 00517 #define USART_UCSR1A UCSR1A 00518 #define UCSR1A_UDRE1 UDRE1 00519 00520 #define USART_UCSR1B UCSR1B 00521 #define UCSR1B_RXEN1 RXEN1 00522 #define UCSR1B_TXEN1 TXEN1 00523 00524 #define USART_UCSR1C UCSR1C 00525 #define UCSR1C_UCSZ10 UCSZ10 00526 #define UCSR1C_USBS1 USBS1 00527 00528 #define USART_UBRR1H UBRR1H 00529 #define USART_UBRR1L UBRR1L 00530 #define USART_UDR1 UDR1 00531 00532 #endif 00533 #endif 00534 00537 /* ================================= */ 00538 00539 00540 00541 /* WATCHDOG =========================================== */ 00547 #if ( LIBRARY_MODE ) 00548 #if ( MICROCONTROLLER == USE_AT90USB1287 ) 00549 00550 #define MCU_MCUSR MCUSR 00551 #define MCUSR_WDRF WDRF 00552 00553 //* WDT watchdog timer */ 00555 #define WDT_WDTCSR WDTCSR 00556 #define WDTCSR_WDIF WDIF 00557 #define WDTCSR_WDIE WDIE 00558 #define WDTCSR_WDP3 WDP3 00559 #define WDTCSR_WDCE WDCE 00560 #define WDTCSR_WDE WDE 00561 #define WDTCSR_WDP2 WDP2 00562 #define WDTCSR_WDP1 WDP1 00563 #define WDTCSR_WDP0 WDP0 00564 00565 #define WDT_64MS ( 1 << WDP1 ) 00566 #define WDT_125MS ( ( 1 << WDP1 ) | ( 1 << WDP0 ) ) 00567 #define WDT_250MS ( 1 << WDP2 ) 00568 #define WDT_500MS ( ( 1 << WDP2 ) | ( 1 << WDP0 ) ) 00569 #define WDT_1000MS ( ( 1 << WDP2 ) | ( 1 << WDP1 ) ) 00570 00571 #endif 00572 #endif 00573 00576 /* ================================= */ 00577 00578 00579 00580 00581 00582 /* EEPROM MEMORY =========================================== */ 00588 #if ( LIBRARY_MODE ) 00589 #if ( EEPROM_TYPE == USE_INT_EEPROM ) 00590 00591 //* EEPROM Control Register */ 00593 #define EEPROM_EECR EECR 00594 00595 //* EEPROM Programming Mode Bits */ 00597 #define EEPROM_EEPM1 EEPM1 00598 00599 //* EEPROM Programming Mode Bits */ 00601 #define EEPROM_EEPM0 EEPM0 00602 00603 //* EEPROM Ready Interrupt Enable */ 00605 #define EEPROM_EERIE EERIE 00606 00607 //* EEPROM Master Programming Enable */ 00609 #define EEPROM_EEMPE EEMPE 00610 00611 //* EEPROM Programming Enable */ 00613 #define EEPROM_EEPE EEPE 00614 00615 //* EEPROM Read Enable */ 00617 #define EEPROM_EERE EERE 00618 00619 //* EEPROM Data Register */ 00621 #define EEPROM_EEDR EEDR 00622 00623 //* EEPROM Address Register */ 00625 #define EEPROM_EEAR EEAR 00626 #define EEPROM_EEARL EEARL 00627 #define EEPROM_EEARH EEARH 00628 00629 #endif 00630 #endif 00631 00634 /* ================================= */ 00635 00636 00637 00638 /* INTERRUPT VECTORS =========================================== */ 00645 #if (LIBRARY_MODE) 00646 #if (MICROCONTROLLER == USE_AT90USB1287) 00647 00648 #define EXT_INT_EIFR EIFR 00649 00650 #define INT0_VECTOR INT0_vect 00651 #define INT1_VECTOR INT1_vect 00652 00653 #define INT2_VECTOR INT2_vect 00654 #define INT3_VECTOR INT3_vect 00655 #define INT4_VECTOR INT4_vect 00656 #define INT5_VECTOR INT5_vect 00657 #define INT6_VECTOR INT6_vect 00658 #define INT7_VECTOR INT7_vect 00659 00660 #define PCINT0_VECTOR PCINT0_vect 00661 #define USB_GEN_VECTOR USB_GEN_vect 00662 #define USB_COM_VECTOR USB_COM_vect 00663 #define WDT_VECT WDT_vect 00664 00665 #define TIMER2_COMPA_VECT TIMER2_COMPA_vect 00666 #define TIMER2_COMPB_VECT TIMER2_COMPB_vect 00667 #define TIMER2_OVF_VECT TIMER2_OVF_vect 00668 00669 #define TIMER1_CAPT_VECT TIMER1_CAPT_vect 00670 #define TIMER1_COMPA_VECT TIMER1_COMPA_vect 00671 #define TIMER1_COMPB_VECT TIMER1_COMPB_vect 00672 #define TIMER1_OVF_VECT TIMER1_OVF_vect 00673 00674 #define TIMER0_COMPA_VECT TIMER0_COMPA_vect 00675 #define TIMER0_COMPB_VECT TIMER0_COMPB_vect 00676 00677 #define TIMER0_OVF_VECT TIMER0_OVF_vect 00678 00679 #define SPI_STC_VECT SPI_STC_vect 00680 #define USART1_RX_VECT USART1_RX_vect 00681 #define USART1_UDRE_VECT USART1_UDRE_vect 00682 #define USART1_TX_VECT USART1_TX_vect 00683 00684 #define ANALOG_COMP_VECT ANALOG_COMP_vect 00685 00686 #define ADC_VECT ADC_vect 00687 #define EE_READY_VECT EE_READY_vect 00688 00689 #define TIMER3_CAPT_VECT TIMER3_CAPT_vect 00690 #define TIMER3_COMPA_VECT TIMER3_COMPA_vect 00691 #define TIMER3_COMPB_VECT TIMER3_COMPB_vect 00692 #define TIMER3_COMPC_VECT TIMER3_COMPC_vect 00693 #define TIMER3_OVF_VECT TIMER3_OVF_vect 00694 #define TWI_VECT TWI_vect 00695 00696 00697 #endif 00698 #endif 00699 00703 /* ================================= */ 00704 00705 00706 00707 00708 /* PUBLIC TYPES =========================================== */ 00717 /* SPI port specification */ 00718 #define HW_CS_MCP2515_PORT DATA_PORT_B 00719 #define HW_CS_MCP2515 B0 00720 #define HW_CS_MCP2515_DDR DATA_DIR_REG_B 00721 00722 #define HW_MISO_MCP2515 B3 00723 #define HW_MOSI_MCP2515 B2 00724 #define HW_MISO_MCP2515_DDR DATA_DIR_REG_B 00725 #define HW_MISO_MCP2515_PIN PORT_INPUT_PIN_B 00726 #define HW_MOSI_MCP2515_DDR DATA_DIR_REG_B 00727 #define HW_MOSI_MCP2515_PORT DATA_PORT_B 00728 00729 #define HW_SCK_MCP2515_DDR DATA_DIR_REG_B 00730 #define HW_SCK_MCP2515 B1 00731 00732 00733 #define ENABLE_SPI_INT 1 00734 #define SPI_INTERRUPT ENABLE_SPI_INT 00735 00736 00737 00739 /* Timer OCR - default not used*/ 00740 #define HW_TIMER_OCR_VALUE 255 00741 00742 00744 /* External interrupt port specification*/ 00745 #define HW_MCP_EXT_INT 0 00746 #define HW_MCP_EXT_INT_DDR DDRD 00747 #define HW_MCP_EXT_INT_PORT PORTD 00748 00749 00750 00752 /* User should decide (basing on processor resources which software interrupt... */ 00753 /* ... routine would like to use */ 00754 00755 /* Software interrupt basing on PIN CHANGE interrupt - implemented only for AT90USB1287 */ 00756 #define USE_SOFT_INT_PIN_CHANGE 0 00757 00758 /* Software interrupt basing on external interrupt adjusted to (output directed) pin change detection */ 00759 #define USE_SOFT_INT_EXTERNAL 1 00760 00761 #define CONFIG_SOFT_INTERRUPT_MODE USE_SOFT_INT_EXTERNAL 00762 00763 00764 /* Software int basing on Pin Change Interrupt handler */ 00765 #define HW_SOFT_INT_DDR DDRB 00766 #define HW_SOFT_INT_PORT PORTB 00767 #define HW_SOFT_INT_NUM PB4 00768 #define HW_SOFT_INT_TRIG INT_PCINT_4 00769 00770 00771 /* Software int basing on external interrupt of uC - be careful with number of interrupt ... 00772 ... to not destroy communication with CAN controller */ 00773 #define HW_SOFT_EXT_INT_DDR DDRE // D before change 00774 #define HW_SOFT_EXT_INT_PORT PORTE 00775 #define HW_SOFT_EXT_INT_1 PE4 00776 #define HW_SOFT_EXT_INT_2 PE5 00777 #define HW_SOFT_EXT_INT_TRIG PE5 00778 00779 #define INT_SENDING INT4_VECTOR 00780 #define INT_RECEIVING INT5_VECTOR 00781 00782 00783 #define TRIGGER_RECEIVING HW_SOFT_EXT_INT_2 00784 #define TRIGGER_SENDING HW_SOFT_EXT_INT_1 00785 00786 00787 00788 /* Configuration mode in which some capacity properties of the system ... 00789 ... can be checked */ 00790 #define CONFIG_DEBUG_CAPACITY 0 00791 00792 /* Configuration mode in which some informations are send through UART ... 00793 ... program like Terminal is needed */ 00794 #define CONFIG_DEBUG_UART_INFO 0 00795 00796 #define CONFIG_DEBUG_TEST_HLL 1 00797 00798 00799 /* Configuration mode in which some toggling diode while msg receiving and ... 00800 ... sending can be started */ 00801 #define CONFIG_DEBUG_LED_TOGGLING 0 00802 #define HW_PORT_LED PORTF 00803 #define HW_DDR_LED DDRF 00804 #define HW_PORT_LED0 PF0 00805 #define HW_PORT_LED1 PF1 00806 #define HW_PORT_LED2 PF2 00807 00808 00809 00810 /* Watchdog mode */ 00811 #define WDT_OFF 0 00812 #define WDT_ON 1 00813 #define WDT_MODE WDT_OFF 00814 00815 00816 /* UART - debugging */ 00817 #if ( CONFIG_DEBUG_UART_INFO ) 00818 #define F_CPU 16000000UL 00819 #define RS_BAUD 9600UL 00820 #define RS_UBRR ((F_CPU/16/RS_BAUD) - 1) 00821 #endif 00822 00823 /* FOR TESTING =================================================== */ 00824 #define DATA_TO_SEND_1 0x5 00825 #define DATA_TO_SEND_2 0xC4 00826 #define MODULE_ID 0x3D//0xAB 00827 #define MSG_ID 0x13D 00828 /* FOR TESTING =================================================== */ 00829 00830 00839 //* shift these enums into another file with MACROS for AT90usb1287 or whole AVR family 00840 00841 /* Enum: AT90USB1287 - EXT_SENSE_CONTROL */ 00844 typedef enum { 00845 EXT_TRIGGER_LOW_LEVEL = 0, 00846 EXT_TRIGGER_ANY_EDGE, 00847 EXT_TRIGGER_FALLING_EDGE, 00848 EXT_TRIGGER_RISING_EDGE 00849 } EXT_SENSE_CONTROL; 00850 00851 00852 #endif