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Register addresses for MCP2515. More...
Defines | |
#define | TXB0CTRL ((uint8_t)(0x30)) |
TXB0CTRL. | |
#define | TXB1CTRL ((uint8_t)(0x40)) |
TXB1CTRL. | |
#define | TXB2CTRL ((uint8_t)(0x50)) |
TXB2CTRL. | |
#define | TXRTSCTRL ((uint8_t)(0x0D)) |
TXRTSCTRL. | |
#define | TXB0SIDH ((uint8_t)(0x31)) |
TXB0SIDH. | |
#define | TXB1SIDH ((uint8_t)(0x41)) |
TXB1SIDH. | |
#define | TXB2SIDH ((uint8_t)(0x51)) |
TXB2SIDH. | |
#define | TXB0SIDL ((uint8_t)(0x32)) |
TXB0SIDL. | |
#define | TXB1SIDL ((uint8_t)(0x42)) |
TXB1SIDL. | |
#define | TXB2SIDL ((uint8_t)(0x52)) |
TXB2SIDL. | |
#define | TXB0EID8 ((uint8_t)(0x33)) |
TXB0EID8. | |
#define | TXB1EID8 ((uint8_t)(0x43)) |
TXB1EID8. | |
#define | TXB2EID8 ((uint8_t)(0x53)) |
TXB2EID8. | |
#define | TXB0EID0 ((uint8_t)(0x34)) |
TXB0EID0. | |
#define | TXB1EID0 ((uint8_t)(0x44)) |
TXB1EID0. | |
#define | TXB2EID0 ((uint8_t)(0x54)) |
TXB2EID0. | |
#define | TXB0DLC ((uint8_t)(0x35)) |
TXB0DLC. | |
#define | TXB1DLC ((uint8_t)(0x45)) |
TXB1DLC. | |
#define | TXB2DLC ((uint8_t)(0x55)) |
TXB2DLC. | |
#define | TXB0D0 ((uint8_t)(0x36)) |
TXB0Dx. | |
#define | TXB1D0 ((uint8_t)(0x46)) |
TXB1Dx. | |
#define | TXB2D0 ((uint8_t)(0x56)) |
TXB2Dx. | |
#define | RXB0CTRL ((uint8_t)(0x60)) |
RXB0CTRL. | |
#define | RXB1CTRL ((uint8_t)(0x70)) |
RXB1CTRL. | |
#define | BFPCTRL ((uint8_t)(0x0C)) |
BFPCTRL. | |
#define | RXB0SIDH ((uint8_t)(0x61)) |
RXBnSIDH. | |
#define | RXB1SIDH ((uint8_t)(0x71)) |
#define | RXB0SIDL ((uint8_t)(0x62)) |
RXBnSIDL. | |
#define | RXB1SIDL ((uint8_t)(0x72)) |
#define | RXB0EID8 ((uint8_t)(0x63)) |
RXBnEID8. | |
#define | RXB1EID8 ((uint8_t)(0x73)) |
#define | RXB0EID0 ((uint8_t)(0x64)) |
RXBnEID8. | |
#define | RXB1EID0 ((uint8_t)(0x74)) |
#define | RXB0DLC ((uint8_t)(0x65)) |
RXBnDLC. | |
#define | RXB1DLC ((uint8_t)(0x75)) |
#define | RXB0D0 ((uint8_t)(0x66)) |
RXB0Dx. | |
#define | RXB1D0 ((uint8_t)(0x76)) |
RXB1Dx. | |
#define | RXB1D1 ((uint8_t)(0x77)) |
#define | RXB1D2 ((uint8_t)(0x78)) |
#define | RXB1D3 ((uint8_t)(0x79)) |
#define | RXB1D4 ((uint8_t)(0x7A)) |
#define | RXB1D5 ((uint8_t)(0x7B)) |
#define | RXB1D6 ((uint8_t)(0x7C)) |
#define | RXB1D7 ((uint8_t)(0x7D)) |
#define | RXF0SIDH ((uint8_t)(0x00)) |
RXFnSIDH. | |
#define | RXF1SIDH ((uint8_t)(0x04)) |
#define | RXF2SIDH ((uint8_t)(0x08)) |
#define | RXF3SIDH ((uint8_t)(0x10)) |
#define | RXF4SIDH ((uint8_t)(0x14)) |
#define | RXF5SIDH ((uint8_t)(0x18)) |
#define | RXF0SIDL ((uint8_t)(0x01)) |
RXFnSIDL. | |
#define | RXF1SIDL ((uint8_t)(0x05)) |
#define | RXF2SIDL ((uint8_t)(0x09)) |
#define | RXF3SIDL ((uint8_t)(0x11)) |
#define | RXF4SIDL ((uint8_t)(0x15)) |
#define | RXF5SIDL ((uint8_t)(0x19)) |
#define | RXF0EID8 ((uint8_t)(0x02)) |
RXFnEID8. | |
#define | RXF1EID8 ((uint8_t)(0x06)) |
#define | RXF2EID8 ((uint8_t)(0x0A)) |
#define | RXF3EID8 ((uint8_t)(0x12)) |
#define | RXF4EID8 ((uint8_t)(0x16)) |
#define | RXF5EID8 ((uint8_t)(0x1A)) |
#define | RXF0EID0 ((uint8_t)(0x03)) |
RXFnEID0. | |
#define | RXF1EID0 ((uint8_t)(0x07)) |
#define | RXF2EID0 ((uint8_t)(0x0B)) |
#define | RXF3EID0 ((uint8_t)(0x13)) |
#define | RXF4EID0 ((uint8_t)(0x17)) |
#define | RXF5EID0 ((uint8_t)(0x1B)) |
#define | RXM0SIDH ((uint8_t)(0x20)) |
RXMnSIDH. | |
#define | RXM1SIDH ((uint8_t)(0x24)) |
#define | RXM0SIDL ((uint8_t)(0x21)) |
RXMnSIDL. | |
#define | RXM1SIDL ((uint8_t)(0x25)) |
#define | RXM0EID8 ((uint8_t)(0x22)) |
RXMnEID8. | |
#define | RXM1EID8 ((uint8_t)(0x26)) |
#define | RXM0EID0 ((uint8_t)(0x23)) |
RXMnEID0. | |
#define | RXM1EID0 ((uint8_t)(0x27)) |
#define | CNF1 ((uint8_t)(0x2A)) |
CNF. | |
#define | CNF2 ((uint8_t)(0x29)) |
#define | CNF3 ((uint8_t)(0x28)) |
#define | TEC ((uint8_t)(0x1C)) |
TEC. | |
#define | REC ((uint8_t)(0x1D)) |
REC. | |
#define | EFLG ((uint8_t)(0x2D)) |
EFLG. | |
#define | CANINTE ((uint8_t)(0x2B)) |
CANINTE. | |
#define | CANINTF ((uint8_t)(0x2C)) |
CANINTF. | |
#define | CANCTRL ((uint8_t)(0x0F)) |
CANCTRL. | |
#define | CANSTAT ((uint8_t)(0xE)) |
CANSTAT. |
Register addresses for MCP2515.
#define BFPCTRL ((uint8_t)(0x0C)) |
BFPCTRL.
RXnBF Pin Control and Status
#define CANCTRL ((uint8_t)(0x0F)) |
CANCTRL.
Can Control Register
#define CANINTE ((uint8_t)(0x2B)) |
CANINTE.
Can Interrupt Enable
#define CANINTF ((uint8_t)(0x2C)) |
CANINTF.
Can Interrupt Flag
#define CANSTAT ((uint8_t)(0xE)) |
CANSTAT.
Can Status Register
#define CNF1 ((uint8_t)(0x2A)) |
CNF.
Configuration registers
#define EFLG ((uint8_t)(0x2D)) |
EFLG.
Error Flag
#define REC ((uint8_t)(0x1D)) |
REC.
Receiver Error Counter
#define RXB0CTRL ((uint8_t)(0x60)) |
RXB0CTRL.
Receive Buffer 0 Control
#define RXB0D0 ((uint8_t)(0x66)) |
RXB0Dx.
Receive Buffer 0 Data Length Code
#define RXB0DLC ((uint8_t)(0x65)) |
RXBnDLC.
Receive Buffer n Data Length Code
#define RXB0EID0 ((uint8_t)(0x64)) |
RXBnEID8.
Receive Buffer n Extended Identifier Low
#define RXB0EID8 ((uint8_t)(0x63)) |
RXBnEID8.
Receive Buffer n Extended Identifier High
#define RXB0SIDH ((uint8_t)(0x61)) |
RXBnSIDH.
Receive Buffer n Standard Identifier High
#define RXB0SIDL ((uint8_t)(0x62)) |
RXBnSIDL.
Receive Buffer n Standard Identifier Low
#define RXB1CTRL ((uint8_t)(0x70)) |
RXB1CTRL.
Receive Buffer 1 Control
#define RXB1D0 ((uint8_t)(0x76)) |
RXB1Dx.
Receive Buffer 1 Data Length Code
#define RXF0EID0 ((uint8_t)(0x03)) |
RXFnEID0.
Filter n Extended Identifier Low
#define RXF0EID8 ((uint8_t)(0x02)) |
RXFnEID8.
Filter n Extended Identifier High
#define RXF0SIDH ((uint8_t)(0x00)) |
RXFnSIDH.
Filter n Standard Identifier High
#define RXF0SIDL ((uint8_t)(0x01)) |
RXFnSIDL.
Filter n Standard Identifier Low
#define RXM0EID0 ((uint8_t)(0x23)) |
RXMnEID0.
Mask n Extended Identifier Low
#define RXM0EID8 ((uint8_t)(0x22)) |
RXMnEID8.
Mask n Extended Identifier High
#define RXM0SIDH ((uint8_t)(0x20)) |
RXMnSIDH.
Mask n Standard Identifier High
#define RXM0SIDL ((uint8_t)(0x21)) |
RXMnSIDL.
Mask n Standard Identifier Low
#define TEC ((uint8_t)(0x1C)) |
TEC.
Transmit Error Counter
#define TXB0CTRL ((uint8_t)(0x30)) |
TXB0CTRL.
Transmit Buffer 0 Control Register
#define TXB0D0 ((uint8_t)(0x36)) |
TXB0Dx.
Transmit Buffer 0 Data Byte 0-7
#define TXB0DLC ((uint8_t)(0x35)) |
TXB0DLC.
Transmit Buffer 0 Data Length Code
#define TXB0EID0 ((uint8_t)(0x34)) |
TXB0EID0.
Transmit Buffer 0 Extended Identifier Low
#define TXB0EID8 ((uint8_t)(0x33)) |
TXB0EID8.
Transmit Buffer 0 Extended Identifier High
#define TXB0SIDH ((uint8_t)(0x31)) |
TXB0SIDH.
Transmit Buffer 0 Standard Identifier High
#define TXB0SIDL ((uint8_t)(0x32)) |
TXB0SIDL.
Transmit Buffer 0 Standard Identifier Low
#define TXB1CTRL ((uint8_t)(0x40)) |
TXB1CTRL.
Transmit Buffer 1 Control Register
#define TXB1D0 ((uint8_t)(0x46)) |
TXB1Dx.
Transmit Buffer 1 Data Byte 0-7
#define TXB1DLC ((uint8_t)(0x45)) |
TXB1DLC.
Transmit Buffer 1 Data Length Code
#define TXB1EID0 ((uint8_t)(0x44)) |
TXB1EID0.
Transmit Buffer 1 Extended Identifier Low
#define TXB1EID8 ((uint8_t)(0x43)) |
TXB1EID8.
Transmit Buffer 1 Extended Identifier High
#define TXB1SIDH ((uint8_t)(0x41)) |
TXB1SIDH.
Transmit Buffer 1 Standard Identifier High
#define TXB1SIDL ((uint8_t)(0x42)) |
TXB1SIDL.
Transmit Buffer 1 Standard Identifier Low
#define TXB2CTRL ((uint8_t)(0x50)) |
TXB2CTRL.
Transmit Buffer 2 Control Register
#define TXB2D0 ((uint8_t)(0x56)) |
TXB2Dx.
Transmit Buffer 2 Data Byte 0-7
#define TXB2DLC ((uint8_t)(0x55)) |
TXB2DLC.
Transmit Buffer 2 Data Length Code
#define TXB2EID0 ((uint8_t)(0x54)) |
TXB2EID0.
Transmit Buffer 2 Extended Identifier Low
#define TXB2EID8 ((uint8_t)(0x53)) |
TXB2EID8.
Transmit Buffer 2 Extended Identifier High
#define TXB2SIDH ((uint8_t)(0x51)) |
TXB2SIDH.
Transmit Buffer 2 Standard Identifier High
#define TXB2SIDL ((uint8_t)(0x52)) |
TXB2SIDL.
Transmit Buffer 2 Standard Identifier Low
#define TXRTSCTRL ((uint8_t)(0x0D)) |
TXRTSCTRL.
TXnRTS Pin Control and Status Register