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Contains functions prototype for PDCP protocol. More...
Go to the source code of this file.
Defines | |
#define | BUS_ARBITRATOR 1 |
#define | BUS_DEVICE 0 |
#define | CONFIG_BUS_MODE BUS_DEVICE |
#define | CONFIG_USE_MALLOC 1 |
#define | CONFIG_NUM_CANMSG 8 |
#define | CONFIG_TRIE_BITS_PER_NODE 2 |
#define | CONFIG_VENDOR_ID 1 |
#define | CONFIG_PRODUCT_ID 2 |
#define | CONFIG_SERIAL_NUMBER 3 |
#define | F_CPU 16000000 |
#define | HW_CS_MCP2515_PORT DATA_PORT_B |
#define | HW_CS_MCP2515 B0 |
#define | HW_CS_MCP2515_DDR DATA_DIR_REG_B |
#define | HW_MISO_MCP2515 B3 |
#define | HW_MOSI_MCP2515 B2 |
#define | HW_MISO_MCP2515_DDR DATA_DIR_REG_B |
#define | HW_MISO_MCP2515_PIN PORT_INPUT_PIN_B |
#define | HW_MOSI_MCP2515_DDR DATA_DIR_REG_B |
#define | HW_MOSI_MCP2515_PORT DATA_PORT_B |
#define | HW_SCK_MCP2515_DDR DATA_DIR_REG_B |
#define | HW_SCK_MCP2515 B1 |
#define | ENABLE_SPI_INT 1 |
#define | SPI_INTERRUPT ENABLE_SPI_INT |
#define | HW_MCP_EXT_INT 0 |
#define | HW_MCP_EXT_INT_DDR DDRD |
#define | HW_MCP_EXT_INT_PORT PORTD |
#define | HW_SOFT_EXT_INT_DDR DDRE |
#define | HW_SOFT_EXT_INT_PORT PORTE |
#define | HW_SOFT_EXT_INT_1 PE4 |
#define | HW_SOFT_EXT_INT_2 PE5 |
#define | INT_SENDING INT4_VECTOR |
#define | INT_RECEIVING INT5_VECTOR |
#define | INT_SENDING_NUM 4 |
#define | INT_RECEIVING_NUM 5 |
#define | TRIGGER_RECEIVING HW_SOFT_EXT_INT_2 |
#define | TRIGGER_SENDING HW_SOFT_EXT_INT_1 |
#define | WDT_OFF 0 |
#define | WDT_ON 1 |
#define | WDT_MODE WDT_OFF |
#define | CONFIG_DEBUG_CAPACITY 0 |
#define | CONFIG_DEBUG_UART_INFO 1 |
#define | CONFIG_DEBUG_TEST_HLL 1 |
#define | MSG_AMOUNT_TEST 10000 |
#define | CONFIG_DEBUG_LED_TOGGLING 0 |
#define | HW_PORT_LED PORTF |
#define | HW_DDR_LED DDRF |
#define | HW_PORT_LED0 PF0 |
#define | HW_PORT_LED1 PF1 |
#define | HW_PORT_LED2 PF2 |
#define | CONFIG_TESTING_HAL 0 |
#define | F_CPU 16000000UL |
#define | RS_BAUD 9600UL |
#define | RS_UBRR ((F_CPU/16/RS_BAUD) - 1) |
#define | DEVICE_DEF_ID 0xFF |
#define | ARB_DEF_ID 0x00 |
#define | DATA_TO_SEND_1 0x5 |
Contains functions prototype for PDCP protocol.
#define ARB_DEF_ID 0x00 |
Arbitrator default ID
#define BUS_ARBITRATOR 1 |
What type of device are we? See PDCP documentation: Message Mode Field
#define CONFIG_DEBUG_CAPACITY 0 |
CONFIGURATION modes External interrupt port specification
#define CONFIG_DEBUG_TEST_HLL 1 |
Configuration mode in which HLL is tested
#define CONFIG_DEBUG_UART_INFO 1 |
Configuration mode in which some informations are sent through UART
#define CONFIG_NUM_CANMSG 8 |
Number of CAN messages reserved in the memory pool of the High Level Layer, shared by all sockets.
#define CONFIG_TESTING_HAL 0 |
Configuration mode in which HAL is tested
#define CONFIG_TRIE_BITS_PER_NODE 2 |
The height of the tree used for indexing node ids in arbitrator is 8 divided by this number.
#define CONFIG_VENDOR_ID 1 |
Used in the Bind request.
#define DEVICE_DEF_ID 0xFF |
Device default ID
#define HW_CS_MCP2515_PORT DATA_PORT_B |
SPI properties for MCP2515 SPI port specification
#define HW_MCP_EXT_INT 0 |
EXTERNAL interrupt External interrupt port specification
External interrupt - number of interrupt
#define HW_MCP_EXT_INT_DDR DDRD |
External interrupt - port direction
#define HW_MCP_EXT_INT_PORT PORTD |
External interrupt - port number
#define HW_SOFT_EXT_INT_1 PE4 |
Software interrupt 1 - port number
#define HW_SOFT_EXT_INT_2 PE5 |
Software interrupt 2 - port number
#define HW_SOFT_EXT_INT_DDR DDRE |
EXTERNAL interrupt as SOFTWARE interrupt Software int basing on external interrupt of uC - be careful with number of interrupt ... ... to not destroy communication with CAN controller
Software interrupt - port direction
#define HW_SOFT_EXT_INT_PORT PORTE |
Software interrupt - port value
#define INT_RECEIVING INT5_VECTOR |
Determinates number of interrupt routine responsible for message receiving
#define INT_RECEIVING_NUM 5 |
Determinates number of interrupt routine responsible for message receiving
#define INT_SENDING INT4_VECTOR |
Determinates vector of interrupt routine responsible for message sending
#define INT_SENDING_NUM 4 |
Determinates number of interrupt routine responsible for message sending
#define MSG_AMOUNT_TEST 10000 |
Number of messages for HAL testing
#define TRIGGER_RECEIVING HW_SOFT_EXT_INT_2 |
It determines port responsible for triggering receiving mechanism
#define TRIGGER_SENDING HW_SOFT_EXT_INT_1 |
It determines port responsible for triggering sending mechanism
#define WDT_MODE WDT_OFF |
WATCHDOG Properties
Watchdog timer ON/OFF