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00027 #ifndef UC_MASK_FILE_H_
00028 #define UC_MASK_FILE_H_
00029
00030
00031
00036
00037
00038
00039
00041 #include <avr/io.h>
00042
00044 #include <avr/interrupt.h>
00045
00047 #include "config.h"
00048
00049
00050
00051
00054 #define USE_AT90USB1287 1
00055 #define MICROCONTROLLER USE_AT90USB1287
00056
00057
00058
00059
00060
00067
00068 #define PORT_INPUT_PIN_A PINA
00069 #define A7 7
00070 #define A6 6
00071 #define A5 5
00072 #define A4 4
00073 #define A3 3
00074 #define A2 2
00075 #define A1 1
00076 #define A0 0
00077
00078
00079 #define DATA_DIR_REG_A DDRA
00080
00081
00082
00083 #define DATA_PORT_A PORTA
00084
00085
00086
00087
00088 #define PORT_INPUT_PIN_B PINB
00089 #define B7 7
00090 #define B6 6
00091 #define B5 5
00092 #define B4 4
00093 #define B3 3
00094 #define B2 2
00095 #define B1 1
00096 #define B0 0
00097
00098
00099 #define DATA_DIR_REG_B DDRB
00100
00101
00102 #define DATA_PORT_B PORTB
00103
00104
00105
00106 #define PORT_INPUT_PIN_C PINC
00107 #define C7 7
00108 #define C6 6
00109 #define C5 5
00110 #define C4 4
00111 #define C3 3
00112 #define C2 2
00113 #define C1 1
00114 #define C0 0
00115
00116
00117 #define DATA_DIR_REG_C DDRC
00118
00119
00120 #define DATA_PORT_C PORTC
00121
00122
00123
00124
00125 #define PORT_INPUT_PIN_D PIND
00126 #define D7 7
00127 #define D6 6
00128 #define D5 5
00129 #define D4 4
00130 #define D3 3
00131 #define D2 2
00132 #define D1 1
00133 #define D0 0
00134
00135
00136 #define DATA_DIR_REG_D DDRD
00137
00138
00139 #define DATA_PORT_D PORTD
00140
00141
00142 #if ( MICROCONTROLLER == USE_AT90USB1287 )
00143
00144
00145 #define PORT_INPUT_PIN_E PINE
00146 #define E7 7
00147 #define E6 6
00148 #define E5 5
00149 #define E4 4
00150 #define E3 3
00151 #define E2 2
00152 #define E1 1
00153 #define E0 0
00154
00155
00156 #define DATA_DIR_REG_E DDRE
00157
00158
00159 #define DATA_PORT_E PORTE
00160
00161
00162
00163 #define PORT_INPUT_PIN_F PINF
00164 #define F7 7
00165 #define F6 6
00166 #define F5 5
00167 #define F4 4
00168 #define F3 3
00169 #define F2 2
00170 #define F1 1
00171 #define F0 0
00172
00173
00174 #define DATA_DIR_REG_F DDRF
00175
00176
00177
00178 #endif
00179
00182
00183
00184
00185
00192 #define TIMER_GTCCR GTCCR
00193 #define TIMER_TSM TSM
00194 #define TIMER_PSRASY TIMER_PSRASY
00195 #define TIMER_PSRSYNC PSRSYNC
00196
00197
00199 #define TIMER0_TCNT TCNT0
00200 #define TIMER0_TCNTL TCNT0L
00201 #define TIMER0_TCNTH TCNT0H
00202
00203 #define TIMER0_TCCR0A TCCR0A
00204 #define TIMER0_TCCR0B TCCR0B
00205 #define TIMER0_COM0A1 COM0A1
00206 #define TIMER0_COM0A0 COM0A0
00207 #define TIMER0_COM0B1 COM0B1
00208 #define TIMER0_COM0B0 COM0B0
00209 #define TIMER0_WGM02 WGM02
00210 #define TIMER0_WGM01 WGM01
00211 #define TIMER0_WGM00 WGM00
00212 #define TIMER0_TIFR0 TIFR0
00213 #define TIMER0_OCF0B OCF0B
00214 #define TIMER0_OCF0A OCF0A
00215 #define TIMER0_TOV0 TOV0
00216 #define TIMER0_FOC0A FOC0A
00217 #define TIMER0_FOC0B FOC0B
00218
00219 #define TIMER0_CS02 CS02
00220 #define TIMER0_CS01 CS01
00221 #define TIMER0_CS00 CS00
00222
00223 #define TIMER0_TIMSK0 TIMSK0
00224 #define TIMER0_OCIE0B OCIE0B
00225 #define TIMER0_OCIE0A OCIE0A
00226 #define TIMER0_TOIE0 TOIE0
00227 #define TIMER0_TOIE0 TOIE0
00228
00229 #define TIMER0_OCR0A OCR0A
00230 #define TIMER0_OCR0B OCR0B
00231
00233 #define TIMER1_TCNT TCNT1
00234 #define TIMER1_TCNTL TCNT1L
00235 #define TIMER1_TCNTH TCNT1H
00236 #define TIMER1_OCR1A OCR1A
00237 #define TIMER1_OCR1AL OCR1AL
00238 #define TIMER1_OCR1AH OCR1AH
00239 #define TIMER1_OCR1B OCR1B
00240 #define TIMER1_OCR1BL OCR1BL
00241 #define TIMER1_OCR1BH OCR1BH
00242 #define TIMER1_OCR1C OCR1C
00243 #define TIMER1_OCR1CL OCR1CL
00244 #define TIMER1_OCR1CH OCR1CH
00245
00246
00247 #define TIMER1_TIFR1 TIFR1
00248 #define TIMER1_ICF1 ICF1
00249 #define TIMER1_OCF1C OCF1C
00250 #define TIMER1_OCF1B OCF1B
00251 #define TIMER1_OCF1A OCF1A
00252 #define TIMER1_TOV1 TOV1
00253
00254 #define TIMER1_TCCR1A TCCR1A
00255 #define TIMER1_COM1A1 COM1A1
00256 #define TIMER1_COM1A0 COM1A0
00257 #define TIMER1_COM1B1 COM1B1
00258 #define TIMER1_COM1B0 COM1B0
00259 #define TIMER1_COM1C1 COM1C1
00260 #define TIMER1_COM1C0 COM1C0
00261 #define TIMER1_WGM11 WGM11
00262 #define TIMER1_WGM10 WGM10
00263
00264 #define TIMER1_TCCR1B TCCR1B
00265 #define TIMER1_ICNC1 ICNC1
00266 #define TIMER1_ICES1 ICES1
00267 #define TIMER1_WGM13 WGM13
00268 #define TIMER1_WGM12 WGM12
00269 #define TIMER1_CS12 CS12
00270 #define TIMER1_CS11 CS11
00271 #define TIMER1_CS10 CS10
00272
00273 #define TIMER1_TCCR1C TCCR1C
00274 #define TIMER1_FOC1A FOC1A
00275 #define TIMER1_FOC1B FOC1B
00276 #define TIMER1_FOC1C FOC1C
00277
00278
00280 #if ( MICROCONTROLLER == USE_AT90USB1287 )
00281
00282
00284 #define TIMER2_TCNT TCNT2
00285 #define TIMER2_TCNTL TCNT2L
00286 #define TIMER2_TCNTH TCNT2H
00287 #define TIMER2_OCR2A OCR2A
00288 #define TIMER2_OCR2B OCR2B
00289
00290 #define TIMER2_TIFR2 TIFR2
00291 #define TIMER2_OCF2B OCF2B
00292 #define TIMER2_OCF2A OCF2A
00293 #define TIMER2_TOV2 TOV2
00294
00295 #define TIMER2_COM2A1 COM2A1
00296 #define TIMER2_COM2A0 COM2A0
00297 #define TIMER2_COM2B1 COM2B1
00298 #define TIMER2_COM2B0 COM2B0
00299 #define TIMER2_WGM21 WGM21
00300 #define TIMER2_WGM20 WGM20
00301
00302 #define TIMER2_FOC2A FOC2A
00303 #define TIMER2_FOC2B FOC2B
00304 #define TIMER2_WGM22 WGM22
00305 #define TIMER2_CS22 CS22
00306 #define TIMER2_CS21 CS21
00307 #define TIMER2_CS20 CS20
00308
00309
00311 #define TIMER3_TCNT TCNT3
00312 #define TIMER3_TCNTL TCNT3L
00313 #define TIMER3_TCNTH TCNT3H
00314
00315 #define TIMER3_TIFR3 TIFR3
00316 #define TIMER3_ICF3 ICF3
00317 #define TIMER3_OCF3C OCF3C
00318 #define TIMER3_OCF3B OCF3B
00319 #define TIMER3_OCF3A OCF3A
00320 #define TIMER3_TOV3 TOV3
00321 #define TIMER3_OCR3A OCF3A
00322 #define TIMER3_OCR3AL OCF3AL
00323 #define TIMER3_OCR3AH OCF3AH
00324 #define TIMER3_OCR3B OCF3B
00325 #define TIMER3_OCR3BL OCF3BL
00326 #define TIMER3_OCR3BH OCF3BH
00327 #define TIMER3_OCR3C OCF3C
00328 #define TIMER3_OCR3CL OCF3CL
00329 #define TIMER3_OCR3CH OCF3CH
00330 #define TIMER3_ICR3 ICR3
00331 #define TIMER3_ICR3L ICR3L
00332 #define TIMER3_ICR3H ICR3H
00333 #define TIMER3_TCCR3A TCCR3A
00334 #define TIMER3_TCCR3B TCCR3B
00335 #define TIMER3_TCCR3C TCCR3C
00336
00337 #define TIMER3_COM3A1 COM3A1
00338 #define TIMER3_COM3A0 COM3A0
00339 #define TIMER3_COM3B1 COM3B1
00340 #define TIMER3_COM3B0 COM3B0
00341 #define TIMER3_COM3C1 COM3C1
00342 #define TIMER3_COM3C0 COM3C0
00343 #define TIMER3_WGM31 WGM31
00344 #define TIMER3_WGM30 WGM30
00345
00346 #define TIMER3_ICNC3 ICNC3
00347 #define TIMER3_ICES3 ICES3
00348 #define TIMER3_WGM33 WGM33
00349 #define TIMER3_WGM32 WGM32
00350 #define TIMER3_CS32 CS32
00351 #define TIMER3_CS31 CS31
00352 #define TIMER3_CS30 CS30
00353
00354 #define TIMER3_FOC3A FOC3
00355 #define TIMER3_FOC3B FOC3B
00356 #define TIMER3_FOC3C FOC3C
00357
00358 #endif
00359
00363
00364
00365
00366
00371
00373 #define EXT_INT_PCIFR PCIFR
00374
00375
00377 #define EXT_INT_EIFR EIFR
00378
00379 #define EXT_INTF_7 INTF7
00380 #define EXT_INTF_6 INTF6
00381 #define EXT_INTF_5 INTF5
00382 #define EXT_INTF_4 INTF4
00383 #define EXT_INTF_3 INTF3
00384 #define EXT_INTF_2 INTF2
00385 #define EXT_INTF_1 INTF1
00386 #define EXT_INTF_0 INTF0
00387
00388
00390 #define EXT_INT_EIMSK EIMSK
00391
00392 #define EXT_INT_7 INT7
00393 #define EXT_INT_6 INT6
00394 #define EXT_INT_5 INT5
00395 #define EXT_INT_4 INT4
00396 #define EXT_INT_3 INT3
00397 #define EXT_INT_2 INT2
00398 #define EXT_INT_1 INT1
00399 #define EXT_INT_0 INT0
00400
00402 #define INT_PCIFR PCIFR
00403 #define INT_PCIF0 PCIF0
00404
00406 #define INT_PCICR PCICR
00407 #define INT_PCIE0 PCIE0
00408
00410 #define INT_PCMSK0 PCMSK0
00411 #define INT_PCINT_7 PCINT7
00412 #define INT_PCINT_6 PCINT6
00413 #define INT_PCINT_5 PCINT5
00414 #define INT_PCINT_4 PCINT4
00415 #define INT_PCINT_3 PCINT3
00416 #define INT_PCINT_2 PCINT2
00417 #define INT_PCINT_1 PCINT1
00418 #define INT_PCINT_0 PCINT0
00419
00421 #define EXT_EICRA EICRA
00422 #define EICRA_ISC31 ISC31
00423 #define EICRA_ISC30 ISC30
00424 #define EICRA_ISC21 ISC21
00425 #define EICRA_ISC20 ISC20
00426 #define EICRA_ISC11 ISC11
00427 #define EICRA_ISC10 ISC10
00428 #define EICRA_ISC01 ISC01
00429 #define EICRA_ISC00 ISC00
00430
00432 #define EXT_EICRB EICRB
00433 #define EICRB_ISC71 ISC71
00434 #define EICRB_ISC70 ISC70
00435 #define EICRB_ISC61 ISC61
00436 #define EICRB_ISC60 ISC60
00437 #define EICRB_ISC51 ISC51
00438 #define EICRB_ISC50 ISC50
00439 #define EICRB_ISC41 ISC41
00440 #define EICRB_ISC40 ISC40
00441
00442
00446
00447
00448
00449
00450
00456
00458 #define SPI_SPCR SPCR
00459 #define SPCR_SPIE SPIE
00460 #define SPCR_SPE SPE
00461 #define SPCR_DORD DORD
00462 #define SPCR_MSTR MSTR
00463 #define SPCR_CPOL CPOL
00464 #define SPCR_CPHA CPHA
00465 #define SPCR_SPR1 SPR1
00466 #define SPCR_SPR0 SPR0
00467
00468
00470 #define SPI_SPSR SPSR
00471 #define SPSR_SPIF SPIF
00472 #define SPSR_WCOL WCOL
00473 #define SPSR_SPI2X SPI2X
00474
00475
00477 #define SPI_SPDR SPDR
00478 #define SPI_SPI2X SPI2X
00479
00483
00484
00485
00486
00492 #define USART_UCSR1A UCSR1A
00493 #define UCSR1A_UDRE1 UDRE1
00494
00495 #define USART_UCSR1B UCSR1B
00496 #define UCSR1B_RXEN1 RXEN1
00497 #define UCSR1B_TXEN1 TXEN1
00498
00499 #define USART_UCSR1C UCSR1C
00500 #define UCSR1C_UCSZ10 UCSZ10
00501 #define UCSR1C_USBS1 USBS1
00502
00503 #define USART_UBRR1H UBRR1H
00504 #define USART_UBRR1L UBRR1L
00505 #define USART_UDR1 UDR1
00506
00510
00511
00512
00513
00514
00520 #define MCU_MCUSR MCUSR
00521 #define MCUSR_WDRF WDRF
00522
00523
00525 #define WDT_WDTCSR WDTCSR
00526 #define WDTCSR_WDIF WDIF
00527 #define WDTCSR_WDIE WDIE
00528 #define WDTCSR_WDP3 WDP3
00529 #define WDTCSR_WDCE WDCE
00530 #define WDTCSR_WDE WDE
00531 #define WDTCSR_WDP2 WDP2
00532 #define WDTCSR_WDP1 WDP1
00533 #define WDTCSR_WDP0 WDP0
00534
00535 #define WDT_64MS ( 1 << WDP1 )
00536 #define WDT_125MS ( ( 1 << WDP1 ) | ( 1 << WDP0 ) )
00537 #define WDT_250MS ( 1 << WDP2 )
00538 #define WDT_500MS ( ( 1 << WDP2 ) | ( 1 << WDP0 ) )
00539 #define WDT_1000MS ( ( 1 << WDP2 ) | ( 1 << WDP1 ) )
00540
00544
00545
00546
00547
00548
00549
00550
00557
00559 #define EEPROM_EECR EECR
00560
00561
00563 #define EEPROM_EEPM1 EEPM1
00564
00565
00567 #define EEPROM_EEPM0 EEPM0
00568
00569
00571 #define EEPROM_EERIE EERIE
00572
00573
00575 #define EEPROM_EEMPE EEMPE
00576
00577
00579 #define EEPROM_EEPE EEPE
00580
00581
00583 #define EEPROM_EERE EERE
00584
00585
00587 #define EEPROM_EEDR EEDR
00588
00589
00591 #define EEPROM_EEAR EEAR
00592 #define EEPROM_EEARL EEARL
00593 #define EEPROM_EEARH EEARH
00594
00598
00599
00600
00601
00602
00609 #define EXT_INT_EIFR EIFR
00610
00611 #define INT0_VECTOR INT0_vect
00612 #define INT1_VECTOR INT1_vect
00613
00614 #define INT2_VECTOR INT2_vect
00615 #define INT3_VECTOR INT3_vect
00616 #define INT4_VECTOR INT4_vect
00617 #define INT5_VECTOR INT5_vect
00618 #define INT6_VECTOR INT6_vect
00619 #define INT7_VECTOR INT7_vect
00620
00621 #define PCINT0_VECTOR PCINT0_vect
00622 #define USB_GEN_VECTOR USB_GEN_vect
00623 #define USB_COM_VECTOR USB_COM_vect
00624 #define WDT_VECT WDT_vect
00625
00626 #define TIMER2_COMPA_VECT TIMER2_COMPA_vect
00627 #define TIMER2_COMPB_VECT TIMER2_COMPB_vect
00628 #define TIMER2_OVF_VECT TIMER2_OVF_vect
00629
00630 #define TIMER1_CAPT_VECT TIMER1_CAPT_vect
00631 #define TIMER1_COMPA_VECT TIMER1_COMPA_vect
00632 #define TIMER1_COMPB_VECT TIMER1_COMPB_vect
00633 #define TIMER1_OVF_VECT TIMER1_OVF_vect
00634
00635 #define TIMER0_COMPA_VECT TIMER0_COMPA_vect
00636 #define TIMER0_COMPB_VECT TIMER0_COMPB_vect
00637
00638 #define TIMER0_OVF_VECT TIMER0_OVF_vect
00639
00640 #define SPI_STC_VECT SPI_STC_vect
00641 #define USART1_RX_VECT USART1_RX_vect
00642 #define USART1_UDRE_VECT USART1_UDRE_vect
00643 #define USART1_TX_VECT USART1_TX_vect
00644
00645 #define ANALOG_COMP_VECT ANALOG_COMP_vect
00646
00647 #define ADC_VECT ADC_vect
00648 #define EE_READY_VECT EE_READY_vect
00649
00650 #define TIMER3_CAPT_VECT TIMER3_CAPT_vect
00651 #define TIMER3_COMPA_VECT TIMER3_COMPA_vect
00652 #define TIMER3_COMPB_VECT TIMER3_COMPB_vect
00653 #define TIMER3_COMPC_VECT TIMER3_COMPC_vect
00654 #define TIMER3_OVF_VECT TIMER3_OVF_vect
00655 #define TWI_VECT TWI_vect
00656
00661
00662
00663
00664
00665
00666
00669 typedef enum {
00670 EXT_TRIGGER_LOW_LEVEL = 0,
00671 EXT_TRIGGER_ANY_EDGE,
00672 EXT_TRIGGER_FALLING_EDGE,
00673 EXT_TRIGGER_RISING_EDGE
00674 } EXT_SENSE_CONTROL;
00675
00676
00677 #endif