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Contains all macro definitions & function prototypes
for MCP2515 can bus controller.
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Go to the source code of this file.
Defines | |
#define | MSG_ENABLE ((uint8_t)(0)) |
#define | SET_BIT 1 |
#define | CLR_BIT 0 |
#define | TXBCTRL_ABTF ((uint8_t)(6)) |
Message Aborted Flag bit - message aborted or completed transmission successfully. | |
#define | TXBCTRL_MLOA ((uint8_t)(5)) |
Message Lost Arbitration bit - message los arbitration while being sent. | |
#define | TXBCTRL_TXERR ((uint8_t)(4)) |
Transmission Error Detected Bit - a bus error occurred while transmission. | |
#define | TXBCTRL_TXREQ ((uint8_t)(3)) |
Message Transmit Request bit - currently pending transmission. | |
#define | TXBCTRL_TXP ((uint8_t)(0)) |
CAN Transmit Buffer Priority. | |
#define | RXB0CTRL_RXM1 ((uint8_t)(6)) |
Receive Buffer Operating Mode bits - turn mask/filter off. | |
#define | RXB0CTRL_RXM0 ((uint8_t)(5)) |
Receive Buffer Operating Mode bits - turn mask/filter off. | |
#define | RXB0CTRL_RXRTR ((uint8_t)(3)) |
Received Remote Transfer Request bit 1 - ON, 0 - no remote. | |
#define | RXB0CTRL_BUKT ((uint8_t)(2)) |
Rollover Enable bit. | |
#define | RXB0CTRL_BUKT1 ((uint8_t)(1)) |
Read-only Copy of BUKT bit (used internally by the MCP2515) | |
#define | RXB0_FILHIT ((uint8_t)(0)) |
Filter Hit Bit - indicates which acceptance filter enabled reception of message. | |
#define | RXB0_FILHIT_MASK ((uint8_t)((1<<0))) |
#define | RXB_DLC_RTR ((uint8_t)(6)) |
Extended Frame Remote Transmission Request bit. | |
#define | RXB_DLC_MASK ((uint8_t)((1<<3)|(1<<2)|(1<<1)|(1<<0))) |
EID6 of Extended Identifier LOW. | |
#define | EFLG_RX1OVR ((uint8_t)(7)) |
RX1OVR. | |
#define | EFLG_RX0OVR ((uint8_t)(6)) |
RX0OVR. | |
#define | EFLG_TXBO ((uint8_t)(5)) |
TXBO. | |
#define | EFLG_TXEP ((uint8_t)(4)) |
TXEP. | |
#define | EFLG_RXEP ((uint8_t)(3)) |
RXEP. | |
#define | EFLG_TXWAR ((uint8_t)(2)) |
TXWAR. | |
#define | EFLG_RXWAR ((uint8_t)(1)) |
RXWAR. | |
#define | EFLG_EWARN ((uint8_t)(0)) |
EWARN. | |
#define | CANINTE_MERRE ((uint8_t)(7)) |
MERRE. | |
#define | CANINTE_WAKIE ((uint8_t)(6)) |
WAKIE. | |
#define | CANINTE_ERRIE ((uint8_t)(5)) |
ERRIE. | |
#define | CANINTE_TX2IE ((uint8_t)(4)) |
TX2IE. | |
#define | CANINTE_TX1IE ((uint8_t)(3)) |
TX1IE. | |
#define | CANINTE_TX0IE ((uint8_t)(2)) |
TX0IE. | |
#define | CANINTE_RX1IE ((uint8_t)(1)) |
RX1IE. | |
#define | CANINTE_RX0IE ((uint8_t)(0)) |
RX0IE. | |
#define | CANCTRL_REQOP_MASK ((uint8_t)( (1<<7)|(1<<6)|(1<<5) )) |
REQOP MASK. | |
#define | CANCTRL_REQOP_SHIFT ((uint8_t)(5)) |
REQOP_SHIFT. | |
#define | CANCTRL_ABAT ((uint8_t)(4)) |
ABAT. | |
#define | CANCTRL_OSM ((uint8_t)(3)) |
OSM. | |
#define | CANCTRL_CLKEN ((uint8_t)(2)) |
CLKEN. | |
#define | CANCTRL_CLKPRE_MASK ((uint8_t)( (1<<1)|(1<<0) )) |
CLKPRE. | |
#define | CANSTAT_OPMOD_MASK ((uint8_t)( (1<<7)|(1<<6)|(1<<5) )) |
OPMOD. | |
#define | CANSTAT_ICOD_MASK ((uint8_t)( (1<<3)|(1<<2)|(1<<1) )) |
ICOD. | |
#define | TXB0CTRL ((uint8_t)(0x30)) |
TXB0CTRL. | |
#define | TXB1CTRL ((uint8_t)(0x40)) |
TXB1CTRL. | |
#define | TXB2CTRL ((uint8_t)(0x50)) |
TXB2CTRL. | |
#define | TXRTSCTRL ((uint8_t)(0x0D)) |
TXRTSCTRL. | |
#define | TXB0SIDH ((uint8_t)(0x31)) |
TXB0SIDH. | |
#define | TXB1SIDH ((uint8_t)(0x41)) |
TXB1SIDH. | |
#define | TXB2SIDH ((uint8_t)(0x51)) |
TXB2SIDH. | |
#define | TXB0SIDL ((uint8_t)(0x32)) |
TXB0SIDL. | |
#define | TXB1SIDL ((uint8_t)(0x42)) |
TXB1SIDL. | |
#define | TXB2SIDL ((uint8_t)(0x52)) |
TXB2SIDL. | |
#define | TXB0EID8 ((uint8_t)(0x33)) |
TXB0EID8. | |
#define | TXB1EID8 ((uint8_t)(0x43)) |
TXB1EID8. | |
#define | TXB2EID8 ((uint8_t)(0x53)) |
TXB2EID8. | |
#define | TXB0EID0 ((uint8_t)(0x34)) |
TXB0EID0. | |
#define | TXB1EID0 ((uint8_t)(0x44)) |
TXB1EID0. | |
#define | TXB2EID0 ((uint8_t)(0x54)) |
TXB2EID0. | |
#define | TXB0DLC ((uint8_t)(0x35)) |
TXB0DLC. | |
#define | TXB1DLC ((uint8_t)(0x45)) |
TXB1DLC. | |
#define | TXB2DLC ((uint8_t)(0x55)) |
TXB2DLC. | |
#define | TXB0D0 ((uint8_t)(0x36)) |
TXB0Dx. | |
#define | TXB1D0 ((uint8_t)(0x46)) |
TXB1Dx. | |
#define | TXB2D0 ((uint8_t)(0x56)) |
TXB2Dx. | |
#define | RXB0CTRL ((uint8_t)(0x60)) |
RXB0CTRL. | |
#define | RXB1CTRL ((uint8_t)(0x70)) |
RXB1CTRL. | |
#define | BFPCTRL ((uint8_t)(0x0C)) |
BFPCTRL. | |
#define | RXB0SIDH ((uint8_t)(0x61)) |
RXBnSIDH. | |
#define | RXB1SIDH ((uint8_t)(0x71)) |
#define | RXB0SIDL ((uint8_t)(0x62)) |
RXBnSIDL. | |
#define | RXB1SIDL ((uint8_t)(0x72)) |
#define | RXB0EID8 ((uint8_t)(0x63)) |
RXBnEID8. | |
#define | RXB1EID8 ((uint8_t)(0x73)) |
#define | RXB0EID0 ((uint8_t)(0x64)) |
RXBnEID8. | |
#define | RXB1EID0 ((uint8_t)(0x74)) |
#define | RXB0DLC ((uint8_t)(0x65)) |
RXBnDLC. | |
#define | RXB1DLC ((uint8_t)(0x75)) |
#define | RXB0D0 ((uint8_t)(0x66)) |
RXB0Dx. | |
#define | RXB1D0 ((uint8_t)(0x76)) |
RXB1Dx. | |
#define | RXB1D1 ((uint8_t)(0x77)) |
#define | RXB1D2 ((uint8_t)(0x78)) |
#define | RXB1D3 ((uint8_t)(0x79)) |
#define | RXB1D4 ((uint8_t)(0x7A)) |
#define | RXB1D5 ((uint8_t)(0x7B)) |
#define | RXB1D6 ((uint8_t)(0x7C)) |
#define | RXB1D7 ((uint8_t)(0x7D)) |
#define | RXF0SIDH ((uint8_t)(0x00)) |
RXFnSIDH. | |
#define | RXF1SIDH ((uint8_t)(0x04)) |
#define | RXF2SIDH ((uint8_t)(0x08)) |
#define | RXF3SIDH ((uint8_t)(0x10)) |
#define | RXF4SIDH ((uint8_t)(0x14)) |
#define | RXF5SIDH ((uint8_t)(0x18)) |
#define | RXF0SIDL ((uint8_t)(0x01)) |
RXFnSIDL. | |
#define | RXF1SIDL ((uint8_t)(0x05)) |
#define | RXF2SIDL ((uint8_t)(0x09)) |
#define | RXF3SIDL ((uint8_t)(0x11)) |
#define | RXF4SIDL ((uint8_t)(0x15)) |
#define | RXF5SIDL ((uint8_t)(0x19)) |
#define | RXF0EID8 ((uint8_t)(0x02)) |
RXFnEID8. | |
#define | RXF1EID8 ((uint8_t)(0x06)) |
#define | RXF2EID8 ((uint8_t)(0x0A)) |
#define | RXF3EID8 ((uint8_t)(0x12)) |
#define | RXF4EID8 ((uint8_t)(0x16)) |
#define | RXF5EID8 ((uint8_t)(0x1A)) |
#define | RXF0EID0 ((uint8_t)(0x03)) |
RXFnEID0. | |
#define | RXF1EID0 ((uint8_t)(0x07)) |
#define | RXF2EID0 ((uint8_t)(0x0B)) |
#define | RXF3EID0 ((uint8_t)(0x13)) |
#define | RXF4EID0 ((uint8_t)(0x17)) |
#define | RXF5EID0 ((uint8_t)(0x1B)) |
#define | RXM0SIDH ((uint8_t)(0x20)) |
RXMnSIDH. | |
#define | RXM1SIDH ((uint8_t)(0x24)) |
#define | RXM0SIDL ((uint8_t)(0x21)) |
RXMnSIDL. | |
#define | RXM1SIDL ((uint8_t)(0x25)) |
#define | RXM0EID8 ((uint8_t)(0x22)) |
RXMnEID8. | |
#define | RXM1EID8 ((uint8_t)(0x26)) |
#define | RXM0EID0 ((uint8_t)(0x23)) |
RXMnEID0. | |
#define | RXM1EID0 ((uint8_t)(0x27)) |
#define | CNF1 ((uint8_t)(0x2A)) |
CNF. | |
#define | CNF2 ((uint8_t)(0x29)) |
#define | CNF3 ((uint8_t)(0x28)) |
#define | TEC ((uint8_t)(0x1C)) |
TEC. | |
#define | REC ((uint8_t)(0x1D)) |
REC. | |
#define | EFLG ((uint8_t)(0x2D)) |
EFLG. | |
#define | CANINTE ((uint8_t)(0x2B)) |
CANINTE. | |
#define | CANINTF ((uint8_t)(0x2C)) |
CANINTF. | |
#define | CANCTRL ((uint8_t)(0x0F)) |
CANCTRL. | |
#define | CANSTAT ((uint8_t)(0xE)) |
CANSTAT. | |
#define | MCP_RESET 0xC0 |
#define | MCP_READ_CMD 0x03 |
#define | MCP_WRITE_CMD 0x02 |
#define | MCP_RECEIVE_RXB0SIDH 0x90 |
#define | MCP_RECEIVE_RXB0D0 0x91 |
#define | MCP_RECEIVE_RXB1SIDH 0x92 |
#define | MCP_RECEIVE_RXB1D0 0x93 |
#define | MCP_LOAD_TXB0SIDH 0x40 |
#define | MCP_LOAD_TXB0D0 0x41 |
#define | MCP_LOAD_TXB1SIDH 0x42 |
#define | MCP_LOAD_TXB1D0 0x43 |
#define | MCP_LOAD_TXB2SIDH 0x44 |
#define | MCP_LOAD_TXB2D0 0x45 |
#define | MCP_READ_STATUS 0xA0 |
#define | MCP_RX_STATUS 0xB0 |
#define | MPC_BIT_MODIFY 0x05 |
#define | REG_OFFSET 0x10 |
#define | REC_REG_0 0 |
#define | REC_REG_1 1 |
#define | SEND_REG_0 0 |
#define | SEND_REG_1 1 |
#define | SEND_REG_2 2 |
#define | CANINTF_FLAG_MERRF ((uint8_t)(7)) |
Macro defines for CANINTF - Can Interrupt Flag (documentation p. 51) | |
#define | CANINTF_FLAG_WAKIF ((uint8_t)(6)) |
WAKIE. | |
#define | CANINTF_FLAG_ERRIF ((uint8_t)(5)) |
ERRIF. | |
#define | CANINTF_FLAG_TX2IF ((uint8_t)(4)) |
TX2IF. | |
#define | CANINTF_FLAG_TX1IF ((uint8_t)(3)) |
TX1IF. | |
#define | CANINTF_FLAG_TX0IF ((uint8_t)(2)) |
TX0IF. | |
#define | CANINTF_FLAG_RX1IF ((uint8_t)(1)) |
RX1IF. | |
#define | CANINTF_FLAG_RX0IF ((uint8_t)(0)) |
RX0IF. | |
Enumerations | |
enum | TXB_CONTROL_TXP { TXBCTRL_TXP_LOWEST_MSG_PRIORITY = 0, TXBCTRL_TXP_LOW_INTERMEDIATE_MSG_PRIORITY, TXP_HIGH_INTERMEDIATE_MSG_PRIORITY, TXP_HIGHEST_MSG_PRIORITY } |
enum | RXB0_CONTROL_RXM { RXB0CTRL_RXM_ALL_MSG_STAND_EXT_ID = 0, RXB0CTRL_RXM_ONLY_VALID_STAND_ID, RXB0CTRL_RXM_ONLY_VALID_EXT_ID, RXB0CTRL_RXM_TURN_OFF_FIL_MASK_ALL_MSG } |
Message Aborted Flag bit enum. More... | |
enum | CONTROL_REQOP { CANCTRL_REQOP_NORMAL = 0, CANCTRL_REQOP_SLEEP, CANCTRL_REQOP_LOOPBACK, CANCTRL_REQOP_LISTEN_ONLY, CANCTRL_REQOP_CONFIGURATION } |
Request Operation Mode bits <2:0> More... | |
enum | STATUS_OPMOD { CANSTAT_OPMOD_NORMAL = 0, CANSTAT_OPMOD_SLEEP, CANSTAT_OPMOD_LOOPBACK, CANSTAT_OPMOD_LISTEN_ONLY, CANSTAT_OPMOD_CONFIGURATION } |
#define | RXB1CTRL_RXM1 ((uint8_t)(6)) |
Macro defines for RXB1CTRL - CAN Receive Buffer 1 Control Register. | |
#define | RXB1CTRL_RXM0 ((uint8_t)(5)) |
Receive Buffer Operating Mode bits - turn mask/filter off; receive any message. | |
#define | RXB1CTRL_RXRTR ((uint8_t)(3)) |
Received Remote Transfer Request bit 1 - ON, 0 - no remote. | |
#define | RXB1CTRL_FILHIT_MASK ((uint8_t) ((1<<2)|(1<<1)|(1<<0))) |
Filter Hit Bit - indicates which acceptance filter enabled reception of message. | |
enum | RXB1_CONTROL_RXM { RXB1CTRL_RXM_ALL_MSG_STAND_EXT_ID = 0, RXB1CTRL_RXM_ONLY_VALID_STAND_ID, RXB1CTRL_RXM_ONLY_VALID_EXT_ID, RXB1CTRL_RXM_TURN_OFF_FIL_MASK_ALL_MSG } |
Message Aborted Flag bit enum. More... |
Contains all macro definitions & function prototypes
for MCP2515 can bus controller.