Name |
Value |
C_INTERCONNECT_M_AXI_GP1_READ_ISSUING |
8 |
C_S_AXI_GP0_PROTOCOL |
AXI3 |
C_S_AXI_GP0_ID_WIDTH |
6 |
C_S_AXI_GP0_ADDR_WIDTH |
32 |
C_S_AXI_GP0_DATA_WIDTH |
32 |
C_INTERCONNECT_S_AXI_GP0_WRITE_ACCEPTANCE |
8 |
C_INTERCONNECT_S_AXI_GP0_READ_ACCEPTANCE |
8 |
C_S_AXI_GP1_PROTOCOL |
AXI3 |
C_S_AXI_GP1_ID_WIDTH |
6 |
C_S_AXI_GP1_ADDR_WIDTH |
32 |
C_S_AXI_GP1_DATA_WIDTH |
32 |
C_INTERCONNECT_S_AXI_GP1_WRITE_ACCEPTANCE |
8 |
C_INTERCONNECT_S_AXI_GP1_READ_ACCEPTANCE |
8 |
C_S_AXI_ACP_PROTOCOL |
AXI3 |
C_S_AXI_ACP_ID_WIDTH |
3 |
C_S_AXI_ACP_ADDR_WIDTH |
32 |
C_S_AXI_ACP_DATA_WIDTH |
64 |
C_S_AXI_ACP_SUPPORTS_USER_SIGNALS |
1 |
C_S_AXI_ACP_ARUSER_WIDTH |
5 |
C_S_AXI_ACP_AWUSER_WIDTH |
5 |
C_INTERCONNECT_S_AXI_ACP_WRITE_ACCEPTANCE |
8 |
C_INTERCONNECT_S_AXI_ACP_READ_ACCEPTANCE |
8 |
C_S_AXI_HP0_PROTOCOL |
AXI3 |
C_S_AXI_HP0_ID_WIDTH |
6 |
C_S_AXI_HP0_ADDR_WIDTH |
32 |
C_S_AXI_HP0_DATA_WIDTH |
64 |
C_INTERCONNECT_S_AXI_HP0_WRITE_ACCEPTANCE |
8 |
C_INTERCONNECT_S_AXI_HP0_READ_ACCEPTANCE |
8 |
C_S_AXI_HP1_PROTOCOL |
AXI3 |
C_S_AXI_HP1_ID_WIDTH |
6 |
C_S_AXI_HP1_ADDR_WIDTH |
32 |
C_S_AXI_HP1_DATA_WIDTH |
64 |
C_INTERCONNECT_S_AXI_HP1_WRITE_ACCEPTANCE |
8 |
C_INTERCONNECT_S_AXI_HP1_READ_ACCEPTANCE |
8 |
C_S_AXI_HP2_PROTOCOL |
AXI3 |
C_S_AXI_HP2_ID_WIDTH |
6 |
C_S_AXI_HP2_ADDR_WIDTH |
32 |
C_S_AXI_HP2_DATA_WIDTH |
64 |
C_INTERCONNECT_S_AXI_HP2_WRITE_ACCEPTANCE |
8 |
C_INTERCONNECT_S_AXI_HP2_READ_ACCEPTANCE |
8 |
C_S_AXI_HP3_PROTOCOL |
AXI3 |
C_S_AXI_HP3_ID_WIDTH |
6 |
C_S_AXI_HP3_ADDR_WIDTH |
32 |
C_S_AXI_HP3_DATA_WIDTH |
64 |
C_INTERCONNECT_S_AXI_HP3_WRITE_ACCEPTANCE |
8 |
C_INTERCONNECT_S_AXI_HP3_READ_ACCEPTANCE |
8 |
C_S_AXI_GP0_BASEADDR |
0xE0000000 |
C_S_AXI_GP0_HIGHADDR |
0xFFFFFFFF |
C_S_AXI_GP0_LOWOCM_DDR_BASEADDR |
0x00000000 |
C_S_AXI_GP0_LOWOCM_DDR_HIGHADDR |
0x3FFFFFFF |
C_S_AXI_GP1_BASEADDR |
0xE0000000 |
C_S_AXI_GP1_HIGHADDR |
0xFFFFFFFF |
C_S_AXI_GP1_LOWOCM_DDR_BASEADDR |
0x00000000 |
C_S_AXI_GP1_LOWOCM_DDR_HIGHADDR |
0x3FFFFFFF |
C_S_AXI_ACP_BASEADDR |
0x00000000 |
C_S_AXI_ACP_HIGHADDR |
0x3FFFFFFF |
C_S_AXI_ACP_HIGHOCM_BASEADDR |
0xFFFC0000 |
C_S_AXI_ACP_HIGHOCM_HIGHADDR |
0xFFFFFFFF |
C_S_AXI_HP0_BASEADDR |
0x00000000 |
C_S_AXI_HP0_HIGHADDR |
0x0FFFFFFF |
C_S_AXI_HP0_HIGHOCM_BASEADDR |
0xFFFC0000 |
C_S_AXI_HP0_HIGHOCM_HIGHADDR |
0xFFFFFFFF |
C_S_AXI_HP1_BASEADDR |
0x10000000 |
C_S_AXI_HP1_HIGHADDR |
0x1FFFFFFF |
C_S_AXI_HP1_HIGHOCM_BASEADDR |
0xFFFC0000 |
C_S_AXI_HP1_HIGHOCM_HIGHADDR |
0xFFFFFFFF |
C_S_AXI_HP2_BASEADDR |
0x00000000 |
C_S_AXI_HP2_HIGHADDR |
0x3FFFFFFF |
C_S_AXI_HP2_HIGHOCM_BASEADDR |
0xFFFC0000 |
C_S_AXI_HP2_HIGHOCM_HIGHADDR |
0xFFFFFFFF |
C_S_AXI_HP3_BASEADDR |
0x00000000 |
C_S_AXI_HP3_HIGHADDR |
0x3FFFFFFF |
C_S_AXI_HP3_HIGHOCM_BASEADDR |
0xFFFC0000 |
C_S_AXI_HP3_HIGHOCM_HIGHADDR |
0xFFFFFFFF |
C_M_AXI_GP0_SUPPORTS_THREADS |
1 |
C_M_AXI_GP0_THREAD_ID_WIDTH |
12 |
C_M_AXI_GP1_SUPPORTS_THREADS |
1 |
C_M_AXI_GP1_THREAD_ID_WIDTH |
12 |
C_NUM_F2P_INTR_INPUTS |
2 |
C_EN_DDR |
1 |
C_EN_SMC |
0 |
C_EN_QSPI |
1 |
C_EN_CAN0 |
0 |
C_EN_CAN1 |
0 |
C_EN_ENET0 |
1 |
C_EN_ENET1 |
0 |
C_EN_GPIO |
1 |
C_EN_I2C0 |
0 |
C_EN_I2C1 |
0 |
C_EN_PJTAG |
0 |
C_EN_SDIO0 |
1 |
C_EN_SDIO1 |
0 |
C_EN_SPI0 |
0 |
C_EN_SPI1 |
0 |
C_EN_UART0 |
0 |
C_EN_UART1 |
1 |
C_EN_MODEM_UART0 |
0 |
C_EN_MODEM_UART1 |
0 |
C_EN_TTC0 |
1 |
C_EN_TTC1 |
0 |
C_EN_WDT |
0 |
C_EN_TRACE |
0 |
C_EN_USB0 |
1 |
C_EN_USB1 |
0 |
C_FCLK_CLK0_FREQ |
100000000 |
C_FCLK_CLK1_FREQ |
142857152 |
C_FCLK_CLK2_FREQ |
50000000 |
C_FCLK_CLK3_FREQ |
50000000 |
C_FCLK_CLK0_BUF |
TRUE |
C_FCLK_CLK1_BUF |
TRUE |
C_FCLK_CLK2_BUF |
TRUE |
C_FCLK_CLK3_BUF |
TRUE |
C_INTERCONNECT_S_AXI_ACP_MASTERS |
lbm_acc_top_0.M_AXI_BUS_R |
C_INTERCONNECT_S_AXI_HP0_MASTERS |
lbm_acc_top_0.M_AXI_SRC_BUS |
C_INTERCONNECT_S_AXI_HP1_MASTERS |
lbm_acc_top_0.M_AXI_DST_BUS |