Definition in file power_clocks_lib.c.
#include "power_clocks_lib.h"
Go to the source code of this file.
Functions | |
long int | pcl_configure_clocks (pcl_freq_param_t *param) |
Device-specific data. | |
long int | pcl_configure_usb_clock (void) |
Configure the USB Clock. | |
unsigned long | pcl_read_gplp (unsigned long gplp) |
Read the content of the GPLP registers. | |
long int | pcl_switch_to_osc (pcl_osc_t osc, unsigned int fcrystal, unsigned int startup) |
Device-specific implementation. | |
void | pcl_write_gplp (unsigned long gplp, unsigned long value) |
Write into the GPLP registers. |
long int pcl_configure_clocks | ( | pcl_freq_param_t * | param | ) |
Device-specific data.
Automatically configure the CPU, PBA, PBB, and HSB clocks.
Definition at line 60 of file power_clocks_lib.c.
References pm_configure_clocks().
00061 { 00062 #ifndef AVR32_PM_VERSION_RESETVALUE 00063 // Implementation for UC3A, UC3A3, UC3B parts. 00064 return(pm_configure_clocks(param)); 00065 #else 00066 #ifdef AVR32_PM_410_H_INCLUDED 00067 // Implementation for UC3C parts. 00068 return(pcl_configure_clocks_uc3c(param)); 00069 #else 00070 // Implementation for UC3L parts. 00071 return(pcl_configure_clocks_uc3l(param)); 00072 #endif 00073 #endif 00074 }
long int pcl_configure_usb_clock | ( | void | ) |
Configure the USB Clock.
0 | Success. | |
<0 | An error occured. |
Definition at line 500 of file power_clocks_lib.c.
References PCL_NOT_SUPPORTED, and pm_configure_usb_clock().
00501 { 00502 #ifndef AVR32_PM_VERSION_RESETVALUE 00503 // Implementation for UC3A, UC3A3, UC3B parts. 00504 pm_configure_usb_clock(); 00505 return PASS; 00506 #else 00507 #ifdef AVR32_PM_410_H_INCLUDED 00508 const scif_pll_opt_t opt = { 00509 .osc = SCIF_OSC0, // Sel Osc0 or Osc1 00510 .lockcount = 16, // lockcount in main clock for the PLL wait lock 00511 .div = 1, // DIV=1 in the formula 00512 .mul = 5, // MUL=7 in the formula 00513 .pll_div2 = 1, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) 00514 .pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. 00515 .pll_freq = 1, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. 00516 }; 00517 00518 /* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */ 00519 scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock 00520 00521 /* Enable PLL1 */ 00522 scif_pll_enable(SCIF_PLL1); 00523 00524 /* Wait for PLL1 locked */ 00525 scif_wait_for_pll_locked(SCIF_PLL1) ; 00526 00527 // Implementation for UC3C parts. 00528 // Setup the generic clock for USB 00529 scif_gc_setup(AVR32_SCIF_GCLK_USB, 00530 SCIF_GCCTRL_PLL1, 00531 AVR32_SCIF_GC_NO_DIV_CLOCK, 00532 0); 00533 // Now enable the generic clock 00534 scif_gc_enable(AVR32_SCIF_GCLK_USB); 00535 return PASS; 00536 #else 00537 return PCL_NOT_SUPPORTED; 00538 #endif 00539 #endif 00540 }
unsigned long pcl_read_gplp | ( | unsigned long | gplp | ) |
Read the content of the GPLP registers.
gplp | GPLP register index (0,1,... depending on the number of GPLP registers for a given part) |
Definition at line 555 of file power_clocks_lib.c.
References pm_read_gplp().
00556 { 00557 #ifndef AVR32_PM_VERSION_RESETVALUE 00558 // Implementation for UC3A, UC3A3, UC3B parts. 00559 return pm_read_gplp(&AVR32_PM,gplp); 00560 #else 00561 return scif_read_gplp(gplp); 00562 #endif 00563 }
long int pcl_switch_to_osc | ( | pcl_osc_t | osc, | |
unsigned int | fcrystal, | |||
unsigned int | startup | |||
) |
Device-specific implementation.
Switch the main clock source to Osc0 configured in crystal mode.
UC3C Device-specific implementation
Definition at line 457 of file power_clocks_lib.c.
References PCL_NOT_SUPPORTED, PCL_OSC0, PM_CLK_SRC_OSC0, pm_set_mclk_source(), and pm_switch_to_osc0().
00458 { 00459 #ifndef AVR32_PM_VERSION_RESETVALUE 00460 // Implementation for UC3A, UC3A3, UC3B parts. 00461 if(PCL_OSC0 == osc) 00462 { 00463 // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency, 00464 // enable the OSC0, set the main clock source as being OSC0. 00465 pm_switch_to_osc0(&AVR32_PM, fcrystal, startup); 00466 } 00467 else 00468 { 00469 return PCL_NOT_SUPPORTED; 00470 } 00471 #else 00472 // Implementation for UC3C, UC3L parts. 00473 #if AVR32_PM_VERSION_RESETVALUE < 0x400 00474 return PCL_NOT_SUPPORTED; 00475 #else 00476 if(PCL_OSC0 == osc) 00477 { 00478 // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency. 00479 scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal); 00480 // Enable the OSC0 00481 scif_enable_osc(SCIF_OSC0, startup, true); 00482 // Set the Flash wait state and the speed read mode (depending on the target CPU frequency). 00483 #if UC3L 00484 flashcdw_set_flash_waitstate_and_readmode(fcrystal); 00485 #elif UC3C 00486 flashc_set_flash_waitstate_and_readmode(fcrystal); 00487 #endif 00488 // Set the main clock source as being OSC0. 00489 pm_set_mclk_source(PM_CLK_SRC_OSC0); 00490 } 00491 else 00492 { 00493 return PCL_NOT_SUPPORTED; 00494 } 00495 #endif 00496 #endif 00497 return PASS; 00498 }
void pcl_write_gplp | ( | unsigned long | gplp, | |
unsigned long | value | |||
) |
Write into the GPLP registers.
gplp | GPLP register index (0,1,... depending on the number of GPLP registers for a given part) | |
value | Value to write |
Definition at line 545 of file power_clocks_lib.c.
References pm_write_gplp().
00546 { 00547 #ifndef AVR32_PM_VERSION_RESETVALUE 00548 // Implementation for UC3A, UC3A3, UC3B parts. 00549 pm_write_gplp(&AVR32_PM,gplp,value); 00550 #else 00551 scif_write_gplp(gplp,value); 00552 #endif 00553 }