00001 /*This file is prepared for Doxygen automatic documentation generation.*/ 00018 /* Copyright (c) 2009 Atmel Corporation. All rights reserved. 00019 * 00020 * Redistribution and use in source and binary forms, with or without 00021 * modification, are permitted provided that the following conditions are met: 00022 * 00023 * 1. Redistributions of source code must retain the above copyright notice, this 00024 * list of conditions and the following disclaimer. 00025 * 00026 * 2. Redistributions in binary form must reproduce the above copyright notice, 00027 * this list of conditions and the following disclaimer in the documentation 00028 * and/or other materials provided with the distribution. 00029 * 00030 * 3. The name of Atmel may not be used to endorse or promote products derived 00031 * from this software without specific prior written permission. 00032 * 00033 * 4. This software may only be redistributed and used in connection with an Atmel 00034 * AVR product. 00035 * 00036 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 00037 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 00038 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 00039 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 00040 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00041 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00042 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 00043 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00044 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00045 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 00046 * 00047 */ 00048 00049 #ifndef _MT48LC16M16A2TG7E_H_ 00050 #define _MT48LC16M16A2TG7E_H_ 00051 00052 00054 #define SDRAM_BANK_BITS 2 00055 00057 #define SDRAM_ROW_BITS 13 00058 00060 #define SDRAM_COL_BITS 9 00061 00064 #define SDRAM_CAS 2 00065 00068 #define SDRAM_TWR 14 00069 00073 #define SDRAM_TRC 60 00074 00078 #define SDRAM_TRP 15 00079 00083 #define SDRAM_TRCD 15 00084 00088 #define SDRAM_TRAS 37 00089 00093 #define SDRAM_TXSR 67 00094 00098 #define SDRAM_TR 7812 00099 00103 #define SDRAM_TRFC 66 00104 00108 #define SDRAM_TMRD 2 00109 00112 #define SDRAM_STABLE_CLOCK_INIT_DELAY 100 00113 00115 #define SDRAM_INIT_AUTO_REFRESH_COUNT 2 00116 00117 00118 #endif // _MT48LC16M16A2TG7E_H_