Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/toplevel_test |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserBrowsedStrategyFiles=/home/jonemil/Xilinx/13.4/ISE_DS/ISE/data/default.xds |
PROP_intProjectCreationTimestamp=2012-02-06T17:12:59 |
PROP_intWbtProjectID=D24152BDF22D76739BA8D67D54F565BE |
PROP_intWbtProjectIteration=36 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_selectedSimRootSourceNode_behav=work.toplevel_test |
PROP_xilxBitgCfg_GenOpt_ASCIIFile=true |
PROP_xilxBitgCfg_GenOpt_BitFile=false |
PROP_AutoTop=false |
PROP_CompxlibEdkSimLib=true |
PROP_DevFamily=Spartan3E |
PROP_DevDevice=xc3s500e |
PROP_DevFamilyPMName=spartan3e |
PROP_DevPackage=pq208 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-5 |
PROP_PreferredLanguage=VHDL |
FILE_UCF=1 |
FILE_VHDL=29 |