00001
00089 #include <string.h>
00090
00091 #include "board.h"
00092 #include "print_funcs.h"
00093 #include "gpio.h"
00094 #include "pm.h"
00095 #include "intc.h"
00096 #include "usart.h"
00097
00098
00101
00102 #if BOARD == EVK1104
00103 # define DMACA_RAM2RAM_EVAL_USART (&AVR32_USART1)
00104 # define DMACA_RAM2RAM_EVAL_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN
00105 # define DMACA_RAM2RAM_EVAL_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION
00106 # define DMACA_RAM2RAM_EVAL_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN
00107 # define DMACA_RAM2RAM_EVAL_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION
00108 # define DMACA_RAM2RAM_EVAL_USART_BAUDRATE 57600
00109 # define DMACA_RAM2RAM_EVAL_LED1 LED0_GPIO
00110 # define DMACA_RAM2RAM_EVAL_LED2 LED1_GPIO
00111 # define DMACA_RAM2RAM_EVAL_LED3 LED2_GPIO
00112 # define DMACA_RAM2RAM_EVAL_LED4 LED3_GPIO
00113 #endif
00114
00115 #if !defined(DMACA_RAM2RAM_EVAL_USART) || \
00116 !defined(DMACA_RAM2RAM_EVAL_USART_RX_PIN) || \
00117 !defined(DMACA_RAM2RAM_EVAL_USART_RX_FUNCTION) || \
00118 !defined(DMACA_RAM2RAM_EVAL_USART_TX_PIN) || \
00119 !defined(DMACA_RAM2RAM_EVAL_USART_TX_FUNCTION) || \
00120 !defined(DMACA_RAM2RAM_EVAL_USART_BAUDRATE) || \
00121 !defined(DMACA_RAM2RAM_EVAL_LED1) || \
00122 !defined(DMACA_RAM2RAM_EVAL_LED2) || \
00123 !defined(DMACA_RAM2RAM_EVAL_LED3) || \
00124 !defined(DMACA_RAM2RAM_EVAL_LED4)
00125 # error The USART and LEDs configuration to use for debug on your board is missing
00126 #endif
00128
00129
00131
00132 #define DMACA_RAM2RAM_EVAL_STATE_1 0
00133 #define DMACA_RAM2RAM_EVAL_STATE_2 1
00134 #define DMACA_RAM2RAM_EVAL_STATE_3 2
00135 #define DMACA_RAM2RAM_EVAL_STATE_4 3
00137
00138 #define DMACA_RAM2RAM_EVAL_BUF_SIZE 256
00139
00140
00141 unsigned int SrcData_CpuSram[DMACA_RAM2RAM_EVAL_BUF_SIZE];
00142 volatile unsigned int DstData_CpuSram[DMACA_RAM2RAM_EVAL_BUF_SIZE];
00143 unsigned int *pSrcData_HsbSram;
00144 volatile unsigned int *pDstData_HsbSram;
00145
00146 volatile unsigned char state = 0;
00147
00148 volatile unsigned int ccountt0, ccountt1 = 0;
00149
00150 volatile unsigned long Tempo;
00151
00152 pm_freq_param_t pm_freq_param =
00153 {
00154 .cpu_f = DMACA_RAM2RAM_EVAL_CPU_FREQ,
00155 .pba_f = DMACA_RAM2RAM_EVAL_CPU_FREQ,
00156 .osc0_f = FOSC0,
00157 .osc0_startup = OSC0_STARTUP
00158 };
00159
00166 #if __GNUC__
00167 __attribute__((__interrupt__))
00168 #elif __ICCAVR32__
00169 __interrupt
00170 #endif
00171 static void dmaca_tfrint_handler(void)
00172 {
00173 unsigned long int u32Status;
00174
00175 gpio_clr_gpio_pin(DMACA_RAM2RAM_EVAL_LED1);
00176
00177 AVR32_DMACA.cleartfr = OK << AVR32_DMACA_CLEARTFR_CLEAR2_OFFSET;
00178
00179
00180 u32Status = AVR32_DMACA.statusint;
00181 if(u32Status & (AVR32_DMACA_STATUSINT_DSTT_MASK | AVR32_DMACA_STATUSINT_SRCT_MASK | AVR32_DMACA_STATUSINT_BLOCK_MASK))
00182 {
00183 gpio_clr_gpio_pin(DMACA_RAM2RAM_EVAL_LED3);
00184 }
00185 }
00186
00187
00194 #if __GNUC__
00195 __attribute__((__interrupt__))
00196 #elif __ICCAVR32__
00197 __interrupt
00198 #endif
00199 static void dmaca_errint_handler(void)
00200 {
00201 unsigned long int u32Status;
00202
00203
00204
00205
00206 gpio_clr_gpio_pin(DMACA_RAM2RAM_EVAL_LED2);
00207
00208 AVR32_DMACA.clearerr = OK << AVR32_DMACA_CLEARERR_CLEAR2_OFFSET;
00209
00210
00211 u32Status = AVR32_DMACA.statusint;
00212 if(u32Status & (AVR32_DMACA_STATUSINT_DSTT_MASK | AVR32_DMACA_STATUSINT_SRCT_MASK | AVR32_DMACA_STATUSINT_BLOCK_MASK))
00213 {
00214 gpio_clr_gpio_pin(DMACA_RAM2RAM_EVAL_LED4);
00215 }
00216 }
00217
00218
00223 void test_ram_to_ram(unsigned short int u16BufferSize, unsigned int *pSrcBuf, unsigned int *pDstBuf)
00224 {
00225 unsigned int i;
00226 unsigned char TestResult = TRUE;
00227
00228
00229
00230
00231
00232
00233 AVR32_DMACA.dmacfgreg = 1 << AVR32_DMACA_DMACFGREG_DMA_EN_OFFSET;
00234
00235
00236
00237
00238
00239
00240
00241
00242
00243
00244
00245
00246
00247
00248
00249 AVR32_DMACA.sar2 = (unsigned long)pSrcBuf;
00250
00251
00252 AVR32_DMACA.dar2 = (unsigned long)pDstBuf;
00253
00254
00255 AVR32_DMACA.llp2 = 0x00000000;
00256
00257
00258 AVR32_DMACA.ctl2l =
00259 (1 << AVR32_DMACA_CTL2L_INT_EN_OFFSET) |
00260 (2<<AVR32_DMACA_CTL2L_DST_TR_WIDTH_OFFSET) |
00261 (2<<AVR32_DMACA_CTL2L_SRC_TR_WIDTH_OFFSET) |
00262 (0<<AVR32_DMACA_CTL2L_DINC_OFFSET) |
00263 (0<<AVR32_DMACA_CTL2L_SINC_OFFSET) |
00264 (1<<AVR32_DMACA_CTL2L_DST_MSIZE_OFFSET) |
00265 (1<<AVR32_DMACA_CTL2L_SRC_MSIZE_OFFSET) |
00266 (0<<AVR32_DMACA_CTL2L_TT_FC_OFFSET) |
00267 (1<<AVR32_DMACA_CTL2L_DMS_OFFSET) |
00268 (0<<AVR32_DMACA_CTL2L_SMS_OFFSET) |
00269 (0<<AVR32_DMACA_CTL2L_LLP_D_EN_OFFSET) |
00270 (0<<AVR32_DMACA_CTL2L_LLP_S_EN_OFFSET)
00271 ;
00272
00273
00274 AVR32_DMACA.ctl2h =
00275 (u16BufferSize << AVR32_DMACA_CTL2H_BLOCK_TS_OFFSET) |
00276 (0 << AVR32_DMACA_CTL2H_DONE_OFFSET)
00277 ;
00278
00279
00280 AVR32_DMACA.cfg2l =
00281 (0 << AVR32_DMACA_CFG2L_HS_SEL_DST_OFFSET) |
00282 (0 << AVR32_DMACA_CFG2L_HS_SEL_SRC_OFFSET)
00283 ;
00284
00285
00286 AVR32_DMACA.cfg2h =
00287 (0 << AVR32_DMACA_CFG2H_DEST_PER_OFFSET) |
00288 (0 << AVR32_DMACA_CFG2H_SRC_PER_OFFSET)
00289 ;
00290
00291
00292 #if DMACA_RAM2RAM_EVAL_TEST_INTERRUPTS
00293 AVR32_DMACA.masktfr =
00294 ( SET << AVR32_DMACA_MASKTFR_INT_M_WE2_OFFSET ) |
00295 ( SET << AVR32_DMACA_MASKTFR_INT_MASK2_OFFSET)
00296 ;
00297 AVR32_DMACA.maskerr =
00298 ( SET << AVR32_DMACA_MASKERR_INT_M_WE2_OFFSET ) |
00299 ( SET << AVR32_DMACA_MASKERR_INT_MASK2_OFFSET)
00300 ;
00301 #endif
00302
00303
00304
00305
00306 ccountt0 = Get_system_register(AVR32_COUNT);
00307
00308
00309 AVR32_DMACA.chenreg = ((4<<AVR32_DMACA_CHENREG_CH_EN_OFFSET) | (4<<AVR32_DMACA_CHENREG_CH_EN_WE_OFFSET));
00310
00311
00312 while(AVR32_DMACA.chenreg & (4<<AVR32_DMACA_CHENREG_CH_EN_OFFSET));
00313
00314 ccountt1 = Get_system_register(AVR32_COUNT);
00315
00316
00317 for(i=0; i<DMACA_RAM2RAM_EVAL_BUF_SIZE; i++)
00318 {
00319 if(pDstBuf[i] != pSrcBuf[i])
00320 {
00321 TestResult = FALSE;
00322 break;
00323 }
00324 }
00325 if(FALSE == TestResult)
00326 print(DMACA_RAM2RAM_EVAL_USART, "KO!!!\n");
00327 else
00328 {
00329 print(DMACA_RAM2RAM_EVAL_USART, "OK!!! Nb cycles: ");
00330 print_ulong(DMACA_RAM2RAM_EVAL_USART, ccountt1 - ccountt0);
00331 }
00332 }
00333
00334
00337 static void init_hmatrix(void)
00338 {
00339
00340
00341 avr32_hmatrix_scfg_t scfg;
00342
00343 scfg = AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_FLASH];
00344 scfg.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
00345 AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_FLASH] = scfg;
00346
00347 scfg = AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_SRAM];
00348 scfg.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
00349 AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_SRAM] = scfg;
00350
00351 scfg = AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_EMBEDDED_SYS_SRAM_0];
00352 scfg.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
00353 AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_EMBEDDED_SYS_SRAM_0] = scfg;
00354
00355 scfg = AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_EMBEDDED_SYS_SRAM_1];
00356 scfg.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
00357 AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_EMBEDDED_SYS_SRAM_1] = scfg;
00358 }
00359
00360
00368 int main(void)
00369 {
00370 int i;
00371 static const gpio_map_t USART_GPIO_MAP =
00372 {
00373 {DMACA_RAM2RAM_EVAL_USART_RX_PIN, DMACA_RAM2RAM_EVAL_USART_RX_FUNCTION},
00374 {DMACA_RAM2RAM_EVAL_USART_TX_PIN, DMACA_RAM2RAM_EVAL_USART_TX_FUNCTION}
00375 };
00376 static const usart_options_t USART_OPTIONS =
00377 {
00378 .baudrate = DMACA_RAM2RAM_EVAL_USART_BAUDRATE,
00379 .charlength = 8,
00380 .paritytype = USART_NO_PARITY,
00381 .stopbits = USART_1_STOPBIT,
00382 .channelmode = USART_NORMAL_CHMODE
00383 };
00384
00385
00386 #if BOARD == EVK1104
00387 if( PM_FREQ_STATUS_FAIL==pm_configure_clocks(&pm_freq_param) )
00388 while(1);
00389 #endif
00390
00391 init_hmatrix();
00392
00393
00394 gpio_enable_module(USART_GPIO_MAP,
00395 sizeof(USART_GPIO_MAP) / sizeof(USART_GPIO_MAP[0]));
00396
00397
00398 usart_init_rs232(DMACA_RAM2RAM_EVAL_USART, &USART_OPTIONS, DMACA_RAM2RAM_EVAL_CPU_FREQ);
00399 print(DMACA_RAM2RAM_EVAL_USART, "\x1B[2J\x1B[H.: RAM to RAM transfers with the DMACA at ");
00400 print_ulong(DMACA_RAM2RAM_EVAL_USART, DMACA_RAM2RAM_EVAL_CPU_FREQ);
00401 print(DMACA_RAM2RAM_EVAL_USART, "Hz :.\n\n");
00402
00403
00404 Disable_global_interrupt();
00405
00406
00407 INTC_init_interrupts();
00408
00409
00410
00411
00412 INTC_register_interrupt(&dmaca_tfrint_handler, AVR32_DMACA_TFR_IRQ, AVR32_INTC_INT0);
00413 INTC_register_interrupt(&dmaca_errint_handler, AVR32_DMACA_ERR_IRQ, AVR32_INTC_INT0);
00414
00415
00416 Enable_global_interrupt();
00417
00418
00419 for(i=0; i<DMACA_RAM2RAM_EVAL_BUF_SIZE; i++)
00420 SrcData_CpuSram[i] = i;
00421
00422
00423
00424
00425
00426
00427 print(DMACA_RAM2RAM_EVAL_USART, "\n---------------------------------------------------\n");
00428 print(DMACA_RAM2RAM_EVAL_USART, "------ DMACA transfer: CPUSRAM -> CPUSRAM ------\n");
00429 print(DMACA_RAM2RAM_EVAL_USART, " - input of 256 32bit words in CPUSRAM\n");
00430 print(DMACA_RAM2RAM_EVAL_USART, " - output of 256 32bit words in CPUSRAM\n");
00431 print(DMACA_RAM2RAM_EVAL_USART, "---------------------------------------------------\n");
00432
00433 test_ram_to_ram(256, (unsigned int *)SrcData_CpuSram, (unsigned int *)DstData_CpuSram);
00434
00435
00436
00437
00438
00439
00440
00441 print(DMACA_RAM2RAM_EVAL_USART, "\n---------------------------------------------------\n");
00442 print(DMACA_RAM2RAM_EVAL_USART, "------ DMACA transfer: HSBSRAM0 -> HSBSRAM1 ------\n");
00443 print(DMACA_RAM2RAM_EVAL_USART, " - input of 256 32bit words in HSBSRAM0\n");
00444 print(DMACA_RAM2RAM_EVAL_USART, " - output of 256 32bit words in HSBSRAM1\n");
00445 print(DMACA_RAM2RAM_EVAL_USART, "---------------------------------------------------\n");
00446
00447
00448 pSrcData_HsbSram = (unsigned int *)AVR32_INTRAM0_ADDRESS;
00449 pDstData_HsbSram = (unsigned int *)AVR32_INTRAM1_ADDRESS;
00450
00451
00452 for(i=0; i<DMACA_RAM2RAM_EVAL_BUF_SIZE; i++)
00453 *(pSrcData_HsbSram+i) = i;
00454
00455 test_ram_to_ram(256, (unsigned int *)pSrcData_HsbSram, (unsigned int *)pDstData_HsbSram);
00456
00457
00458
00459
00460
00461
00462
00463 print(DMACA_RAM2RAM_EVAL_USART, "\n---------------------------------------------------\n");
00464 print(DMACA_RAM2RAM_EVAL_USART, "------ DMACA transfer: CPUSRAM -> HSBSRAM1 ------\n");
00465 print(DMACA_RAM2RAM_EVAL_USART, " - input of 256 32bit words in CPUSRAM\n");
00466 print(DMACA_RAM2RAM_EVAL_USART, " - output of 256 32bit words in HSBSRAM1\n");
00467 print(DMACA_RAM2RAM_EVAL_USART, "---------------------------------------------------\n");
00468
00469
00470 memset((unsigned int *)pDstData_HsbSram, 0, DMACA_RAM2RAM_EVAL_BUF_SIZE*sizeof(unsigned int));
00471
00472 test_ram_to_ram(256, (unsigned int *)SrcData_CpuSram, (unsigned int *)pDstData_HsbSram);
00473
00474
00475
00476
00477
00478
00479
00480 print(DMACA_RAM2RAM_EVAL_USART, "\n---------------------------------------------------\n");
00481 print(DMACA_RAM2RAM_EVAL_USART, "------ DMACA transfer: HSBSRAM0 -> CPUSRAM ------\n");
00482 print(DMACA_RAM2RAM_EVAL_USART, " - input of 256 32bit words in HSBSRAM0\n");
00483 print(DMACA_RAM2RAM_EVAL_USART, " - output of 256 32bit words in CPUSRAM\n");
00484 print(DMACA_RAM2RAM_EVAL_USART, "---------------------------------------------------\n");
00485
00486
00487 memset((unsigned int *)DstData_CpuSram, 0, DMACA_RAM2RAM_EVAL_BUF_SIZE*sizeof(unsigned int));
00488
00489 test_ram_to_ram(256, pSrcData_HsbSram, (unsigned int *)DstData_CpuSram);
00490
00491
00492 SLEEP(AVR32_PM_SMODE_STATIC);
00493 while (TRUE);
00494 }