Definition in file pm.h.
#include <avr32/io.h>
#include "compiler.h"
#include "preprocessor.h"
Go to the source code of this file.
Data Structures | |
struct | pm_freq_param_t |
Input and output parameters when initializing PM clocks using pm_configure_clocks(). More... | |
Defines | |
#define | PM_FREQ_STATUS_FAIL (-1) |
#define | PM_FREQ_STATUS_OK (0) |
#define | SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));} |
Sets the MCU in the specified sleep mode. | |
Functions | |
void | pm_bod_clear_irq (volatile avr32_pm_t *pm) |
Clears the Brown-Out Detector interrupt flag. | |
void | pm_bod_disable_irq (volatile avr32_pm_t *pm) |
Disables the Brown-Out Detector interrupt. | |
void | pm_bod_enable_irq (volatile avr32_pm_t *pm) |
Enables the Brown-Out Detector interrupt. | |
unsigned long | pm_bod_get_irq_enable_bit (volatile avr32_pm_t *pm) |
Gets the Brown-Out Detector interrupt enable status. | |
unsigned long | pm_bod_get_irq_status (volatile avr32_pm_t *pm) |
Gets the Brown-Out Detector interrupt flag. | |
unsigned long | pm_bod_get_level (volatile avr32_pm_t *pm) |
Gets the triggering threshold of the Brown-Out Detector. | |
void | pm_cksel (volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel) |
This function will select all the power manager clocks. | |
int | pm_configure_clocks (pm_freq_param_t *param) |
Automatically configure the CPU, PBA, PBB, and HSB clocks according to the user wishes. | |
void | pm_configure_usb_clock (void) |
Automatically configure the USB clock. | |
void | pm_disable_clk0 (volatile avr32_pm_t *pm) |
This function will disable the oscillator 0. | |
void | pm_disable_clk1 (volatile avr32_pm_t *pm) |
This function will disable the oscillator 1. | |
void | pm_disable_clk32 (volatile avr32_pm_t *pm) |
This function will disable the oscillator 32. | |
long | pm_disable_module (volatile avr32_pm_t *pm, unsigned long module) |
Disable the clock of a module. | |
void | pm_enable_clk0 (volatile avr32_pm_t *pm, unsigned int startup) |
This function will enable the oscillator 0 to be used with a startup time. | |
void | pm_enable_clk0_no_wait (volatile avr32_pm_t *pm, unsigned int startup) |
This function will enable the oscillator 0 to be used with no startup time. | |
void | pm_enable_clk1 (volatile avr32_pm_t *pm, unsigned int startup) |
This function will enable the oscillator 1 to be used with a startup time. | |
void | pm_enable_clk1_no_wait (volatile avr32_pm_t *pm, unsigned int startup) |
This function will enable the oscillator 1 to be used with no startup time. | |
void | pm_enable_clk32 (volatile avr32_pm_t *pm, unsigned int startup) |
This function will enable the oscillator 32 to be used with a startup time. | |
void | pm_enable_clk32_no_wait (volatile avr32_pm_t *pm, unsigned int startup) |
This function will enable the oscillator 32 to be used with no startup time. | |
long | pm_enable_module (volatile avr32_pm_t *pm, unsigned long module) |
Enable the clock of a module. | |
void | pm_enable_osc0_crystal (volatile avr32_pm_t *pm, unsigned int fosc0) |
This function will enable the crystal mode of the oscillator 0. | |
void | pm_enable_osc0_ext_clock (volatile avr32_pm_t *pm) |
This function will enable the external clock mode of the oscillator 0. | |
void | pm_enable_osc1_crystal (volatile avr32_pm_t *pm, unsigned int fosc1) |
This function will enable the crystal mode of the oscillator 1. | |
void | pm_enable_osc1_ext_clock (volatile avr32_pm_t *pm) |
This function will enable the external clock mode of the oscillator 1. | |
void | pm_enable_osc32_crystal (volatile avr32_pm_t *pm) |
This function will enable the crystal mode of the 32-kHz oscillator. | |
void | pm_enable_osc32_ext_clock (volatile avr32_pm_t *pm) |
This function will enable the external clock mode of the 32-kHz oscillator. | |
void | pm_gc_disable (volatile avr32_pm_t *pm, unsigned int gc) |
This function will disable a generic clock. | |
void | pm_gc_enable (volatile avr32_pm_t *pm, unsigned int gc) |
This function will enable a generic clock. | |
void | pm_gc_setup (volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div) |
This function will setup a generic clock. | |
__inline__ unsigned int | pm_get_reset_cause (volatile avr32_pm_t *pm) |
Gets the MCU reset cause. | |
void | pm_pll_disable (volatile avr32_pm_t *pm, unsigned int pll) |
This function will disable a PLL. | |
void | pm_pll_enable (volatile avr32_pm_t *pm, unsigned int pll) |
This function will enable a PLL. | |
unsigned int | pm_pll_get_option (volatile avr32_pm_t *pm, unsigned int pll) |
This function will get a PLL option. | |
void | pm_pll_set_option (volatile avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pll_wbwdisable) |
This function will set a PLL option. | |
void | pm_pll_setup (volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount) |
This function will setup a PLL. | |
unsigned long | pm_read_gplp (volatile avr32_pm_t *pm, unsigned long gplp) |
Read the content of the PM GPLP registers. | |
void | pm_switch_to_clock (volatile avr32_pm_t *pm, unsigned long clock) |
This function will switch the power manager main clock. | |
void | pm_switch_to_osc0 (volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup) |
Switch main clock to clock Osc0 (crystal mode). | |
void | pm_wait_for_clk0_ready (volatile avr32_pm_t *pm) |
This function will wait until the Osc0 clock is ready. | |
void | pm_wait_for_clk1_ready (volatile avr32_pm_t *pm) |
This function will wait until the Osc1 clock is ready. | |
void | pm_wait_for_clk32_ready (volatile avr32_pm_t *pm) |
This function will wait until the osc32 clock is ready. | |
void | pm_wait_for_pll0_locked (volatile avr32_pm_t *pm) |
This function will wait for PLL0 locked. | |
void | pm_wait_for_pll1_locked (volatile avr32_pm_t *pm) |
This function will wait for PLL1 locked. | |
void | pm_write_gplp (volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value) |
Write into the PM GPLP registers. |
#define PM_FREQ_STATUS_FAIL (-1) |
#define PM_FREQ_STATUS_OK (0) |
#define SLEEP | ( | mode | ) | {__asm__ __volatile__ ("sleep "STRINGZ(mode));} |
Sets the MCU in the specified sleep mode.
mode | Sleep mode:
|
Definition at line 65 of file pm.h.
Referenced by main().
void pm_bod_clear_irq | ( | volatile avr32_pm_t * | pm | ) |
void pm_bod_disable_irq | ( | volatile avr32_pm_t * | pm | ) |
Disables the Brown-Out Detector interrupt.
pm | Base address of the Power Manager (i.e. &AVR32_PM). |
Definition at line 473 of file pm.c.
00474 { 00475 Bool global_interrupt_enabled = Is_global_interrupt_enabled(); 00476 00477 if (global_interrupt_enabled) Disable_global_interrupt(); 00478 pm->idr = AVR32_PM_IDR_BODDET_MASK; 00479 pm->isr; 00480 if (global_interrupt_enabled) Enable_global_interrupt(); 00481 }
void pm_bod_enable_irq | ( | volatile avr32_pm_t * | pm | ) |
unsigned long pm_bod_get_irq_enable_bit | ( | volatile avr32_pm_t * | pm | ) |
unsigned long pm_bod_get_irq_status | ( | volatile avr32_pm_t * | pm | ) |
unsigned long pm_bod_get_level | ( | volatile avr32_pm_t * | pm | ) |
void pm_cksel | ( | volatile avr32_pm_t * | pm, | |
unsigned int | pbadiv, | |||
unsigned int | pbasel, | |||
unsigned int | pbbdiv, | |||
unsigned int | pbbsel, | |||
unsigned int | hsbdiv, | |||
unsigned int | hsbsel | |||
) |
This function will select all the power manager clocks.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
pbadiv | Peripheral Bus A clock divisor enable | |
pbasel | Peripheral Bus A select | |
pbbdiv | Peripheral Bus B clock divisor enable | |
pbbsel | Peripheral Bus B select | |
hsbdiv | High Speed Bus clock divisor enable (CPU clock = HSB clock) | |
hsbsel | High Speed Bus select (CPU clock = HSB clock ) |
Definition at line 327 of file pm.c.
References u_avr32_pm_cksel_t::cksel, and u_avr32_pm_cksel_t::CKSEL.
Referenced by pm_configure_clocks().
00334 { 00335 u_avr32_pm_cksel_t u_avr32_pm_cksel = {0}; 00336 00337 u_avr32_pm_cksel.CKSEL.cpusel = hsbsel; 00338 u_avr32_pm_cksel.CKSEL.cpudiv = hsbdiv; 00339 u_avr32_pm_cksel.CKSEL.hsbsel = hsbsel; 00340 u_avr32_pm_cksel.CKSEL.hsbdiv = hsbdiv; 00341 u_avr32_pm_cksel.CKSEL.pbasel = pbasel; 00342 u_avr32_pm_cksel.CKSEL.pbadiv = pbadiv; 00343 u_avr32_pm_cksel.CKSEL.pbbsel = pbbsel; 00344 u_avr32_pm_cksel.CKSEL.pbbdiv = pbbdiv; 00345 00346 pm->cksel = u_avr32_pm_cksel.cksel; 00347 00348 // Wait for ckrdy bit and then clear it 00349 while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK)); 00350 }
int pm_configure_clocks | ( | pm_freq_param_t * | param | ) |
Automatically configure the CPU, PBA, PBB, and HSB clocks according to the user wishes.
This function needs some parameters stored in a pm_freq_param_t structure:
The function will then configure the clocks using the following rules:
The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.
param | pointer on the configuration structure. |
PM_FREQ_STATUS_OK | Mode successfully initialized. | |
PM_FREQ_STATUS_FAIL | The configuration can not be done. |
Definition at line 60 of file pm_conf_clocks.c.
References pm_freq_param_t::cpu_f, flashc_set_wait_state(), pm_freq_param_t::osc0_f, pm_freq_param_t::osc0_startup, pm_freq_param_t::pba_f, pm_cksel(), PM_FREQ_STATUS_FAIL, PM_FREQ_STATUS_OK, PM_MAX_MUL, pm_pll_enable(), pm_pll_set_option(), pm_pll_setup(), pm_switch_to_clock(), pm_switch_to_osc0(), and pm_wait_for_pll0_locked().
Referenced by pcl_configure_clocks().
00061 { 00062 // Supported frequencies: 00063 // Fosc0 mul div PLL div2_en cpu_f pba_f Comment 00064 // 12 15 1 192 1 12 12 00065 // 12 9 3 40 1 20 20 PLL out of spec 00066 // 12 15 1 192 1 24 12 00067 // 12 9 1 120 1 30 15 00068 // 12 9 3 40 0 40 20 PLL out of spec 00069 // 12 15 1 192 1 48 12 00070 // 12 15 1 192 1 48 24 00071 // 12 8 1 108 1 54 27 00072 // 12 9 1 120 1 60 15 00073 // 12 9 1 120 1 60 30 00074 // 12 10 1 132 1 66 16.5 00075 // 00076 unsigned long in_cpu_f = param->cpu_f; 00077 unsigned long in_osc0_f = param->osc0_f; 00078 unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0; 00079 unsigned long pll_freq, rest; 00080 Bool b_div2_pba, b_div2_cpu; 00081 00082 // Switch to external Oscillator 0 00083 pm_switch_to_osc0(&AVR32_PM, in_osc0_f, param->osc0_startup); 00084 00085 // Start with CPU freq config 00086 if (in_cpu_f == in_osc0_f) 00087 { 00088 param->cpu_f = in_osc0_f; 00089 param->pba_f = in_osc0_f; 00090 return PM_FREQ_STATUS_OK; 00091 } 00092 else if (in_cpu_f < in_osc0_f) 00093 { 00094 // TBD 00095 } 00096 00097 rest = in_cpu_f % in_osc0_f; 00098 00099 for (div = 1; div < 32; div++) 00100 { 00101 if ((div * rest) % in_osc0_f == 0) 00102 break; 00103 } 00104 if (div == 32) 00105 return PM_FREQ_STATUS_FAIL; 00106 00107 mul = (in_cpu_f * div) / in_osc0_f; 00108 00109 if (mul > PM_MAX_MUL) 00110 return PM_FREQ_STATUS_FAIL; 00111 00112 // export 2power from PLL div to div2_cpu 00113 while (!(div % 2)) 00114 { 00115 div /= 2; 00116 div2_cpu++; 00117 } 00118 00119 // Here we know the mul and div parameter of the PLL config. 00120 // . Check out if the PLL has a valid in_cpu_f. 00121 // . Try to have for the PLL frequency (VCO output) the highest possible value 00122 // to reduce jitter. 00123 while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ) 00124 { 00125 if (2 * mul > PM_MAX_MUL) 00126 break; 00127 mul *= 2; 00128 div2_cpu++; 00129 } 00130 00131 if (div2_cpu != 0) 00132 { 00133 div2_cpu--; 00134 div2_en = 1; 00135 } 00136 00137 pll_freq = in_osc0_f * mul / (div * (1 << div2_en)); 00138 00139 // Update real CPU Frequency 00140 param->cpu_f = pll_freq / (1 << div2_cpu); 00141 mul--; 00142 00143 pm_pll_setup(&AVR32_PM 00144 , 0 // pll 00145 , mul // mul 00146 , div // div 00147 , 0 // osc 00148 , 16 // lockcount 00149 ); 00150 00151 pm_pll_set_option(&AVR32_PM 00152 , 0 // pll 00153 // PLL clock is lower than 160MHz: need to set pllopt. 00154 , (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0 // pll_freq 00155 , div2_en // pll_div2 00156 , 0 // pll_wbwdisable 00157 ); 00158 00159 rest = pll_freq; 00160 while (rest > AVR32_PM_PBA_MAX_FREQ || 00161 rest != param->pba_f) 00162 { 00163 div2_pba++; 00164 rest = pll_freq / (1 << div2_pba); 00165 if (rest < param->pba_f) 00166 break; 00167 } 00168 00169 // Update real PBA Frequency 00170 param->pba_f = pll_freq / (1 << div2_pba); 00171 00172 // Enable PLL0 00173 pm_pll_enable(&AVR32_PM, 0); 00174 00175 // Wait for PLL0 locked 00176 pm_wait_for_pll0_locked(&AVR32_PM); 00177 00178 if (div2_cpu) 00179 { 00180 b_div2_cpu = TRUE; 00181 div2_cpu--; 00182 } 00183 else 00184 b_div2_cpu = FALSE; 00185 00186 if (div2_pba) 00187 { 00188 b_div2_pba = TRUE; 00189 div2_pba--; 00190 } 00191 else 00192 b_div2_pba = FALSE; 00193 00194 pm_cksel(&AVR32_PM 00195 , b_div2_pba, div2_pba // PBA 00196 , b_div2_cpu, div2_cpu // PBB 00197 , b_div2_cpu, div2_cpu // HSB 00198 ); 00199 00200 if (param->cpu_f > AVR32_FLASHC_FWS_0_MAX_FREQ) 00201 { 00202 flashc_set_wait_state(1); 00203 #if (defined AVR32_FLASHC_210_H_INCLUDED) 00204 if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ) 00205 flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1); 00206 else 00207 flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1); 00208 #endif 00209 } 00210 else 00211 { 00212 flashc_set_wait_state(0); 00213 #if (defined AVR32_FLASHC_210_H_INCLUDED) 00214 if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ) 00215 flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1); 00216 else 00217 flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1); 00218 #endif 00219 } 00220 00221 pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0); 00222 00223 return PM_FREQ_STATUS_OK; 00224 }
void pm_configure_usb_clock | ( | void | ) |
Automatically configure the USB clock.
USB clock is configured to 48MHz, using the PLL1 from the Oscillator0, assuming a 12 MHz crystal is connected to it.
Definition at line 227 of file pm_conf_clocks.c.
References pm_gc_enable(), pm_gc_setup(), pm_pll_enable(), pm_pll_set_option(), pm_pll_setup(), and pm_wait_for_pll1_locked().
Referenced by pcl_configure_usb_clock().
00228 { 00229 #if UC3A3 00230 00231 // Setup USB GCLK. 00232 pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc 00233 0, // osc_or_pll: use Osc (if 0) or PLL (if 1) 00234 0, // pll_osc: select Osc0/PLL0 or Osc1/PLL1 00235 0, // diven 00236 0); // div 00237 00238 // Enable USB GCLK. 00239 pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB); 00240 #else 00241 // Use 12MHz from OSC0 and generate 96 MHz 00242 pm_pll_setup(&AVR32_PM, 1, // pll. 00243 7, // mul. 00244 1, // div. 00245 0, // osc. 00246 16); // lockcount. 00247 00248 pm_pll_set_option(&AVR32_PM, 1, // pll. 00249 1, // pll_freq: choose the range 80-180MHz. 00250 1, // pll_div2. 00251 0); // pll_wbwdisable. 00252 00253 // start PLL1 and wait forl lock 00254 pm_pll_enable(&AVR32_PM, 1); 00255 00256 // Wait for PLL1 locked. 00257 pm_wait_for_pll1_locked(&AVR32_PM); 00258 00259 pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc. 00260 1, // osc_or_pll: use Osc (if 0) or PLL (if 1). 00261 1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1. 00262 0, // diven. 00263 0); // div. 00264 pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB); 00265 #endif 00266 }
void pm_disable_clk0 | ( | volatile avr32_pm_t * | pm | ) |
void pm_disable_clk1 | ( | volatile avr32_pm_t * | pm | ) |
void pm_disable_clk32 | ( | volatile avr32_pm_t * | pm | ) |
long pm_disable_module | ( | volatile avr32_pm_t * | pm, | |
unsigned long | module | |||
) |
Disable the clock of a module.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
module | The module to shut down (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks") |
0 | Success. | |
<0 | An error occured. |
Definition at line 533 of file pm.c.
00534 { 00535 unsigned long domain = module>>5; 00536 unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain); 00537 00538 // Implementation-specific shortcut: the ckMASK registers are contiguous and 00539 // memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK. 00540 00541 *regptr &= ~(1<<(module%32)); 00542 00543 return PASS; 00544 }
void pm_enable_clk0 | ( | volatile avr32_pm_t * | pm, | |
unsigned int | startup | |||
) |
This function will enable the oscillator 0 to be used with a startup time.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
startup | Clock 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC. |
Definition at line 173 of file pm.c.
References pm_enable_clk0_no_wait(), and pm_wait_for_clk0_ready().
Referenced by local_switch_to_osc0(), and pm_switch_to_osc0().
00174 { 00175 pm_enable_clk0_no_wait(pm, startup); 00176 pm_wait_for_clk0_ready(pm); 00177 }
void pm_enable_clk0_no_wait | ( | volatile avr32_pm_t * | pm, | |
unsigned int | startup | |||
) |
This function will enable the oscillator 0 to be used with no startup time.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
startup | Clock 0 startup time, for which the function does not wait. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC. |
Definition at line 186 of file pm.c.
References u_avr32_pm_oscctrl0_t::oscctrl0, and u_avr32_pm_oscctrl0_t::OSCCTRL0.
Referenced by pm_enable_clk0().
00187 { 00188 // Read register 00189 u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0}; 00190 // Modify 00191 u_avr32_pm_oscctrl0.OSCCTRL0.startup = startup; 00192 // Write back 00193 pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0; 00194 00195 pm->mcctrl |= AVR32_PM_MCCTRL_OSC0EN_MASK; 00196 }
void pm_enable_clk1 | ( | volatile avr32_pm_t * | pm, | |
unsigned int | startup | |||
) |
This function will enable the oscillator 1 to be used with a startup time.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
startup | Clock 1 startup time. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC. |
Definition at line 236 of file pm.c.
References pm_enable_clk1_no_wait(), and pm_wait_for_clk1_ready().
00237 { 00238 pm_enable_clk1_no_wait(pm, startup); 00239 pm_wait_for_clk1_ready(pm); 00240 }
void pm_enable_clk1_no_wait | ( | volatile avr32_pm_t * | pm, | |
unsigned int | startup | |||
) |
This function will enable the oscillator 1 to be used with no startup time.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
startup | Clock 1 startup time, for which the function does not wait. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC. |
Definition at line 249 of file pm.c.
References u_avr32_pm_oscctrl1_t::oscctrl1, and u_avr32_pm_oscctrl1_t::OSCCTRL1.
Referenced by pm_enable_clk1().
00250 { 00251 // Read register 00252 u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1}; 00253 // Modify 00254 u_avr32_pm_oscctrl1.OSCCTRL1.startup = startup; 00255 // Write back 00256 pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1; 00257 00258 pm->mcctrl |= AVR32_PM_MCCTRL_OSC1EN_MASK; 00259 }
void pm_enable_clk32 | ( | volatile avr32_pm_t * | pm, | |
unsigned int | startup | |||
) |
This function will enable the oscillator 32 to be used with a startup time.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
startup | Clock 32 kHz startup time. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC. |
Definition at line 296 of file pm.c.
References pm_enable_clk32_no_wait(), and pm_wait_for_clk32_ready().
00297 { 00298 pm_enable_clk32_no_wait(pm, startup); 00299 pm_wait_for_clk32_ready(pm); 00300 }
void pm_enable_clk32_no_wait | ( | volatile avr32_pm_t * | pm, | |
unsigned int | startup | |||
) |
This function will enable the oscillator 32 to be used with no startup time.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
startup | Clock 32 kHz startup time, for which the function does not wait. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC. |
Definition at line 309 of file pm.c.
References u_avr32_pm_oscctrl32_t::oscctrl32, and u_avr32_pm_oscctrl32_t::OSCCTRL32.
Referenced by pm_enable_clk32().
00310 { 00311 // Read register 00312 u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32}; 00313 // Modify 00314 u_avr32_pm_oscctrl32.OSCCTRL32.osc32en = 1; 00315 u_avr32_pm_oscctrl32.OSCCTRL32.startup = startup; 00316 // Write back 00317 pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32; 00318 }
long pm_enable_module | ( | volatile avr32_pm_t * | pm, | |
unsigned long | module | |||
) |
Enable the clock of a module.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
module | The module to clock (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks") |
0 | Success. | |
<0 | An error occured. |
Definition at line 520 of file pm.c.
00521 { 00522 unsigned long domain = module>>5; 00523 unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain); 00524 00525 // Implementation-specific shortcut: the ckMASK registers are contiguous and 00526 // memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK. 00527 00528 *regptr |= (1<<(module%32)); 00529 00530 return PASS; 00531 }
void pm_enable_osc0_crystal | ( | volatile avr32_pm_t * | pm, | |
unsigned int | fosc0 | |||
) |
This function will enable the crystal mode of the oscillator 0.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
fosc0 | Oscillator 0 crystal frequency (Hz) |
Definition at line 164 of file pm.c.
References pm_set_osc0_mode().
Referenced by local_switch_to_osc0(), and pm_switch_to_osc0().
00165 { 00166 pm_set_osc0_mode(pm, (fosc0 < 900000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G0 : 00167 (fosc0 < 3000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G1 : 00168 (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 : 00169 AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3); 00170 }
void pm_enable_osc0_ext_clock | ( | volatile avr32_pm_t * | pm | ) |
This function will enable the external clock mode of the oscillator 0.
pm | Base address of the Power Manager (i.e. &AVR32_PM) |
Definition at line 158 of file pm.c.
References pm_set_osc0_mode().
00159 { 00160 pm_set_osc0_mode(pm, AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK); 00161 }
void pm_enable_osc1_crystal | ( | volatile avr32_pm_t * | pm, | |
unsigned int | fosc1 | |||
) |
This function will enable the crystal mode of the oscillator 1.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
fosc1 | Oscillator 1 crystal frequency (Hz) |
Definition at line 227 of file pm.c.
References pm_set_osc1_mode().
00228 { 00229 pm_set_osc1_mode(pm, (fosc1 < 900000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G0 : 00230 (fosc1 < 3000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G1 : 00231 (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 : 00232 AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3); 00233 }
void pm_enable_osc1_ext_clock | ( | volatile avr32_pm_t * | pm | ) |
This function will enable the external clock mode of the oscillator 1.
pm | Base address of the Power Manager (i.e. &AVR32_PM) |
Definition at line 221 of file pm.c.
References pm_set_osc1_mode().
00222 { 00223 pm_set_osc1_mode(pm, AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK); 00224 }
void pm_enable_osc32_crystal | ( | volatile avr32_pm_t * | pm | ) |
This function will enable the crystal mode of the 32-kHz oscillator.
pm | Base address of the Power Manager (i.e. &AVR32_PM) |
Definition at line 290 of file pm.c.
References pm_set_osc32_mode().
00291 { 00292 pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_CRYSTAL); 00293 }
void pm_enable_osc32_ext_clock | ( | volatile avr32_pm_t * | pm | ) |
This function will enable the external clock mode of the 32-kHz oscillator.
pm | Base address of the Power Manager (i.e. &AVR32_PM) |
Definition at line 284 of file pm.c.
References pm_set_osc32_mode().
00285 { 00286 pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK); 00287 }
void pm_gc_disable | ( | volatile avr32_pm_t * | pm, | |
unsigned int | gc | |||
) |
void pm_gc_enable | ( | volatile avr32_pm_t * | pm, | |
unsigned int | gc | |||
) |
This function will enable a generic clock.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
gc | generic clock number (0 for gc0...) |
Definition at line 371 of file pm.c.
Referenced by local_enable_gclk_on_gpio(), and pm_configure_usb_clock().
void pm_gc_setup | ( | volatile avr32_pm_t * | pm, | |
unsigned int | gc, | |||
unsigned int | osc_or_pll, | |||
unsigned int | pll_osc, | |||
unsigned int | diven, | |||
unsigned int | div | |||
) |
This function will setup a generic clock.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
gc | generic clock number (0 for gc0...) | |
osc_or_pll | Use OSC (=0) or PLL (=1) | |
pll_osc | Select Osc0/PLL0 or Osc1/PLL1 | |
diven | Generic clock divisor enable | |
div | Generic clock divisor |
Definition at line 353 of file pm.c.
References u_avr32_pm_gcctrl_t::gcctrl, and u_avr32_pm_gcctrl_t::GCCTRL.
Referenced by local_enable_gclk_on_gpio(), and pm_configure_usb_clock().
00359 { 00360 u_avr32_pm_gcctrl_t u_avr32_pm_gcctrl = {0}; 00361 00362 u_avr32_pm_gcctrl.GCCTRL.oscsel = pll_osc; 00363 u_avr32_pm_gcctrl.GCCTRL.pllsel = osc_or_pll; 00364 u_avr32_pm_gcctrl.GCCTRL.diven = diven; 00365 u_avr32_pm_gcctrl.GCCTRL.div = div; 00366 00367 pm->gcctrl[gc] = u_avr32_pm_gcctrl.gcctrl; 00368 }
__inline__ unsigned int pm_get_reset_cause | ( | volatile avr32_pm_t * | pm | ) |
void pm_pll_disable | ( | volatile avr32_pm_t * | pm, | |
unsigned int | pll | |||
) |
void pm_pll_enable | ( | volatile avr32_pm_t * | pm, | |
unsigned int | pll | |||
) |
This function will enable a PLL.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
pll | PLL number(0 for PLL0, 1 for PLL1) |
Definition at line 422 of file pm.c.
Referenced by pm_configure_clocks(), and pm_configure_usb_clock().
unsigned int pm_pll_get_option | ( | volatile avr32_pm_t * | pm, | |
unsigned int | pll | |||
) |
void pm_pll_set_option | ( | volatile avr32_pm_t * | pm, | |
unsigned int | pll, | |||
unsigned int | pll_freq, | |||
unsigned int | pll_div2, | |||
unsigned int | pll_wbwdisable | |||
) |
This function will set a PLL option.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
pll | PLL number(0 for PLL0, 1 for PLL1) | |
pll_freq | Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. | |
pll_div2 | Divide the PLL output frequency by 2 (this settings does not change the FVCO value) | |
pll_wbwdisable | 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. |
Definition at line 403 of file pm.c.
References u_avr32_pm_pll_t::pll, and u_avr32_pm_pll_t::PLL.
Referenced by pm_configure_clocks(), and pm_configure_usb_clock().
00408 { 00409 u_avr32_pm_pll_t u_avr32_pm_pll = {pm->pll[pll]}; 00410 u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2); 00411 pm->pll[pll] = u_avr32_pm_pll.pll; 00412 }
void pm_pll_setup | ( | volatile avr32_pm_t * | pm, | |
unsigned int | pll, | |||
unsigned int | mul, | |||
unsigned int | div, | |||
unsigned int | osc, | |||
unsigned int | lockcount | |||
) |
This function will setup a PLL.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
pll | PLL number(0 for PLL0, 1 for PLL1) | |
mul | PLL MUL in the PLL formula | |
div | PLL DIV in the PLL formula | |
osc | OSC number (0 for osc0, 1 for osc1) | |
lockcount | PLL lockount |
Definition at line 385 of file pm.c.
References u_avr32_pm_pll_t::pll, and u_avr32_pm_pll_t::PLL.
Referenced by pm_configure_clocks(), and pm_configure_usb_clock().
00391 { 00392 u_avr32_pm_pll_t u_avr32_pm_pll = {0}; 00393 00394 u_avr32_pm_pll.PLL.pllosc = osc; 00395 u_avr32_pm_pll.PLL.plldiv = div; 00396 u_avr32_pm_pll.PLL.pllmul = mul; 00397 u_avr32_pm_pll.PLL.pllcount = lockcount; 00398 00399 pm->pll[pll] = u_avr32_pm_pll.pll; 00400 }
unsigned long pm_read_gplp | ( | volatile avr32_pm_t * | pm, | |
unsigned long | gplp | |||
) |
Read the content of the PM GPLP registers.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
gplp | GPLP register index (0,1,... depending on the number of GPLP registers for a given part) |
Definition at line 508 of file pm.c.
Referenced by pcl_read_gplp().
void pm_switch_to_clock | ( | volatile avr32_pm_t * | pm, | |
unsigned long | clock | |||
) |
This function will switch the power manager main clock.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
clock | Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0. |
Definition at line 448 of file pm.c.
References u_avr32_pm_mcctrl_t::mcctrl, and u_avr32_pm_mcctrl_t::MCCTRL.
Referenced by local_switch_to_osc0(), pm_configure_clocks(), and pm_switch_to_osc0().
00449 { 00450 // Read 00451 u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl}; 00452 // Modify 00453 u_avr32_pm_mcctrl.MCCTRL.mcsel = clock; 00454 // Write back 00455 pm->mcctrl = u_avr32_pm_mcctrl.mcctrl; 00456 }
void pm_switch_to_osc0 | ( | volatile avr32_pm_t * | pm, | |
unsigned int | fosc0, | |||
unsigned int | startup | |||
) |
Switch main clock to clock Osc0 (crystal mode).
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
fosc0 | Oscillator 0 crystal frequency (Hz) | |
startup | Crystal 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC. |
Definition at line 459 of file pm.c.
References pm_enable_clk0(), pm_enable_osc0_crystal(), and pm_switch_to_clock().
Referenced by pcl_switch_to_osc(), and pm_configure_clocks().
00460 { 00461 pm_enable_osc0_crystal(pm, fosc0); // Enable the Osc0 in crystal mode 00462 pm_enable_clk0(pm, startup); // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal 00463 pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0); // Then switch main clock to Osc0 00464 }
void pm_wait_for_clk0_ready | ( | volatile avr32_pm_t * | pm | ) |
This function will wait until the Osc0 clock is ready.
pm | Base address of the Power Manager (i.e. &AVR32_PM) |
Definition at line 199 of file pm.c.
Referenced by pm_enable_clk0().
void pm_wait_for_clk1_ready | ( | volatile avr32_pm_t * | pm | ) |
This function will wait until the Osc1 clock is ready.
pm | Base address of the Power Manager (i.e. &AVR32_PM) |
Definition at line 262 of file pm.c.
Referenced by pm_enable_clk1().
void pm_wait_for_clk32_ready | ( | volatile avr32_pm_t * | pm | ) |
This function will wait until the osc32 clock is ready.
pm | Base address of the Power Manager (i.e. &AVR32_PM) |
Definition at line 321 of file pm.c.
Referenced by pm_enable_clk32().
void pm_wait_for_pll0_locked | ( | volatile avr32_pm_t * | pm | ) |
This function will wait for PLL0 locked.
pm | Base address of the Power Manager (i.e. &AVR32_PM) |
Definition at line 436 of file pm.c.
Referenced by pm_configure_clocks().
void pm_wait_for_pll1_locked | ( | volatile avr32_pm_t * | pm | ) |
This function will wait for PLL1 locked.
pm | Base address of the Power Manager (i.e. &AVR32_PM) |
Definition at line 442 of file pm.c.
Referenced by pm_configure_usb_clock().
void pm_write_gplp | ( | volatile avr32_pm_t * | pm, | |
unsigned long | gplp, | |||
unsigned long | value | |||
) |
Write into the PM GPLP registers.
pm | Base address of the Power Manager (i.e. &AVR32_PM) | |
gplp | GPLP register index (0,1,... depending on the number of GPLP registers for a given part) | |
value | Value to write |
Definition at line 514 of file pm.c.
Referenced by pcl_write_gplp().