Definition in file scif_example1.c.
#include "board.h"
#include "gpio.h"
#include "scif_uc3l.h"
#include "power_clocks_lib.h"
Go to the source code of this file.
Defines | |
Generic Clock Configuration | |
#define | EXAMPLE_FDFLL_HZ 22579200 |
#define | EXAMPLE_FDFLL_KHZ 22579 |
The target output frequency (22MHz) of the DFLL. | |
#define | EXAMPLE_GCLK_FREQ_HZ 44100 |
The target frequency (44kHz) of the generic clock. | |
#define | EXAMPLE_GCLK_FUNCTION AVR32_SCIF_GCLK_1_0_FUNCTION |
#define | EXAMPLE_GCLK_ID AVR32_SCIF_GCLK_DFLL0_SSG |
#define | EXAMPLE_GCLK_PIN AVR32_SCIF_GCLK_1_0_PIN |
Functions | |
static void | local_start_dfll_clock () |
Generate a high frequency clock with a DFLL running in closed-loop mode. | |
static void | local_start_gc () |
Set-up a generic clock at 44kz with the DFLL as a source, output the generic clock to a pin. | |
int | main (void) |
#define EXAMPLE_FDFLL_HZ 22579200 |
Definition at line 106 of file scif_example1.c.
Referenced by local_start_dfll_clock(), and local_start_gc().
#define EXAMPLE_FDFLL_KHZ 22579 |
#define EXAMPLE_GCLK_FREQ_HZ 44100 |
The target frequency (44kHz) of the generic clock.
Definition at line 109 of file scif_example1.c.
Referenced by local_start_gc().
#define EXAMPLE_GCLK_FUNCTION AVR32_SCIF_GCLK_1_0_FUNCTION |
#define EXAMPLE_GCLK_ID AVR32_SCIF_GCLK_DFLL0_SSG |
#define EXAMPLE_GCLK_PIN AVR32_SCIF_GCLK_1_0_PIN |
static void local_start_dfll_clock | ( | ) | [static] |
Generate a high frequency clock with a DFLL running in closed-loop mode.
Definition at line 116 of file scif_example1.c.
References scif_gclk_opt_t::clock_source, scif_dfll_closedloop_conf_t::coarse, scif_dfll_closedloop_conf_t::coarsemaxstep, scif_gclk_opt_t::diven, EXAMPLE_FDFLL_HZ, scif_dfll_closedloop_conf_t::finemaxstep, scif_dfll_closedloop_conf_t::fmul, scif_dfll0_closedloop_mainref_gc_enable, scif_dfll0_closedloop_start(), SCIF_DFLL_MAXFREQ_HZ, SCIF_DFLL_MINFREQ_HZ, SCIF_GCCTRL_SLOWCLOCK, and SCIF_SLOWCLOCK_FREQ_HZ.
Referenced by main().
00117 { 00118 scif_dfll_closedloop_conf_t DfllConfig; 00119 scif_gclk_opt_t GcConf; 00120 00121 00122 // 1) Configure and start the DFLL main reference generic clock: 00123 // use the undivided RCOSC slow clock as source for the generic clock. The 00124 // generic clock frequency will thus be ~115kHz. 00125 GcConf.clock_source = SCIF_GCCTRL_SLOWCLOCK; 00126 GcConf.diven = OFF; 00127 // Note: this function will start the AVR32_SCIF_GCLK_DFLL0_REF generic clock 00128 // (i.e. the generic clock dedicated to be the DFLL main reference clock). 00129 scif_dfll0_closedloop_mainref_gc_enable(&GcConf); 00130 00131 // 2) Configure and start the DFLL. 00132 // The coarse value (= (fDFLL - SCIF_DFLL_MINFREQ_KHZ)*255/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ)) 00133 DfllConfig.coarse = ((unsigned long long)(EXAMPLE_FDFLL_HZ - SCIF_DFLL_MINFREQ_HZ)*255)/(SCIF_DFLL_MAXFREQ_HZ - SCIF_DFLL_MINFREQ_HZ); 00134 // The fmul value (= (fDFLL*2^16)/fref, with fref being the frequency of the 00135 // DFLL main reference generic clock) 00136 DfllConfig.fmul = ((unsigned long long)EXAMPLE_FDFLL_HZ<<16)/SCIF_SLOWCLOCK_FREQ_HZ; 00137 // The fine and coarse maxstep values 00138 #if (defined(__GNUC__) \ 00139 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \ 00140 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \ 00141 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__))) 00142 // UC3L revC and higher 00143 DfllConfig.finemaxstep = 0x0000004; 00144 DfllConfig.coarsemaxstep = 0x0000004; 00145 #else 00146 // UC3L revB 00147 //+ Errata UC3L revB: 35.2.7 SCIF.12 DFLLIF indicates coarse lock too early 00148 //+ The DFLLIF might indicate coarse lock too early, the DFLL will lose 00149 //+ coarse lock and regain it later. 00150 //+ Fix/Workaround 00151 //+ Use max step size (DFLL0MAXSTEP.MAXSTEP) of 4 or higher. 00152 DfllConfig.maxstep = 0x0040004; 00153 #endif 00154 scif_dfll0_closedloop_start(&DfllConfig); 00155 }
static void local_start_gc | ( | ) | [static] |
Set-up a generic clock at 44kz with the DFLL as a source, output the generic clock to a pin.
Definition at line 162 of file scif_example1.c.
References EXAMPLE_FDFLL_HZ, EXAMPLE_GCLK_FREQ_HZ, EXAMPLE_GCLK_FUNCTION, EXAMPLE_GCLK_ID, EXAMPLE_GCLK_PIN, scif_gc_enable(), scif_gc_setup(), and SCIF_GCCTRL_DFLL0.
Referenced by main().
00163 { 00164 // Setup gc on DFLL; the target frequency is 44kHz => divide the DFLL frequency 00165 // by 512 (== EXAMPLE_FDFLL_HZ / EXAMPLE_GCLK_FREQ_HZ). 00166 scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_DFLL0, AVR32_GC_DIV_CLOCK, 00167 EXAMPLE_FDFLL_HZ/EXAMPLE_GCLK_FREQ_HZ); 00168 00169 // Now enable the generic clock 00170 scif_gc_enable(EXAMPLE_GCLK_ID); 00171 00172 /* Assign a GPIO to generic clock output */ 00173 gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION); 00174 // Note that gclk1 is GPIO pin 6 pa06 on AT32UC3L064 pin 10 on QFP48. 00175 }
int main | ( | void | ) |
Definition at line 186 of file scif_example1.c.
References local_start_dfll_clock(), and local_start_gc().
00187 { 00188 // Generate a high frequency clock (~22MHz) with a DFLL in closed-loop mode 00189 local_start_dfll_clock(); 00190 00191 // Set-up a generic clock from a high frequency clock and output it to a gpio pin. 00192 local_start_gc(); 00193 00194 //*** Sleep mode 00195 // If there is a chance that any PB write operations are incomplete, the CPU 00196 // should perform a read operation from any register on the PB bus before 00197 // executing the sleep instruction. 00198 AVR32_INTC.ipr[0]; // Dummy read 00199 00200 // - Go into a sleep mode (while still maintaining GCLK output) 00201 SLEEP(AVR32_PM_SMODE_FROZEN); 00202 00203 while(1); 00204 }