Copyright © 2007 Atmel Corporation
The Analog-to-Digital Converter (ADC) is fully differential and based on a 12-bit pipelined topol- ogy using switched capacitors circuitry. Two sample and hold (S/H) running simultaneously with 1, 2, 4, 8, 16, 32, 64 gain factors are feeding a single ADC analog block so that the system acts as if there were two conversion running in parallel. It can be configured as a 8-bit 10-bit or 12-bit ADC and is capable of converting 1.5 million samples per second thanks to its pipeline topology. 10-bit and 8-bit conversion resolution can be achieved at higher conversion rates. Note that results are always signed in 2's complement.
Note: The pipelined topology implies a latency between the sampling event and the update of the result register of: (Resolution(SRES)/2 + 3 - SHD) · T(CkADC)
The ADC has an internal defined conversion range of ±1.0V. An additional internal reference mode allows conversion range of ±0.6·VDDANA. In addition, the ADC may operate with external references for different conversion ranges. When internal reference is used, the external refer- ence pins should be decoupled in order to achieve full accuracy of the ADC.
The driver is composed of adcifa.c and adcifa.h.
An example is available: How to use the ADCIFA in sequencer mode.