This file provides an example for the PWM4 on AVR32 UC3 devices.
Definition in file pwm4_example.c.
#include <avr32/io.h>
#include "pwm4.h"
#include "gpio.h"
#include "board.h"
#include "power_clocks_lib.h"
#include "pm_uc3c.h"
#include "scif_uc3c.h"
Go to the source code of this file.
Defines | |
PWM Configuration | |
#define | EXAMPLE_PWM_CHANNEL_ID 0 |
#define | EXAMPLE_PWM_H_FUNCTION AVR32_PWM_PWMH_0_1_FUNCTION |
#define | EXAMPLE_PWM_H_PIN AVR32_PWM_PWMH_0_1_PIN |
#define | EXAMPLE_PWM_L_FUNCTION AVR32_PWM_PWML_0_1_FUNCTION |
#define | EXAMPLE_PWM_L_PIN AVR32_PWM_PWML_0_1_PIN |
Functions | |
static void | local_start_highfreq_clock (void) |
int | main (void) |
Main function. Execution starts here. | |
static void | pwm_start_gc () |
#define EXAMPLE_PWM_CHANNEL_ID 0 |
#define EXAMPLE_PWM_H_FUNCTION AVR32_PWM_PWMH_0_1_FUNCTION |
#define EXAMPLE_PWM_H_PIN AVR32_PWM_PWMH_0_1_PIN |
#define EXAMPLE_PWM_L_FUNCTION AVR32_PWM_PWML_0_1_FUNCTION |
#define EXAMPLE_PWM_L_PIN AVR32_PWM_PWML_0_1_PIN |
static void local_start_highfreq_clock | ( | void | ) | [static] |
Definition at line 105 of file pwm4_example.c.
Referenced by main().
00106 { 00107 const scif_pll_opt_t opt = { 00108 .osc = SCIF_OSC0, // Sel Osc0/PLL0 or Osc1/PLL1 00109 .lockcount = 16, // lockcount in main clock for the PLL wait lock 00110 .div = 1, // DIV=1 in the formula 00111 .mul = 6, // MUL=7 in the formula 00112 .pll_div2 = 1, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) 00113 .pll_wbwdisable = 0, // pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. 00114 .pll_freq = 1, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. 00115 }; 00116 // Switch main clock to Osc0. 00117 pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP); 00118 00119 /* Setup PLL0 on Osc0, mul=7 ,no divisor, lockcount=16, ie. (16Mhzx7)/(div2) = 56MHz output */ 00120 scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock 00121 00122 /* Enable PLL0 */ 00123 scif_pll_enable(SCIF_PLL0); 00124 00125 /* Wait for PLL0 locked */ 00126 scif_wait_for_pll_locked(SCIF_PLL0) ; 00127 }
int main | ( | void | ) |
Main function. Execution starts here.
Definition at line 144 of file pwm4_example.c.
References pwm_opt_t::cksel, pwm_opt_t::diva, pwm_opt_t::divb, EXAMPLE_PWM_CHANNEL_ID, EXAMPLE_PWM_H_FUNCTION, EXAMPLE_PWM_H_PIN, EXAMPLE_PWM_L_FUNCTION, EXAMPLE_PWM_L_PIN, pwm_opt_t::fault_detection_activated, local_start_highfreq_clock(), pwm_opt_t::prea, pwm_opt_t::preb, pwm_channel_init(), PWM_CKSEL_GCLK, pwm_init(), PWM_MODE_LEFT_ALIGNED, PWM_POLARITY_LOW, pwm_start_channels(), pwm_start_gc(), PWM_SYNC_UPDATE_MANUAL_WRITE_MANUAL_UPDATE, pwm_update_period_value(), pwm_opt_t::sync_channel_activated, pwm_opt_t::sync_channel_select, and pwm_opt_t::sync_update_channel_mode.
00145 { 00146 pwm_opt_t pwm_opt; // PWM option config. 00147 avr32_pwm_channel_t pwm_channel = {{0}, // cmr 00148 {0}, // cdty 00149 {0}, // cdtyupd 00150 {0}, // cprd 00151 {0}, // cprdupd 00152 {0}, // ccnt 00153 {0}, // dt 00154 {0}};// dtupd ; One channel config. 00155 unsigned int channel_id; 00156 00157 // Start Main Clock On external 16MHz Oscillator 00158 // Start PLL for PWM 00159 local_start_highfreq_clock(); 00160 // Start Enable Generic Clock with PLL as source clock 00161 pwm_start_gc(); 00162 00163 channel_id = EXAMPLE_PWM_CHANNEL_ID; 00164 gpio_enable_module_pin(EXAMPLE_PWM_L_PIN, EXAMPLE_PWM_L_FUNCTION); 00165 gpio_enable_module_pin(EXAMPLE_PWM_H_PIN, EXAMPLE_PWM_H_FUNCTION); 00166 // PWM controller configuration. 00167 pwm_opt.diva = AVR32_PWM_DIVA_CLK_OFF; 00168 pwm_opt.divb = AVR32_PWM_DIVB_CLK_OFF; 00169 pwm_opt.prea = AVR32_PWM_PREA_CCK; 00170 pwm_opt.preb = AVR32_PWM_PREB_CCK; 00171 00172 pwm_opt.fault_detection_activated = FALSE; 00173 pwm_opt.sync_channel_activated = TRUE; 00174 pwm_opt.sync_update_channel_mode = PWM_SYNC_UPDATE_MANUAL_WRITE_MANUAL_UPDATE; 00175 pwm_opt.sync_channel_select[0] = TRUE; 00176 pwm_opt.sync_channel_select[1] = TRUE; 00177 pwm_opt.sync_channel_select[2] = FALSE; 00178 pwm_opt.sync_channel_select[3] = FALSE; 00179 pwm_opt.cksel = PWM_CKSEL_GCLK; 00180 pwm_init(&pwm_opt); 00181 00182 // Update the period 00183 pwm_update_period_value(10); 00184 00185 // Channel configuration 00186 pwm_channel.CMR.dte = 1; // Enable Deadtime for complementary Mode 00187 pwm_channel.CMR.dthi = 1; // Deadtime Inverted on PWMH 00188 pwm_channel.CMR.dtli = 0; // Deadtime Not Inverted on PWML 00189 pwm_channel.CMR.ces = 0; // 0/1 Channel Event at the End of PWM Period 00190 pwm_channel.CMR.calg = PWM_MODE_LEFT_ALIGNED; // Channel mode. 00191 pwm_channel.CMR.cpol = PWM_POLARITY_LOW; // Channel polarity. 00192 pwm_channel.CMR.cpre = AVR32_PWM_CPRE_CCK; // Channel prescaler. 00193 pwm_channel.cdty = 10; // Channel duty cycle, should be < CPRD. 00194 pwm_channel.cprd = 20; // Channel period. 00195 00196 // With these settings, the output waveform period will be : 00197 // (56MHz)/20 == 2.8MHz == (MCK/prescaler)/period, with MCK == 56MHz, 00198 // prescaler == 1, period == 20. 00199 00200 pwm_channel_init(channel_id, &pwm_channel); // Set channel configuration to channel 0 00201 pwm_start_channels((1 << channel_id)); // Start channel 0 & 1. 00202 00203 while(1); 00204 }
static void pwm_start_gc | ( | ) | [static] |
Definition at line 130 of file pwm4_example.c.
Referenced by main().
00131 { 00132 scif_gc_setup(AVR32_SCIF_GCLK_PWM, 00133 SCIF_GCCTRL_PLL0, 00134 AVR32_SCIF_GC_NO_DIV_CLOCK, 00135 0); 00136 // Now enable the generic clock 00137 scif_gc_enable(AVR32_SCIF_GCLK_PWM); 00138 }