Definition in file scif_uc3l.c.
#include "compiler.h"
#include "scif_uc3l.h"
Go to the source code of this file.
Data Structures | |
union | u_avr32_scif_dfll0conf_t |
union | u_avr32_scif_dfll0ssg_t |
union | u_avr32_scif_oscctrl0_t |
union | u_avr32_scif_oscctrl32_t |
Defines | |
#define | SCIF_DFLL_COARSE_MAX (AVR32_SCIF_COARSE_MASK >> AVR32_SCIF_COARSE_OFFSET) |
#define | SCIF_DFLL_FINE_HALF (1 << (AVR32_SCIF_DFLL0CONF_FINE_SIZE-1)) |
#define | SCIF_DFLL_FINE_MAX (AVR32_SCIF_FINE_MASK >> AVR32_SCIF_FINE_OFFSET) |
Enumerations | |
enum | scif_dfll_mode_t { SCIF_DFLL0_MODE_OPENLOOP = 0, SCIF_DFLL0_MODE_CLOSEDLOOP } |
DFLL Control Functions. More... | |
Functions | |
long int | scif_configure_osc_crystalmode (scif_osc_t osc, unsigned int fcrystal) |
Configure an oscillator in crystal mode. | |
long int | scif_dfll0_closedloop_configure_and_start (const scif_gclk_opt_t *gc_dfllif_ref_opt, unsigned long long target_freq_hz, bool enable_ssg) |
Depending on the target frequency, compute the DFLL configuration parameters and start the DFLL0 in closed loop mode. | |
long int | scif_dfll0_closedloop_start (const scif_dfll_closedloop_conf_t *pdfllconfig) |
Configure and start the DFLL0 in closed loop mode. | |
long int | scif_dfll0_openloop_start (const scif_dfll_openloop_conf_t *pdfllconfig) |
Configure and start the DFLL0 in open loop mode. | |
long int | scif_dfll0_openloop_start_auto (unsigned long TargetFreqkHz) |
Automatic configuration and start of the DFLL0 in open loop mode. | |
long int | scif_dfll0_openloop_stop (void) |
Stop the DFLL0 in open loop mode. | |
long int | scif_dfll0_openloop_updatefreq (const scif_dfll_openloop_conf_t *pdfllconfig) |
Update the frequency of the DFLL0 in open loop mode. | |
long int | scif_dfll0_ssg_enable (scif_dfll_ssg_conf_t *pssg_conf) |
Configure and enable the SSG. | |
void | scif_disable_rc32out (void) |
Unforce the RC32 signal from being output on the dedicated pin (PB04 on revB, PA20 on revC and later). | |
long int | scif_enable_osc (scif_osc_t osc, unsigned int startup, bool wait_for_ready) |
Enable an oscillator with a given startup time. | |
long int | scif_gc_enable (unsigned int gclk) |
Enable a generic clock. | |
long int | scif_gc_setup (unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor) |
Setup a generic clock. | |
bool | scif_is_osc_ready (scif_osc_t osc) |
Is an oscillator stable and ready to be used as clock source? | |
long int | scif_pclksr_statushigh_wait (unsigned long statusMask) |
Backup Registers Functions. | |
long int | scif_start_gclk (unsigned int gclk, const scif_gclk_opt_t *opt) |
Generic Clock Functions. | |
long int | scif_start_osc (scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready) |
Interrupt Functions. | |
long int | scif_start_osc32 (const scif_osc32_opt_t *opt, bool wait_for_ready) |
OSC32 Functions. | |
void | scif_start_rc120M (void) |
Calibration Functions. | |
void | scif_start_rc32k (void) |
32kHz internal RCosc (RC32K) Functions | |
long int | scif_stop_gclk (unsigned int gclk) |
Stop a generic clock. | |
long int | scif_stop_osc (scif_osc_t osc) |
Stop an oscillator. | |
long | scif_stop_osc32 () |
Stop the OSC32 oscillator. | |
void | scif_stop_rc120M (void) |
Stop the 120MHz internal RCosc (RC120M) clock. | |
void | scif_stop_rc32k (void) |
Stop the 32kHz internal RCosc (RC32K) clock. |
#define SCIF_DFLL_COARSE_MAX (AVR32_SCIF_COARSE_MASK >> AVR32_SCIF_COARSE_OFFSET) |
#define SCIF_DFLL_FINE_HALF (1 << (AVR32_SCIF_DFLL0CONF_FINE_SIZE-1)) |
#define SCIF_DFLL_FINE_MAX (AVR32_SCIF_FINE_MASK >> AVR32_SCIF_FINE_OFFSET) |
enum scif_dfll_mode_t |
DFLL Control Functions.
The different DFLL0 modes
Definition at line 336 of file scif_uc3l.c.
00337 { 00338 SCIF_DFLL0_MODE_OPENLOOP = 0, 00339 SCIF_DFLL0_MODE_CLOSEDLOOP 00340 } scif_dfll_mode_t;
long int scif_configure_osc_crystalmode | ( | scif_osc_t | osc, | |
unsigned int | fcrystal | |||
) |
Configure an oscillator in crystal mode.
osc | The oscillator to configure [INPUT] | |
fcrystal | Crystal frequency (Hz) [INPUT] |
0 | Oscillator successfully configured. | |
<0 | Error configuring the oscillator. |
Definition at line 179 of file scif_uc3l.c.
References u_avr32_scif_oscctrl_t::OSCCTRL, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, SCIF_OSC0, SCIF_OSC1, SCIF_OSC_MODE_2PIN_CRYSTAL, and SCIF_UNLOCK.
00180 { 00181 //# Implementation note: this code doesn't consider the osc input parameter 00182 //# because UC3L devices only implement OSC0. 00183 u_avr32_scif_oscctrl0_t u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0}; 00184 00185 // Configure the oscillator mode to crystal and set the gain according to the 00186 // cyrstal frequency. 00187 u_avr32_scif_oscctrl0.OSCCTRL0.mode = SCIF_OSC_MODE_2PIN_CRYSTAL; 00188 u_avr32_scif_oscctrl0.OSCCTRL0.gain = (fcrystal < 900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 : 00189 (fcrystal < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 : 00190 (fcrystal < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 : 00191 AVR32_SCIF_OSCCTRL0_GAIN_G3; 00192 AVR32_ENTER_CRITICAL_REGION( ); 00193 // Unlock the write-protected OSCCTRL0 register 00194 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0); 00195 // Write 00196 AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0; 00197 AVR32_LEAVE_CRITICAL_REGION( ); 00198 // Add here after support for OSC1 for devices that implement OSC1. 00199 00200 return PASS; 00201 }
long int scif_dfll0_closedloop_configure_and_start | ( | const scif_gclk_opt_t * | gc_dfllif_ref_opt, | |
unsigned long long | target_freq_hz, | |||
bool | enable_ssg | |||
) |
Depending on the target frequency, compute the DFLL configuration parameters and start the DFLL0 in closed loop mode.
This function only supports the following source clocks for the CLK_DFLLIF_REF generic clock: SCIF_GCCTRL_SLOWCLOCK (aka RCSYS), SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC32K, SCIF_GCCTRL_OSC0, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_CLK1K.
gc_dfllif_ref_opt | The settings for the CLK_DFLLIF_REF generic clock [INPUT] | |
target_freq_hz | The target frequency (in Hz) [INPUT] | |
enable_ssg | Enable/disable the SSG feature [INPUT] |
0 | DFLL0 configured and started successfully. | |
<0 | Error. |
Definition at line 615 of file scif_uc3l.c.
References scif_gclk_opt_t::clock_source, scif_dfll_closedloop_conf_t::coarse, scif_dfll_closedloop_conf_t::coarsemaxstep, scif_gclk_opt_t::diven, scif_gclk_opt_t::divider, scif_gclk_opt_t::extosc_f, scif_dfll_closedloop_conf_t::finemaxstep, scif_dfll_closedloop_conf_t::fmul, scif_dfll0_closedloop_mainref_gc_enable, scif_dfll0_closedloop_start(), SCIF_DFLL_MAXFREQ_HZ, SCIF_DFLL_MINFREQ_HZ, SCIF_GCCTRL_CLK1K, SCIF_GCCTRL_OSC0, SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_RC32K, SCIF_GCCTRL_SLOWCLOCK, SCIF_RC120M_FREQ_HZ, SCIF_RC32K_FREQ_HZ, and SCIF_SLOWCLOCK_FREQ_HZ.
00618 { 00619 scif_dfll_closedloop_conf_t DfllConfig; 00620 int gc_source_clock_freq_hz; 00621 00622 // This function only supports the following source clocks for the CLK_DFLLIF_REF generic clock: 00623 // SCIF_GCCTRL_SLOWCLOCK (aka RCSYS), SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC32K, 00624 // SCIF_GCCTRL_OSC0, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_CLK1K. 00625 if(SCIF_GCCTRL_SLOWCLOCK == gc_dfllif_ref_opt->clock_source) 00626 gc_source_clock_freq_hz = SCIF_SLOWCLOCK_FREQ_HZ; 00627 else if((SCIF_GCCTRL_OSC32K == gc_dfllif_ref_opt->clock_source) || (SCIF_GCCTRL_RC32K == gc_dfllif_ref_opt->clock_source)) 00628 gc_source_clock_freq_hz = SCIF_RC32K_FREQ_HZ; 00629 else if(SCIF_GCCTRL_OSC0 == gc_dfllif_ref_opt->clock_source) 00630 gc_source_clock_freq_hz = gc_dfllif_ref_opt->extosc_f; 00631 else if(SCIF_GCCTRL_RC120M == gc_dfllif_ref_opt->clock_source) 00632 gc_source_clock_freq_hz = SCIF_RC120M_FREQ_HZ; 00633 else if(SCIF_GCCTRL_CLK1K == gc_dfllif_ref_opt->clock_source) 00634 gc_source_clock_freq_hz = 1000; 00635 else 00636 return -1; 00637 00638 // Configure and start the DFLL main reference generic clock (CLK_DFLLIF_REF). 00639 if(scif_dfll0_closedloop_mainref_gc_enable(gc_dfllif_ref_opt)) 00640 return(-1); 00641 00642 // Configure the DFLL. 00643 // The coarse value (= (dfll_f - SCIF_DFLL_MINFREQ_KHZ)*255/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ)) 00644 DfllConfig.coarse = ((unsigned long long)(target_freq_hz - SCIF_DFLL_MINFREQ_HZ)*255)/(SCIF_DFLL_MAXFREQ_HZ - SCIF_DFLL_MINFREQ_HZ); 00645 00646 // The fmul value (= (fDFLL*2^16)/fref, with fref being the frequency of the 00647 // DFLL main reference generic clock) 00648 if(0 == gc_dfllif_ref_opt->diven) 00649 DfllConfig.fmul = ((unsigned long long)target_freq_hz<<16)/gc_source_clock_freq_hz; 00650 else 00651 DfllConfig.fmul = ((((unsigned long long)target_freq_hz<<16)/gc_source_clock_freq_hz)<<1)*(1+gc_dfllif_ref_opt->divider); 00652 00653 // The fine and coarse maxstep values 00654 #if (defined(__GNUC__) \ 00655 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \ 00656 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \ 00657 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__))) 00658 // UC3L revC and higher 00659 DfllConfig.finemaxstep = 0x0000004; 00660 DfllConfig.coarsemaxstep = 0x0000004; 00661 #else 00662 // UC3L revB 00663 //+ Errata UC3L revB: 35.2.7 SCIF.12 DFLLIF indicates coarse lock too early 00664 //+ The DFLLIF might indicate coarse lock too early, the DFLL will lose 00665 //+ coarse lock and regain it later. 00666 //+ Fix/Workaround 00667 //+ Use max step size (DFLL0MAXSTEP.MAXSTEP) of 4 or higher. 00668 DfllConfig.maxstep = 0x0040004; 00669 #endif 00670 00671 // Dithering disabled. 00672 //+ Errata UC3L revB: 35.2.7 SCIF.13 DFLLIF dithering does not work 00673 //+ The DFLLIF dithering does not work. 00674 //+ Fix/Workaround 00675 //+ None. 00676 00677 // Configure and start the DFLL0 in closed loop mode. 00678 if(scif_dfll0_closedloop_start(&DfllConfig)) 00679 return -1; 00680 00681 // TODO: Future implementation note: add use of the generic clock CLK_DFLLIF_DITHER 00682 // as a reference for the SSG feature. 00683 if(TRUE == enable_ssg) 00684 { 00685 ; 00686 } 00687 return PASS; 00688 }
long int scif_dfll0_closedloop_start | ( | const scif_dfll_closedloop_conf_t * | pdfllconfig | ) |
Configure and start the DFLL0 in closed loop mode.
pdfllconfig | The DFLL parameters in closed loop mode [INPUT] |
0 | DFLL0 configured and started successfully. | |
<0 | Error. |
Definition at line 520 of file scif_uc3l.c.
References scif_dfll_closedloop_conf_t::coarse, scif_dfll_closedloop_conf_t::coarsemaxstep, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_dfll_closedloop_conf_t::finemaxstep, scif_dfll_closedloop_conf_t::fmul, SCIF_DFLL0_MODE_CLOSEDLOOP, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.
Referenced by local_start_dfll_clock(), and scif_dfll0_closedloop_configure_and_start().
00521 { 00522 u_avr32_scif_dfll0conf_t u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf}; 00523 #if (defined(__GNUC__) \ 00524 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \ 00525 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \ 00526 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__))) 00527 volatile unsigned long tempo; 00528 #endif 00529 00530 00531 #ifdef AVR32SFW_INPUT_CHECK 00532 if((pdfllconfig->coarse >> AVR32_SCIF_DFLL0CONF_COARSE_SIZE)) 00533 return -1; 00534 #if (defined(__GNUC__) \ 00535 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \ 00536 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \ 00537 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__))) 00538 // UC3L revC and higher 00539 if( (pdfllconfig->finemaxstep >> AVR32_SCIF_DFLL0STEP_FSTEP_SIZE) 00540 || (pdfllconfig->coarsemaxstep >> AVR32_SCIF_DFLL0STEP_CSTEP_SIZE) ) 00541 return -1; 00542 #else 00543 // UC3L revB 00544 if((pdfllconfig->maxstep >> AVR32_SCIF_DFLL0STEP_MAXSTEP_SIZE)) 00545 return -1; 00546 #endif 00547 #endif 00548 00549 // Enable the DFLL0: DFLL0CONF.EN=1 00550 u_avr32_scif_dfll0conf.DFLL0CONF.en = ENABLE; 00551 AVR32_ENTER_CRITICAL_REGION( ); 00552 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF); 00553 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf; 00554 AVR32_LEAVE_CRITICAL_REGION( ); 00555 00556 // Wait for PCLKSR.DFLL0RDY is high 00557 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK)) 00558 return -1; 00559 00560 // Set the maxstep values 00561 #if (defined(__GNUC__) \ 00562 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \ 00563 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \ 00564 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__))) 00565 // UC3L revC and higher 00566 tempo = ((pdfllconfig->coarsemaxstep << AVR32_SCIF_DFLL0STEP_CSTEP_OFFSET)&AVR32_SCIF_DFLL0STEP_CSTEP_MASK) 00567 | ((pdfllconfig->finemaxstep << AVR32_SCIF_DFLL0STEP_FSTEP_OFFSET)&AVR32_SCIF_DFLL0STEP_FSTEP_MASK); 00568 AVR32_ENTER_CRITICAL_REGION( ); 00569 SCIF_UNLOCK(AVR32_SCIF_DFLL0STEP); 00570 AVR32_SCIF.dfll0step = tempo; 00571 AVR32_LEAVE_CRITICAL_REGION( ); 00572 #else 00573 // UC3L revB 00574 AVR32_ENTER_CRITICAL_REGION( ); 00575 SCIF_UNLOCK(AVR32_SCIF_DFLL0STEP); 00576 AVR32_SCIF.dfll0step = (pdfllconfig->maxstep << AVR32_SCIF_DFLL0STEP_MAXSTEP_OFFSET)&AVR32_SCIF_DFLL0STEP_MAXSTEP_MASK; 00577 AVR32_LEAVE_CRITICAL_REGION( ); 00578 #endif 00579 00580 // Wait for PCLKSR.DFLL0RDY is high 00581 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK)) 00582 return -1; 00583 00584 // Set the fmul 00585 AVR32_ENTER_CRITICAL_REGION( ); 00586 SCIF_UNLOCK(AVR32_SCIF_DFLL0FMUL); 00587 AVR32_SCIF.dfll0fmul = (pdfllconfig->fmul << AVR32_SCIF_DFLL0FMUL_FMUL_OFFSET)&AVR32_SCIF_DFLL0FMUL_FMUL_MASK; 00588 AVR32_LEAVE_CRITICAL_REGION( ); 00589 00590 // Wait for PCLKSR.DFLL0RDY is high 00591 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK)) 00592 return -1; 00593 00594 // Set the DFLL0 to operate in closed-loop mode: DFLL0CONF.MODE=1 00595 u_avr32_scif_dfll0conf.DFLL0CONF.mode = SCIF_DFLL0_MODE_CLOSEDLOOP; 00596 u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse; 00597 AVR32_ENTER_CRITICAL_REGION( ); 00598 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF); 00599 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf; 00600 AVR32_LEAVE_CRITICAL_REGION( ); 00601 00602 // Wait for PCLKSR.DFLL0RDY is high 00603 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK)) 00604 return -1; 00605 00606 // Wait until the DFLL is locked on Fine value, and is ready to be selected as 00607 // clock source with a highly accurate output clock. 00608 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0LOCKF_MASK)) 00609 return -1; 00610 00611 return PASS; 00612 }
long int scif_dfll0_openloop_start | ( | const scif_dfll_openloop_conf_t * | pdfllconfig | ) |
Configure and start the DFLL0 in open loop mode.
pdfllconfig | The DFLL parameters in open loop mode [INPUT] |
0 | DFLL0 configured and started successfully. | |
<0 | Error. |
Definition at line 342 of file scif_uc3l.c.
References scif_dfll_openloop_conf_t::coarse, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_dfll_openloop_conf_t::fine, SCIF_DFLL0_MODE_OPENLOOP, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.
Referenced by scif_dfll0_openloop_start_auto().
00343 { 00344 u_avr32_scif_dfll0conf_t u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf}; 00345 00346 00347 #ifdef AVR32SFW_INPUT_CHECK 00348 if((pdfllconfig->fine >> AVR32_SCIF_DFLL0CONF_FINE_SIZE)) 00349 return -1; 00350 if((pdfllconfig->coarse >> AVR32_SCIF_DFLL0CONF_COARSE_SIZE)) 00351 return -1; 00352 #endif 00353 00354 // Enable the DFLL0: DFLL0CONF.EN=1 00355 u_avr32_scif_dfll0conf.DFLL0CONF.en = ENABLE; 00356 AVR32_ENTER_CRITICAL_REGION( ); 00357 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF); 00358 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf; 00359 AVR32_LEAVE_CRITICAL_REGION( ); 00360 00361 // Wait for PCLKSR.DFLL0RDY is high 00362 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK)) 00363 return -1; 00364 00365 // Set the DFLL0 to operate in open mode: DFLL0CONF.MODE=0 00366 u_avr32_scif_dfll0conf.DFLL0CONF.mode = SCIF_DFLL0_MODE_OPENLOOP; 00367 AVR32_ENTER_CRITICAL_REGION( ); 00368 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF); 00369 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf; 00370 AVR32_LEAVE_CRITICAL_REGION( ); 00371 00372 // Wait for PCLKSR.DFLL0RDY is high 00373 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK)) 00374 return -1; 00375 00376 // Write DFLL0CONF.COARSE & DFLL0CONF.FINE 00377 u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse; 00378 u_avr32_scif_dfll0conf.DFLL0CONF.fine = pdfllconfig->fine; 00379 AVR32_ENTER_CRITICAL_REGION( ); 00380 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF); 00381 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf; 00382 AVR32_LEAVE_CRITICAL_REGION( ); 00383 00384 // Wait for PCLKSR.DFLL0RDY is high 00385 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK)) 00386 return -1; 00387 00388 return PASS; 00389 }
long int scif_dfll0_openloop_start_auto | ( | unsigned long | TargetFreqkHz | ) |
Automatic configuration and start of the DFLL0 in open loop mode.
TargetFreqkHz | The DFLL target frequency (in kHz) [INPUT] |
0 | DFLL0 configured and started successfully. | |
<0 | Error. |
Definition at line 395 of file scif_uc3l.c.
References scif_dfll_openloop_conf_t::coarse, scif_dfll_openloop_conf_t::fine, scif_dfll0_openloop_start(), SCIF_DFLL_COARSE_MAX, SCIF_DFLL_FINE_HALF, SCIF_DFLL_FINE_MAX, SCIF_DFLL_MAXFREQ_KHZ, and SCIF_DFLL_MINFREQ_KHZ.
00396 { 00397 scif_dfll_openloop_conf_t Dfll0Conf; 00398 unsigned long Coarse; 00399 unsigned long Fine; 00400 unsigned long CoarseFreq; 00401 unsigned long DeltaFreq; 00402 00403 00404 #ifdef AVR32SFW_INPUT_CHECK 00405 if((TargetFreqkHz < SCIF_DFLL_MINFREQ_KHZ) || (TargetFreqkHz > SCIF_DFLL_MAXFREQ_KHZ)) 00406 return -1; 00407 #endif 00408 00409 //** 00410 //** Dynamically compute the COARSE and FINE values. 00411 //** 00412 // Fdfll = (Fmin+(Fmax-Fmin)*(COARSE/0xFF))*(1+X*(FINE-0x100)/0x1FF)=CoarseFreq*(1+X*(FINE-0x100)/0x1FF) 00413 00414 // Compute the COARSE value. 00415 Coarse = ((TargetFreqkHz - SCIF_DFLL_MINFREQ_KHZ)*SCIF_DFLL_COARSE_MAX)/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ); 00416 // Compute the COARSE DFLL frequency. 00417 CoarseFreq = SCIF_DFLL_MINFREQ_KHZ + (((SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ)/SCIF_DFLL_COARSE_MAX)*Coarse); 00418 // Compute the coarse error. 00419 DeltaFreq = TargetFreqkHz - CoarseFreq; 00420 // Compute the FINE value. 00421 // Fine = ((DeltaFreq*SCIF_DFLL_FINE_MAX)*10/CoarseFreq) + SCIF_DFLL_FINE_HALF; 00422 // Theorical equation don't work on silicon: the best was to use X=5/2 to 00423 // find FINE, then do FINE/4. 00424 Fine = ((DeltaFreq*SCIF_DFLL_FINE_MAX)*2/CoarseFreq*5) + SCIF_DFLL_FINE_HALF; 00425 Fine >>=2; 00426 00427 Dfll0Conf.coarse = Coarse; 00428 Dfll0Conf.fine = Fine; 00429 return(scif_dfll0_openloop_start(&Dfll0Conf)); 00430 }
long int scif_dfll0_openloop_stop | ( | void | ) |
Stop the DFLL0 in open loop mode.
0 | DFLL0 successfully stopped. | |
<0 | Error. |
Definition at line 464 of file scif_uc3l.c.
References u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.
00465 { 00466 u_avr32_scif_dfll0conf_t u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf}; 00467 00468 00469 // Before disabling the DFLL, the output freq of the DFLL should be set to a 00470 // minimum: set COARSE to 0x00. 00471 00472 // Wait for PCLKSR.DFLL0RDY is high 00473 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK)) 00474 return -1; 00475 00476 // Write DFLL0CONF.COARSE 00477 u_avr32_scif_dfll0conf.DFLL0CONF.coarse = 0; 00478 AVR32_ENTER_CRITICAL_REGION( ); 00479 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF); 00480 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf; 00481 AVR32_LEAVE_CRITICAL_REGION( ); 00482 00483 // Wait for PCLKSR.DFLL0RDY is high 00484 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK)) 00485 return -1; 00486 00487 // Disable the DFLL 00488 u_avr32_scif_dfll0conf.DFLL0CONF.en = 0; 00489 AVR32_ENTER_CRITICAL_REGION( ); 00490 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF); 00491 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf; 00492 AVR32_LEAVE_CRITICAL_REGION( ); 00493 00494 // Wait for PCLKSR.DFLL0RDY is high 00495 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK)) 00496 return -1; 00497 00498 return PASS; 00499 }
long int scif_dfll0_openloop_updatefreq | ( | const scif_dfll_openloop_conf_t * | pdfllconfig | ) |
Update the frequency of the DFLL0 in open loop mode.
pdfllconfig | The DFLL parameters in open loop mode [INPUT] |
0 | DFLL0 frequency updated successfully. | |
<0 | Error. |
Definition at line 432 of file scif_uc3l.c.
References scif_dfll_openloop_conf_t::coarse, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_dfll_openloop_conf_t::fine, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.
00433 { 00434 u_avr32_scif_dfll0conf_t u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf}; 00435 00436 00437 #ifdef AVR32SFW_INPUT_CHECK 00438 if((pdfllconfig->fine >> AVR32_SCIF_DFLL0CONF_FINE_SIZE)) 00439 return -1; 00440 #endif 00441 00442 // It is assumed that the DFLL is enabled and operates in open-loop mode. 00443 00444 // Wait for PCLKSR.DFLL0RDY is high 00445 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK)) 00446 return -1; 00447 00448 // Write DFLL0CONF.COARSE & DFLL0CONF.FINE 00449 u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse; 00450 u_avr32_scif_dfll0conf.DFLL0CONF.fine = pdfllconfig->fine; 00451 AVR32_ENTER_CRITICAL_REGION( ); 00452 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF); 00453 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf; 00454 AVR32_LEAVE_CRITICAL_REGION( ); 00455 00456 // Wait for PCLKSR.DFLL0RDY is high 00457 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK)) 00458 return -1; 00459 00460 return PASS; 00461 }
long int scif_dfll0_ssg_enable | ( | scif_dfll_ssg_conf_t * | pssg_conf | ) |
Configure and enable the SSG.
pssg_conf | The settings for the SCIF.DFLL0SSG register [INPUT] |
0 | SSG Generic clock configured and started successfully. | |
<0 | Error. |
Definition at line 502 of file scif_uc3l.c.
References scif_dfll_ssg_conf_t::amplitude, u_avr32_scif_dfll0ssg_t::dfll0ssg, u_avr32_scif_dfll0ssg_t::DFLL0SSG, SCIF_UNLOCK, scif_dfll_ssg_conf_t::step_size, and scif_dfll_ssg_conf_t::use_random.
00503 { 00504 u_avr32_scif_dfll0ssg_t u_avr32_scif_dfll0ssg = {AVR32_SCIF.dfll0ssg}; 00505 00506 00507 u_avr32_scif_dfll0ssg.DFLL0SSG.en = ENABLE; 00508 u_avr32_scif_dfll0ssg.DFLL0SSG.prbs = pssg_conf->use_random; 00509 u_avr32_scif_dfll0ssg.DFLL0SSG.amplitude = pssg_conf->amplitude; 00510 u_avr32_scif_dfll0ssg.DFLL0SSG.stepsize = pssg_conf->step_size; 00511 AVR32_ENTER_CRITICAL_REGION( ); 00512 SCIF_UNLOCK(AVR32_SCIF_DFLL0SSG); 00513 AVR32_SCIF.dfll0ssg = u_avr32_scif_dfll0ssg.dfll0ssg; 00514 AVR32_LEAVE_CRITICAL_REGION( ); 00515 00516 return PASS; 00517 }
void scif_disable_rc32out | ( | void | ) |
Unforce the RC32 signal from being output on the dedicated pin (PB04 on revB, PA20 on revC and later).
Definition at line 751 of file scif_uc3l.c.
Referenced by scif_start_osc32().
00752 { 00753 unsigned long temp; 00754 AVR32_ENTER_CRITICAL_REGION( ); 00755 temp = AVR32_PM.ppcr & (~AVR32_PM_PPCR_FRC32_MASK); 00756 // Unforce the RC32 signal from being output on the dedicated pin (PB04 on revB, PA20 on revC and later). 00757 AVR32_PM.unlock = 0xAA000000 | AVR32_PM_PPCR; 00758 AVR32_PM.ppcr = temp; 00759 AVR32_LEAVE_CRITICAL_REGION( ); 00760 }
long int scif_enable_osc | ( | scif_osc_t | osc, | |
unsigned int | startup, | |||
bool | wait_for_ready | |||
) |
Enable an oscillator with a given startup time.
osc | The oscillator to configure [INPUT] | |
startup | Oscillator startup time (one of AVR32_SCIF_OSCCTRLx_STARTUP_x_RCOSC) [INPUT] | |
wait_for_ready | Wait for the oscillator to be stable before return [INPUT] |
0 | Oscillator successfully started | |
<0 | Error starting the oscillator. |
Definition at line 204 of file scif_uc3l.c.
References u_avr32_scif_oscctrl_t::OSCCTRL, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.
00205 { 00206 //# Implementation note: this code doesn't consider the osc input parameter 00207 //# because UC3L devices only implement OSC0. 00208 u_avr32_scif_oscctrl0_t u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0}; 00209 00210 00211 // Configure the oscillator startup and enable the osc. 00212 u_avr32_scif_oscctrl0.OSCCTRL0.startup = startup; 00213 u_avr32_scif_oscctrl0.OSCCTRL0.oscen = ENABLE; 00214 AVR32_ENTER_CRITICAL_REGION( ); 00215 // Unlock the write-protected OSCCTRL0 register 00216 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0); 00217 // Write 00218 AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0; 00219 AVR32_LEAVE_CRITICAL_REGION( ); 00220 00221 if(true == wait_for_ready) 00222 { 00223 // Wait until OSC0 is stable and ready to be used. 00224 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK)) 00225 return -1; 00226 } 00227 00228 return PASS; 00229 }
long int scif_gc_enable | ( | unsigned int | gclk | ) |
Enable a generic clock.
gclk | generic clock number (0 for gc0...) |
0 | Success. | |
<0 | An error occured. |
Definition at line 869 of file scif_uc3l.c.
00870 { 00871 #ifdef AVR32SFW_INPUT_CHECK 00872 // Check that the generic clock number is correct 00873 if( gclk > AVR32_SCIF_GCLK_NUM ) 00874 { 00875 return -1; 00876 } 00877 #endif // AVR32SFW_INPUT_CHECK 00878 00879 // If the generic clock is already enabled, do nothing. 00880 if(!(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)) 00881 AVR32_SCIF.gcctrl[gclk] |= (AVR32_SCIF_GCCTRL_CEN_MASK); 00882 00883 return PASS; 00884 }
long int scif_gc_setup | ( | unsigned int | gclk, | |
scif_gcctrl_oscsel_t | clk_src, | |||
unsigned int | diven, | |||
unsigned int | divfactor | |||
) |
Setup a generic clock.
gclk | generic clock number (0 for gc0...) | |
clk_src | The input clock source to use for the generic clock | |
diven | Generic clock divisor enable | |
divfactor | Generic clock divisor |
0 | Success. | |
<0 | An error occured. |
Definition at line 821 of file scif_uc3l.c.
References SCIF_GCCTRL_OSCSEL_INVALID, and scif_stop_gclk().
00822 { 00823 int restart_gc = false; 00824 00825 00826 // Change the division factor to conform to the equation: fgclk = fsrc/divfactor = fsrc/(2*(div+1)) 00827 divfactor = (divfactor>>1) -1; 00828 00829 #ifdef AVR32SFW_INPUT_CHECK 00830 // Check that the generic clock number is correct 00831 if( gclk > AVR32_SCIF_GCLK_NUM ) 00832 { 00833 return -1; 00834 } 00835 // Check that the clock source for the generic clock is correct. 00836 if(( clk_src >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( clk_src < 0 )) 00837 { 00838 return -1; 00839 } 00840 // Check that the required division factor is correct. 00841 if(diven) 00842 { 00843 if(divfactor >= (1<<AVR32_SCIF_GCCTRL_DIV_SIZE)) 00844 return -1; 00845 } 00846 #endif // AVR32SFW_INPUT_CHECK 00847 00848 // If the generic clock is already enabled, disable it before changing its setup. 00849 if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK) 00850 { 00851 restart_gc = true; 00852 if(scif_stop_gclk(gclk) < 0) 00853 return -1; // Could not stop the generic clock. 00854 } 00855 00856 // Setup the generic clock. 00857 AVR32_SCIF.gcctrl[gclk] = ((divfactor << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK) 00858 |((diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK) 00859 |((clk_src << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK); 00860 00861 // Restart the gc if it previously was enabled. 00862 if(true == restart_gc) 00863 AVR32_SCIF.gcctrl[gclk] |= (AVR32_SCIF_GCCTRL_CEN_MASK); 00864 00865 return PASS; 00866 }
bool scif_is_osc_ready | ( | scif_osc_t | osc | ) |
Is an oscillator stable and ready to be used as clock source?
osc | The oscillator [INPUT] |
true | oscillator stable and ready | |
false | oscillator not enabled or not ready. |
Definition at line 153 of file scif_uc3l.c.
References SCIF_OSC0.
00154 { 00155 //# Implementation note: this code doesn't consider the osc input parameter 00156 //# because UC3L devices only implement OSC0. 00157 return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC0RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC0RDY_OFFSET); 00158 }
long int scif_pclksr_statushigh_wait | ( | unsigned long | statusMask | ) |
Backup Registers Functions.
Wait for a status high in the Power and Clocks status register.
Misc
Wait for a status high in the Power and Clocks status register.
statusMask | Mask field of the status to poll [INPUT] |
0 | Status is high. | |
<0 | SCIF_POLL_TIMEOUT Timeout expired before the status was high. |
Definition at line 903 of file scif_uc3l.c.
References SCIF_POLL_TIMEOUT.
00904 { 00905 unsigned int timeout = SCIF_POLL_TIMEOUT; 00906 00907 while(!(AVR32_SCIF.pclksr & statusMask)) 00908 { 00909 if(--timeout == 0) 00910 return -1; 00911 } 00912 return PASS; 00913 }
long int scif_start_gclk | ( | unsigned int | gclk, | |
const scif_gclk_opt_t * | opt | |||
) |
Generic Clock Functions.
Setup and start a generic clock.
Definition at line 766 of file scif_uc3l.c.
References scif_gclk_opt_t::clock_source, scif_gclk_opt_t::diven, scif_gclk_opt_t::divider, and SCIF_GCCTRL_OSCSEL_INVALID.
00767 { 00768 #ifdef AVR32SFW_INPUT_CHECK 00769 // Check that the generic clock number is correct 00770 if( gclk > AVR32_SCIF_GCLK_NUM ) 00771 { 00772 return -1; 00773 } 00774 // Check that the clock source for the generic clock is correct. 00775 if(( opt->clock_source >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( opt->clock_source < 0 )) 00776 { 00777 return -1; 00778 } 00779 #endif // AVR32SFW_INPUT_CHECK 00780 00781 // If the generic clock is already enabled, return an error. 00782 if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK) 00783 return -1; 00784 00785 // Configure & start the generic clock. 00786 AVR32_SCIF.gcctrl[gclk] = ((opt->divider << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK) 00787 |((opt->diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK) 00788 |((opt->clock_source << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK) 00789 |(AVR32_SCIF_GCCTRL_CEN_MASK); 00790 00791 return PASS; 00792 }
long int scif_start_osc | ( | scif_osc_t | osc, | |
const scif_osc_opt_t * | opt, | |||
bool | wait_for_ready | |||
) |
Interrupt Functions.
Configure and start an OSC0/OSC1 oscillator.
Power and Clocks Status Functions OSC0/OSC1 Functions
Definition at line 98 of file scif_uc3l.c.
References scif_osc_opt_t::freq_hz, scif_osc_opt_t::gain, scif_osc_opt_t::mode, u_avr32_scif_oscctrl_t::OSCCTRL, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, SCIF_EXT_CRYSTAL_MAX_FREQ_HZ, SCIF_EXT_CRYSTAL_MIN_FREQ_HZ, SCIF_OSC0, SCIF_OSC_MODE_2PIN_CRYSTAL, SCIF_OSC_MODE_EXT_CLK, scif_pclksr_statushigh_wait(), SCIF_UNLOCK, and scif_osc_opt_t::startup.
00099 { 00100 //# Implementation note: this code doesn't consider the osc input parameter 00101 //# because UC3L devices only implement OSC0. 00102 u_avr32_scif_oscctrl0_t u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0}; 00103 00104 00105 #ifdef AVR32SFW_INPUT_CHECK 00106 // Check that the input frequency is in the supported frequency range. 00107 if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ) 00108 || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ)) 00109 { 00110 return -1; 00111 } 00112 // Check : for OSC0/OSC1, only 2 modes are supported 00113 if( (opt->mode != SCIF_OSC_MODE_EXT_CLK) 00114 && (opt->mode != SCIF_OSC_MODE_2PIN_CRYSTAL)) 00115 { 00116 return -1; 00117 } 00118 // Check that the startup value is in the supported range. 00119 if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC) 00120 { 00121 return -1; 00122 } 00123 // Check that the gain value is in the supported range. 00124 if(opt->gain > AVR32_SCIF_OSCCTRL0_GAIN_G3) 00125 { 00126 return -1; 00127 } 00128 #endif // AVR32SFW_INPUT_CHECK 00129 00130 // Configure & start OSC0. 00131 u_avr32_scif_oscctrl0.OSCCTRL0.mode = opt->mode; 00132 u_avr32_scif_oscctrl0.OSCCTRL0.gain = opt->gain; 00133 u_avr32_scif_oscctrl0.OSCCTRL0.startup = opt->startup; 00134 u_avr32_scif_oscctrl0.OSCCTRL0.oscen = ENABLE; 00135 AVR32_ENTER_CRITICAL_REGION( ); 00136 // Unlock the write-protected OSCCTRL0 register 00137 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0); 00138 // Write 00139 AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0; 00140 AVR32_LEAVE_CRITICAL_REGION( ); 00141 00142 if(true == wait_for_ready) 00143 { 00144 // Wait until OSC0 is stable and ready to be used. 00145 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK)) 00146 return -1; 00147 } 00148 00149 return PASS; 00150 }
long int scif_start_osc32 | ( | const scif_osc32_opt_t * | opt, | |
bool | wait_for_ready | |||
) |
OSC32 Functions.
Configure and start the OSC32 oscillator.
Definition at line 236 of file scif_uc3l.c.
References scif_osc32_opt_t::en1k, scif_osc32_opt_t::en32k, scif_osc32_opt_t::freq_hz, scif_osc32_opt_t::mode, u_avr32_scif_oscctrl32_t::OSCCTRL32, u_avr32_scif_oscctrl32_t::oscctrl32, scif_osc32_opt_t::pinsel, scif_disable_rc32out(), SCIF_EXT_CRYSTAL_MAX_FREQ_HZ, SCIF_EXT_CRYSTAL_MIN_FREQ_HZ, SCIF_OSC_MODE_2PIN_CRYSTAL, SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR, SCIF_OSC_MODE_EXT_CLK, SCIF_OSC_MODE_NOT_SUPPORTED_1, SCIF_OSC_MODE_NOT_SUPPORTED_2, scif_pclksr_statushigh_wait(), SCIF_UNLOCK, and scif_osc32_opt_t::startup.
00237 { 00238 u_avr32_scif_oscctrl32_t u_avr32_scif_oscctrl32 = {AVR32_SCIF.oscctrl32}; 00239 00240 00241 #ifdef AVR32SFW_INPUT_CHECK 00242 // Check that the input frequency is in the supported frequency range. 00243 if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ) 00244 || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ)) 00245 { 00246 return -1; 00247 } 00248 // Check : for OSC32, 3 modes are supported 00249 if( (opt->mode != SCIF_OSC_MODE_EXT_CLK) 00250 && (opt->mode != SCIF_OSC_MODE_2PIN_CRYSTAL) 00251 && (opt->mode != SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR) 00252 ) 00253 { 00254 return -1; 00255 } 00256 // Check that the startup value is in the supported range. 00257 if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL32_STARTUP_524288_RCOSC) 00258 { 00259 return -1; 00260 } 00261 #endif // AVR32SFW_INPUT_CHECK 00262 00263 #if (defined(__GNUC__) \ 00264 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \ 00265 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \ 00266 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__))) 00267 // Note: starting from UC3L revC on, RC32K is automatically output on PA20 upon 00268 // reset, which is the pin for XOUT32_2 => we must disable this output before 00269 // setting-up the OSC32K (in case the OSC32 is connected to XIN32_2/XOUT32_2). 00270 scif_disable_rc32out(); 00271 #endif 00272 00273 // Configure & start OSC32. 00274 u_avr32_scif_oscctrl32.OSCCTRL32.mode = opt->mode; 00275 u_avr32_scif_oscctrl32.OSCCTRL32.pinsel = opt->pinsel; 00276 u_avr32_scif_oscctrl32.OSCCTRL32.en32k = opt->en32k; 00277 u_avr32_scif_oscctrl32.OSCCTRL32.en1k = opt->en1k; 00278 u_avr32_scif_oscctrl32.OSCCTRL32.startup = opt->startup; 00279 u_avr32_scif_oscctrl32.OSCCTRL32.osc32en = ENABLE; 00280 #if (defined(__GNUC__) \ 00281 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \ 00282 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \ 00283 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__))) 00284 // Note: starting from UC3L revC on, the OSCCTRL32 register is protected by a lock. 00285 AVR32_ENTER_CRITICAL_REGION( ); 00286 // Unlock the write-protected OSCCTRL32 register 00287 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32); 00288 #endif 00289 // write 00290 AVR32_SCIF.oscctrl32 = u_avr32_scif_oscctrl32.oscctrl32; 00291 #if (defined(__GNUC__) \ 00292 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \ 00293 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \ 00294 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__))) 00295 // Note: starting from UC3L revC on, the OSCCTRL32 register is protected by a lock. 00296 AVR32_LEAVE_CRITICAL_REGION( ); 00297 #endif 00298 00299 if(true == wait_for_ready) 00300 { 00301 // Wait until OSC32 is stable and ready to be used. 00302 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC32RDY_MASK)) 00303 return -1; 00304 } 00305 00306 return PASS; 00307 }
void scif_start_rc120M | ( | void | ) |
Calibration Functions.
Start the 120MHz internal RCosc (RC120M) clock.
Critical Path Oscillator Functions 120MHz RCosc Functions
Definition at line 704 of file scif_uc3l.c.
References SCIF_UNLOCK.
00705 { 00706 AVR32_ENTER_CRITICAL_REGION( ); 00707 // Unlock the write-protected RC120MCR register 00708 SCIF_UNLOCK(AVR32_SCIF_RC120MCR); 00709 AVR32_SCIF.rc120mcr = AVR32_SCIF_RC120MCR_EN_MASK; 00710 AVR32_LEAVE_CRITICAL_REGION( ); 00711 }
void scif_start_rc32k | ( | void | ) |
32kHz internal RCosc (RC32K) Functions
Start the 32kHz internal RCosc (RC32K) clock.
Definition at line 730 of file scif_uc3l.c.
References SCIF_UNLOCK.
00731 { 00732 AVR32_ENTER_CRITICAL_REGION( ); 00733 // Unlock the write-protected RC32KCR register 00734 SCIF_UNLOCK(AVR32_SCIF_RC32KCR); 00735 AVR32_SCIF.rc32kcr = AVR32_SCIF_RC32KCR_EN_MASK; 00736 AVR32_LEAVE_CRITICAL_REGION( ); 00737 }
long int scif_stop_gclk | ( | unsigned int | gclk | ) |
Stop a generic clock.
gclk | The generic clock number to stop. |
0 | Success. | |
<0 | Unable to stop generic clock. |
Definition at line 795 of file scif_uc3l.c.
References SCIF_POLL_TIMEOUT.
00796 { 00797 unsigned int timeout = SCIF_POLL_TIMEOUT; 00798 00799 #ifdef AVR32SFW_INPUT_CHECK 00800 // Check that the generic clock number is correct 00801 if( gclk > AVR32_SCIF_GCLK_NUM ) 00802 { 00803 return -1; 00804 } 00805 #endif // AVR32SFW_INPUT_CHECK 00806 00807 // Stop the generic clock. 00808 AVR32_SCIF.gcctrl[gclk] &= ~AVR32_SCIF_GCCTRL_CEN_MASK; 00809 00810 // Wait until the generic clock is actually stopped. 00811 while(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK) 00812 { 00813 if(--timeout == 0) 00814 return -1; 00815 } 00816 00817 return PASS; 00818 }
long int scif_stop_osc | ( | scif_osc_t | osc | ) |
Stop an oscillator.
osc | The oscillator to stop |
0 | Oscillator successfully stopped. | |
<0 | An error occured when stopping the oscillator. |
Definition at line 161 of file scif_uc3l.c.
References SCIF_UNLOCK.
00162 { 00163 //# Implementation note: this code doesn't consider the osc input parameter 00164 //# because UC3L devices only implement OSC0. 00165 unsigned long temp = AVR32_SCIF.oscctrl0; 00166 temp &= ~AVR32_SCIF_OSCCTRL0_OSCEN_MASK; 00167 00168 AVR32_ENTER_CRITICAL_REGION( ); 00169 // Unlock the write-protected OSCCTRL0 register 00170 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0); 00171 // Stop OSC0. 00172 AVR32_SCIF.oscctrl0 = temp; 00173 AVR32_LEAVE_CRITICAL_REGION( ); 00174 00175 return PASS; 00176 }
long scif_stop_osc32 | ( | ) |
Stop the OSC32 oscillator.
0 | Oscillator successfully stopped. | |
<0 | An error occured when stopping the oscillator. |
Definition at line 310 of file scif_uc3l.c.
References AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE, and SCIF_UNLOCK.
00311 { 00312 unsigned long temp = AVR32_SCIF.oscctrl32; 00313 temp &= ~AVR32_SCIF_OSCCTRL32_OSC32EN_MASK; 00314 00315 #if (defined(__GNUC__) \ 00316 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \ 00317 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \ 00318 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__))) 00319 // Note: starting from UC3L revC on, the OSCCTRL32 register is protected by a lock. 00320 // Unlock the write-protected OSCCTRL32 register 00321 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32); 00322 #endif 00323 // Stop OSC32. 00324 AVR32_SCIF.oscctrl32 = temp; 00325 00326 return PASS; 00327 }
void scif_stop_rc120M | ( | void | ) |
Stop the 120MHz internal RCosc (RC120M) clock.
Definition at line 713 of file scif_uc3l.c.
References SCIF_UNLOCK.
00714 { 00715 unsigned long temp = AVR32_SCIF.rc120mcr; 00716 00717 temp &= ~AVR32_SCIF_RC120MCR_EN_MASK; 00718 AVR32_ENTER_CRITICAL_REGION( ); 00719 // Unlock the write-protected RC120MCR register 00720 SCIF_UNLOCK(AVR32_SCIF_RC120MCR); 00721 AVR32_SCIF.rc120mcr = temp; 00722 AVR32_LEAVE_CRITICAL_REGION( ); 00723 }
void scif_stop_rc32k | ( | void | ) |
Stop the 32kHz internal RCosc (RC32K) clock.
Definition at line 739 of file scif_uc3l.c.
References SCIF_UNLOCK.
00740 { 00741 unsigned long temp = AVR32_SCIF.rc32kcr; 00742 00743 temp &= ~AVR32_SCIF_RC32KCR_EN_MASK; 00744 AVR32_ENTER_CRITICAL_REGION( ); 00745 // Unlock the write-protected RC32KCR register 00746 SCIF_UNLOCK(AVR32_SCIF_RC32KCR); 00747 AVR32_SCIF.rc32kcr = temp; 00748 AVR32_LEAVE_CRITICAL_REGION( ); 00749 }