Definition in file flash_example.c.
#include "compiler.h"
#include "print_funcs.h"
#include "board.h"
#include "power_clocks_lib.h"
#include "flashcdw.h"
Go to the source code of this file.
Data Structures | |
struct | nvram_data_t |
Structure type containing variables to store in NVRAM using a specific memory map. More... | |
Defines | |
#define | EXAMPLE_TARGET_DFLL_FREQ_HZ 96000000 |
#define | EXAMPLE_TARGET_MCUCLK_FREQ_HZ 12000000 |
#define | EXAMPLE_TARGET_PBACLK_FREQ_HZ 12000000 |
Functions | |
static void | flash_rw_example (const char *caption, nvram_data_t *nvram_data) |
This is an example demonstrating flash read / write data accesses using the FLASHCDW driver. | |
int | main (void) |
Main function running the example on both the flash array and the User page. | |
static void | print_nvram_variables (nvram_data_t *nvram_data) |
Prints the variables stored in NVRAM. | |
Variables | |
static nvram_data_t | flash_nvram_data |
NVRAM data structure located in the flash array. | |
static nvram_data_t | user_nvram_data |
NVRAM data structure located in the User page. | |
Parameters to pcl_configure_clocks(). | |
static scif_gclk_opt_t | gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, OFF} |
static pcl_freq_param_t | pcl_dfll_freq_param |
#define EXAMPLE_TARGET_DFLL_FREQ_HZ 96000000 |
Definition at line 104 of file flash_example.c.
#define EXAMPLE_TARGET_MCUCLK_FREQ_HZ 12000000 |
Definition at line 105 of file flash_example.c.
#define EXAMPLE_TARGET_PBACLK_FREQ_HZ 12000000 |
static void flash_rw_example | ( | const char * | caption, | |
nvram_data_t * | nvram_data | |||
) | [static] |
This is an example demonstrating flash read / write data accesses using the FLASHCDW driver.
caption | Caption to print before running the example. | |
nvram_data | Pointer to the NVRAM data structure to use in the example. |
Definition at line 187 of file flash_example.c.
References flashcdw_memcpy(), flashcdw_memset, and print_nvram_variables().
Referenced by main().
00188 { 00189 static const U8 write_data[8] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xAB, 0xCD, 0xEF}; 00190 00191 print_dbg(caption); 00192 00193 print_dbg("Initial values of NVRAM variables:\n"); 00194 print_nvram_variables(nvram_data); 00195 00196 print_dbg("\nClearing NVRAM variables..."); 00197 flashcdw_memset((void *)nvram_data, 0x00, 8, sizeof(*nvram_data), TRUE); 00198 print_dbg("\nNVRAM variables cleared:\n"); 00199 print_nvram_variables(nvram_data); 00200 00201 print_dbg("\nWriting new values to NVRAM variables..."); 00202 flashcdw_memcpy((void *)&nvram_data->var8, &write_data, sizeof(nvram_data->var8), TRUE); 00203 flashcdw_memcpy((void *)&nvram_data->var16, &write_data, sizeof(nvram_data->var16), TRUE); 00204 flashcdw_memcpy((void *)&nvram_data->var8_3, &write_data, sizeof(nvram_data->var8_3), TRUE); 00205 flashcdw_memcpy((void *)&nvram_data->var32, &write_data, sizeof(nvram_data->var32), TRUE); 00206 print_dbg("\nNVRAM variables written:\n"); 00207 print_nvram_variables(nvram_data); 00208 }
int main | ( | void | ) |
Main function running the example on both the flash array and the User page.
Definition at line 214 of file flash_example.c.
References EXAMPLE_TARGET_PBACLK_FREQ_HZ, flash_nvram_data, flash_rw_example(), pcl_dfll_freq_param, and user_nvram_data.
00215 { 00216 #if BOARD == UC3L_EK 00217 // Note: on the AT32UC3L-EK board, there is no crystal/external clock connected 00218 // to the OSC0 pinout XIN0/XOUT0. We shall then program the DFLL and switch the 00219 // main clock source to the DFLL. 00220 pcl_configure_clocks(&pcl_dfll_freq_param); 00221 // Note: since it is dynamically computing the appropriate field values of the 00222 // configuration registers from the parameters structure, this function is not 00223 // optimal in terms of code size. For a code size optimal solution, it is better 00224 // to create a new function from pcl_configure_clocks_dfll0() and modify it 00225 // to use preprocessor computation from pre-defined target frequencies. 00226 #else 00227 // Configure Osc0 in crystal mode (i.e. use of an external crystal source, with 00228 // frequency FOSC0) with an appropriate startup time then switch the main clock 00229 // source to Osc0. 00230 pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP); 00231 #endif 00232 00233 // Initialize the debug USART module. 00234 init_dbg_rs232(EXAMPLE_TARGET_PBACLK_FREQ_HZ); 00235 00236 // Apply the example to the flash array. 00237 flash_rw_example("\x0C=== Using a piece of the flash array as NVRAM ==================================\n", 00238 &flash_nvram_data); 00239 00240 // Apply the example to the User page. 00241 flash_rw_example("\n\n=== Using a piece of the User page as NVRAM ====================================\n", 00242 &user_nvram_data); 00243 00244 //*** Sleep mode 00245 // This program won't be doing anything else from now on, so it might as well 00246 // sleep. 00247 // Modules communicating with external circuits should normally be disabled 00248 // before entering a sleep mode that will stop the module operation. 00249 // For this application, we must disable the USART module that the DEBUG 00250 // software module is using. 00251 pcl_disable_module(DBG_USART_CLOCK_MASK); 00252 00253 // Since we're going into a sleep mode deeper than IDLE, all HSB masters must 00254 // be stopped before entering the sleep mode. 00255 pcl_disable_module(AVR32_PDCA_CLK_HSB); 00256 pcl_disable_module(AVR32_PDCA_CLK_PBA); 00257 00258 // If there is a chance that any PB write operations are incomplete, the CPU 00259 // should perform a read operation from any register on the PB bus before 00260 // executing the sleep instruction. 00261 AVR32_INTC.ipr[0]; // Dummy read 00262 00263 // Go to STATIC sleep mode. 00264 SLEEP(AVR32_PM_SMODE_STATIC); 00265 00266 while (TRUE); 00267 }
static void print_nvram_variables | ( | nvram_data_t * | nvram_data | ) | [static] |
Prints the variables stored in NVRAM.
nvram_data | Pointer to the NVRAM data structure to print. |
Definition at line 161 of file flash_example.c.
References nvram_data_t::var16, nvram_data_t::var32, nvram_data_t::var8, and nvram_data_t::var8_3.
Referenced by flash_rw_example().
00162 { 00163 print_dbg("var8:\t0x"); 00164 print_dbg_char_hex(nvram_data->var8); 00165 00166 print_dbg("\nvar16:\t0x"); 00167 print_dbg_short_hex(nvram_data->var16); 00168 00169 print_dbg("\nvar8_3:\t0x"); 00170 print_dbg_char_hex(nvram_data->var8_3[0]); 00171 print_dbg_char_hex(nvram_data->var8_3[1]); 00172 print_dbg_char_hex(nvram_data->var8_3[2]); 00173 00174 print_dbg("\nvar32:\t0x"); 00175 print_dbg_hex(nvram_data->var32); 00176 00177 print_dbg_char('\n'); 00178 }
nvram_data_t flash_nvram_data [static] |
NVRAM data structure located in the flash array.
Definition at line 144 of file flash_example.c.
Referenced by main().
scif_gclk_opt_t gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, OFF} [static] |
Definition at line 110 of file flash_example.c.
pcl_freq_param_t pcl_dfll_freq_param [static] |
Initial value:
{ .main_clk_src = PCL_MC_DFLL0, .cpu_f = EXAMPLE_TARGET_MCUCLK_FREQ_HZ, .pba_f = EXAMPLE_TARGET_PBACLK_FREQ_HZ, .pbb_f = EXAMPLE_TARGET_PBACLK_FREQ_HZ, .dfll_f = EXAMPLE_TARGET_DFLL_FREQ_HZ, .pextra_params = &gc_dfllif_ref_opt }
Definition at line 111 of file flash_example.c.
Referenced by main().
nvram_data_t user_nvram_data [static] |
NVRAM data structure located in the User page.
Definition at line 154 of file flash_example.c.
Referenced by main().