EMB Project Status (05/09/2010 - 14:15:34) | |||
Project File: | EMB.ise | Implementation State: | Synthesized |
Module Name: | memory_controller |
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Target Device: | xc3s500e-5pq208 |
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Product Version: | ISE 11.1 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 55 | 4656 | 1% | |
Number of Slice Flip Flops | 11 | 9312 | 0% | |
Number of 4 input LUTs | 91 | 9312 | 0% | |
Number of bonded IOBs | 144 | 232 | 62% | |
Number of GCLKs | 1 | 24 | 4% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Sun May 9 13:33:12 2010 | ||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |