scif_example2.c File Reference


Detailed Description

DFLL and main clock configuration and generic clock configuration and sleep mode example.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file scif_example2.c.

#include "board.h"
#include "gpio.h"
#include "scif_uc3l.h"
#include "power_clocks_lib.h"

Go to the source code of this file.

Defines

Generic Clock Configuration
#define EXAMPLE_FDFLL_HZ   24000000
#define EXAMPLE_FDFLL_KHZ   24000
 The target output frequency (24MHz) of the DFLL.
#define EXAMPLE_GCLK_FREQ_HZ   12000000
 The target frequency (12MHz) of the generic clock.
#define EXAMPLE_GCLK_FUNCTION   AVR32_SCIF_GCLK_1_0_FUNCTION
#define EXAMPLE_GCLK_ID   AVR32_SCIF_GCLK_DFLL0_SSG
#define EXAMPLE_GCLK_PIN   AVR32_SCIF_GCLK_1_0_PIN

Functions

static void local_start_dfll_clock ()
 Generate a high frequency clock with a DFLL running in closed-loop mode.
static void local_start_gc ()
 Set-up a generic clock at 12MHz with the DFLL as a source, output the generic clock to a pin.
int main (void)


Define Documentation

#define EXAMPLE_FDFLL_HZ   24000000

Definition at line 107 of file scif_example2.c.

Referenced by local_start_dfll_clock(), and local_start_gc().

#define EXAMPLE_FDFLL_KHZ   24000

The target output frequency (24MHz) of the DFLL.

Definition at line 106 of file scif_example2.c.

#define EXAMPLE_GCLK_FREQ_HZ   12000000

The target frequency (12MHz) of the generic clock.

Definition at line 110 of file scif_example2.c.

Referenced by local_start_gc().

#define EXAMPLE_GCLK_FUNCTION   AVR32_SCIF_GCLK_1_0_FUNCTION

Definition at line 96 of file scif_example2.c.

Referenced by local_start_gc().

#define EXAMPLE_GCLK_ID   AVR32_SCIF_GCLK_DFLL0_SSG

Definition at line 94 of file scif_example2.c.

Referenced by local_start_gc().

#define EXAMPLE_GCLK_PIN   AVR32_SCIF_GCLK_1_0_PIN

Definition at line 95 of file scif_example2.c.

Referenced by local_start_gc().


Function Documentation

static void local_start_dfll_clock (  )  [static]

Generate a high frequency clock with a DFLL running in closed-loop mode.

Definition at line 117 of file scif_example2.c.

References scif_gclk_opt_t::clock_source, scif_dfll_closedloop_conf_t::coarse, scif_dfll_closedloop_conf_t::coarsemaxstep, scif_gclk_opt_t::diven, EXAMPLE_FDFLL_HZ, scif_dfll_closedloop_conf_t::finemaxstep, scif_dfll_closedloop_conf_t::fmul, scif_dfll0_closedloop_mainref_gc_enable, scif_dfll0_closedloop_start(), SCIF_DFLL_MAXFREQ_HZ, SCIF_DFLL_MINFREQ_HZ, SCIF_GCCTRL_SLOWCLOCK, and SCIF_SLOWCLOCK_FREQ_HZ.

Referenced by main().

00118 {
00119   scif_dfll_closedloop_conf_t DfllConfig;
00120   scif_gclk_opt_t             GcConf;
00121   
00122 
00123   // 1) Configure and start the DFLL main reference generic clock:
00124   // use the undivided RCOSC slow clock as source for the generic clock. The
00125   // generic clock frequency will thus be ~115kHz.
00126   GcConf.clock_source = SCIF_GCCTRL_SLOWCLOCK;
00127   GcConf.diven = OFF;
00128   // Note: this function will start the AVR32_SCIF_GCLK_DFLL0_REF generic clock
00129   // (i.e. the generic clock dedicated to be the DFLL main reference clock).
00130   scif_dfll0_closedloop_mainref_gc_enable(&GcConf);
00131   
00132   // 2) Configure and start the DFLL.
00133   // The coarse value (= (fDFLL - SCIF_DFLL_MINFREQ_KHZ)*255/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ))
00134   DfllConfig.coarse = ((unsigned long long)(EXAMPLE_FDFLL_HZ - SCIF_DFLL_MINFREQ_HZ)*255)/(SCIF_DFLL_MAXFREQ_HZ - SCIF_DFLL_MINFREQ_HZ);
00135   // The fmul value (= (fDFLL*2^16)/fref, with fref being the frequency of the
00136   // DFLL main reference generic clock)
00137   DfllConfig.fmul = ((unsigned long long)EXAMPLE_FDFLL_HZ<<16)/SCIF_SLOWCLOCK_FREQ_HZ;
00138   // The fine and coarse maxstep values
00139 #if (defined(__GNUC__) \
00140       && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00141   ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00142       && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00143       // UC3L revC and higher
00144   DfllConfig.finemaxstep = 0x0000004;
00145   DfllConfig.coarsemaxstep = 0x0000004;
00146 #else
00147       // UC3L revB
00148       //+ Errata UC3L revB: 35.2.7 SCIF.12 DFLLIF indicates coarse lock too early
00149       //+ The DFLLIF might indicate coarse lock too early, the DFLL will lose
00150       //+ coarse lock and regain it later.
00151       //+ Fix/Workaround
00152       //+ Use max step size (DFLL0MAXSTEP.MAXSTEP) of 4 or higher.
00153   DfllConfig.maxstep = 0x0040004;
00154 #endif
00155   scif_dfll0_closedloop_start(&DfllConfig);
00156 }

static void local_start_gc (  )  [static]

Set-up a generic clock at 12MHz with the DFLL as a source, output the generic clock to a pin.

Definition at line 163 of file scif_example2.c.

References EXAMPLE_FDFLL_HZ, EXAMPLE_GCLK_FREQ_HZ, EXAMPLE_GCLK_FUNCTION, EXAMPLE_GCLK_ID, EXAMPLE_GCLK_PIN, scif_gc_enable(), scif_gc_setup(), and SCIF_GCCTRL_DFLL0.

Referenced by main().

00164 {
00165   // Setup gc on DFLL; the target frequency is 12MHz => divide the DFLL frequency
00166   // by 2 (== EXAMPLE_FDFLL_HZ / EXAMPLE_GCLK_FREQ_HZ).
00167   scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_DFLL0, AVR32_GC_DIV_CLOCK,
00168                 EXAMPLE_FDFLL_HZ/EXAMPLE_GCLK_FREQ_HZ);
00169   
00170   // Now enable the generic clock
00171   scif_gc_enable(EXAMPLE_GCLK_ID);
00172 
00173   /* Assign a GPIO to generic clock output */
00174   gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION);
00175   // Note that gclk1 is GPIO pin 6 pa06 on AT32UC3L064 pin 10 on QFP48.
00176 }

int main ( void   ) 

Definition at line 187 of file scif_example2.c.

References local_start_dfll_clock(), and local_start_gc().

00188 {
00189   // Generate a high frequency clock (~24MHz) with a DFLL in closed-loop mode
00190   local_start_dfll_clock();
00191 
00192   // Set the division ratio to apply to the main clock to 2 for each clock domain
00193   // so that each clock domain is at 12MHz.
00194   pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_2);
00195   pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_2);
00196   pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_2);
00197   // Switch the main clock source to the DFLL.
00198   pm_set_mclk_source(PM_CLK_SRC_DFLL0);
00199 
00200   // Set-up a generic clock from a high frequency clock and output it to a gpio pin.
00201   local_start_gc();
00202   
00203   //*** Sleep mode
00204   // If there is a chance that any PB write operations are incomplete, the CPU
00205   // should perform a read operation from any register on the PB bus before
00206   // executing the sleep instruction.
00207   AVR32_INTC.ipr[0];  // Dummy read
00208 
00209   // - Go into a sleep mode (while still maintaining GCLK output)
00210   SLEEP(AVR32_PM_SMODE_FROZEN);
00211 
00212   while(1);
00213 }


Generated on Fri Feb 19 02:26:22 2010 for AVR32 UC3 - SCIF Driver Example 1 by  doxygen 1.5.5