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00047 #include "compiler.h"
00048 #include "scif_uc3c.h"
00049
00050
00053
00054
00055 typedef union
00056 {
00057 unsigned long oscctrl[2];
00058 avr32_scif_oscctrl_t OSCCTRL[2];
00059 } u_avr32_scif_oscctrl_t;
00060
00061 typedef union
00062 {
00063 unsigned long pll[2];
00064 avr32_scif_pll_t PLL[2];
00065 } u_avr32_scif_pll_t;
00066
00067 typedef union
00068 {
00069 unsigned long oscctrl32;
00070 avr32_scif_oscctrl32_t OSCCTRL32;
00071 } u_avr32_scif_oscctrl32_t;
00072
00073
00074
00076
00077
00078
00079
00088 static long int scif_pclksr_statushigh_wait(unsigned long statusMask)
00089 {
00090 unsigned int timeout = SCIF_POLL_TIMEOUT;
00091
00092 while(!(AVR32_SCIF.pclksr & statusMask))
00093 {
00094 if(--timeout == 0)
00095 return -1;
00096 }
00097 return PASS;
00098 }
00099
00100 unsigned long scif_read_gplp(unsigned long gplp)
00101 {
00102 return AVR32_SCIF.gplp[gplp];
00103 }
00104
00105
00106 void scif_write_gplp(int gplp, unsigned long value)
00107 {
00108 SCIF_UNLOCK(AVR32_SCIF_GPLP + 4*gplp);
00109 AVR32_SCIF.gplp[gplp] = value;
00110 }
00111
00115
00116
00117
00121
00122
00123
00128 long int scif_start_osc(scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready)
00129 {
00130 u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl;
00131
00132 #ifdef AVR32SFW_INPUT_CHECK
00133
00134 if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ)
00135 || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ))
00136 {
00137 return -1;
00138 }
00139
00140 if( (opt->mode != SCIF_OSC_MODE_EXT_CLK)
00141 && (opt->mode != SCIF_OSC_MODE_2PIN_CRYSTAL))
00142 {
00143 return -1;
00144 }
00145
00146 if (osc == SCIF_OSC0)
00147 {
00148
00149 if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC)
00150 {
00151 return -1;
00152 }
00153
00154 if(opt->gain > AVR32_SCIF_OSCCTRL0_GAIN_G3)
00155 {
00156 return -1;
00157 }
00158 }
00159 else
00160 {
00161
00162 if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL1_STARTUP_16384_RCOSC)
00163 {
00164 return -1;
00165 }
00166
00167 if(opt->gain > AVR32_SCIF_OSCCTRL1_GAIN_G3)
00168 {
00169 return -1;
00170 }
00171 }
00172 #endif // AVR32SFW_INPUT_CHECK
00173
00174 u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ;
00175
00176 u_avr32_scif_oscctrl.OSCCTRL[osc].mode = opt->mode;
00177 u_avr32_scif_oscctrl.OSCCTRL[osc].gain = opt->gain;
00178 u_avr32_scif_oscctrl.OSCCTRL[osc].startup = opt->startup;
00179 u_avr32_scif_oscctrl.OSCCTRL[osc].oscen = ENABLE;
00180 AVR32_ENTER_CRITICAL_REGION( );
00181
00182 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);
00183
00184 AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc];
00185 AVR32_LEAVE_CRITICAL_REGION( );
00186
00187 if(true == wait_for_ready)
00188 {
00189
00190 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK))
00191 return -1;
00192 }
00193 return PASS;
00194 }
00195
00196
00197 bool scif_is_osc_ready(scif_osc_t osc)
00198 {
00199 if (osc == SCIF_OSC0)
00200 {
00201 return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC0RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC0RDY_OFFSET);
00202 }
00203 else
00204 {
00205 return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC1RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC1RDY_OFFSET);
00206 }
00207 }
00208
00209
00210 long int scif_stop_osc(scif_osc_t osc)
00211 {
00212
00213 unsigned long temp;
00214
00215 temp = AVR32_SCIF.oscctrl[osc];
00216 temp &= ~(AVR32_SCIF_OSCCTRL_OSCEN_DISABLE << AVR32_SCIF_OSCCTRL_OSCEN_OFFSET);
00217 AVR32_ENTER_CRITICAL_REGION( );
00218
00219 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);
00220
00221 AVR32_SCIF.oscctrl[osc] = temp;
00222 AVR32_LEAVE_CRITICAL_REGION( );
00223
00224 return PASS;
00225 }
00226
00227
00228 long int scif_configure_osc_crystalmode(scif_osc_t osc, unsigned int fcrystal)
00229 {
00230 u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl;
00231
00232 if (osc == SCIF_OSC0)
00233 {
00234
00235 u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0] = AVR32_SCIF.OSCCTRL[SCIF_OSC0] ;
00236
00237
00238 u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
00239 u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].gain = (fcrystal < 900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
00240 (fcrystal < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
00241 (fcrystal < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
00242 AVR32_SCIF_OSCCTRL0_GAIN_G3;
00243 AVR32_ENTER_CRITICAL_REGION( );
00244
00245 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL);
00246
00247 AVR32_SCIF.OSCCTRL[SCIF_OSC0] = u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0];
00248 AVR32_LEAVE_CRITICAL_REGION( );
00249 }
00250 else
00251 {
00252
00253 u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1] = AVR32_SCIF.OSCCTRL[SCIF_OSC1] ;
00254
00255
00256 u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1].mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
00257 u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1].gain = (fcrystal < 900000) ? AVR32_SCIF_OSCCTRL1_GAIN_G0 :
00258 (fcrystal < 3000000) ? AVR32_SCIF_OSCCTRL1_GAIN_G1 :
00259 (fcrystal < 8000000) ? AVR32_SCIF_OSCCTRL1_GAIN_G2 :
00260 AVR32_SCIF_OSCCTRL1_GAIN_G3;
00261 AVR32_ENTER_CRITICAL_REGION( );
00262
00263 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4);
00264
00265 AVR32_SCIF.OSCCTRL[SCIF_OSC1] = u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1];
00266 AVR32_LEAVE_CRITICAL_REGION( );
00267 }
00268
00269 return PASS;
00270 }
00271
00272 long int scif_configure_osc_extmode(scif_osc_t osc)
00273 {
00274 u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl;
00275
00276
00277 u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ;
00278
00279
00280 u_avr32_scif_oscctrl.OSCCTRL[osc].mode = SCIF_OSC_MODE_EXT_CLK;
00281 AVR32_ENTER_CRITICAL_REGION( );
00282
00283 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);
00284
00285 AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc];
00286 AVR32_LEAVE_CRITICAL_REGION( );
00287
00288 return PASS;
00289 }
00290
00291 long int scif_enable_osc(scif_osc_t osc, unsigned int startup, bool wait_for_ready)
00292 {
00293
00294 u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl;
00295
00296
00297 u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ;
00298
00299 u_avr32_scif_oscctrl.OSCCTRL[osc].startup = startup;
00300 u_avr32_scif_oscctrl.OSCCTRL[osc].oscen = ENABLE;
00301 AVR32_ENTER_CRITICAL_REGION( );
00302
00303 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);
00304
00305 AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc];
00306 AVR32_LEAVE_CRITICAL_REGION( );
00307
00308 if(true == wait_for_ready)
00309 {
00310
00311 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK))
00312 return -1;
00313 }
00314
00315 return PASS;
00316 }
00317
00318 long int scif_enable_extosc(scif_osc_t osc)
00319 {
00320
00321 u_avr32_scif_oscctrl_t u_avr32_scif_oscctrl;
00322
00323
00324 u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ;
00325
00326 u_avr32_scif_oscctrl.OSCCTRL[osc].oscen = ENABLE;
00327 AVR32_ENTER_CRITICAL_REGION( );
00328
00329 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);
00330
00331 AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc];
00332 AVR32_LEAVE_CRITICAL_REGION( );
00333
00334 return PASS;
00335 }
00336
00340 long int scif_pll_setup(scif_pll_t pll, const scif_pll_opt_t opt)
00341 {
00342
00343 u_avr32_scif_pll_t u_avr32_scif_pll;
00344
00345
00346 u_avr32_scif_pll.PLL[pll] = AVR32_SCIF.PLL[pll] ;
00347
00348 u_avr32_scif_pll.PLL[pll].pllosc = opt.osc;
00349 u_avr32_scif_pll.PLL[pll].pllopt = opt.pll_freq | (opt.pll_div2 << 1) | (opt.pll_wbwdisable << 2);
00350 u_avr32_scif_pll.PLL[pll].plldiv = opt.div;
00351 u_avr32_scif_pll.PLL[pll].pllmul = opt.mul;
00352 u_avr32_scif_pll.PLL[pll].pllcount= opt.lockcount;
00353 AVR32_ENTER_CRITICAL_REGION( );
00354
00355 SCIF_UNLOCK(AVR32_SCIF_PLL + 4*pll);
00356
00357 AVR32_SCIF.PLL[pll] = u_avr32_scif_pll.PLL[pll];
00358 AVR32_LEAVE_CRITICAL_REGION( );
00359
00360 return PASS;
00361 }
00362
00363 long int scif_pll_enable(scif_pll_t pll)
00364 {
00365
00366 u_avr32_scif_pll_t u_avr32_scif_pll;
00367
00368
00369 u_avr32_scif_pll.PLL[pll] = AVR32_SCIF.PLL[pll] ;
00370
00371 u_avr32_scif_pll.PLL[pll].pllen = ENABLE;
00372 AVR32_ENTER_CRITICAL_REGION( );
00373
00374 SCIF_UNLOCK(AVR32_SCIF_PLL + 4*pll);
00375
00376 AVR32_SCIF.PLL[pll] = u_avr32_scif_pll.PLL[pll];
00377 AVR32_LEAVE_CRITICAL_REGION( );
00378
00379 return PASS;
00380 }
00381
00382 long int scif_pll_disable(scif_pll_t pll)
00383 {
00384
00385 u_avr32_scif_pll_t u_avr32_scif_pll;
00386
00387
00388 u_avr32_scif_pll.PLL[pll] = AVR32_SCIF.PLL[pll] ;
00389
00390 u_avr32_scif_pll.PLL[pll].pllen = DISABLE;
00391 AVR32_ENTER_CRITICAL_REGION( );
00392
00393 SCIF_UNLOCK(AVR32_SCIF_PLL + 4*pll);
00394
00395 AVR32_SCIF.PLL[pll] = u_avr32_scif_pll.PLL[pll];
00396 AVR32_LEAVE_CRITICAL_REGION( );
00397
00398 return PASS;
00399 }
00400
00401 long int scif_wait_for_pll_locked(scif_pll_t pll)
00402 {
00403
00404 if (pll == SCIF_PLL0)
00405 {
00406
00407 while(!(AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_PLL0_LOCK_MASK));
00408 }
00409 else
00410 {
00411
00412 while(!(AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_PLL1_LOCK_MASK));
00413 }
00414
00415 return PASS;
00416 }
00417
00422 long int scif_start_osc32(const scif_osc32_opt_t *opt, bool wait_for_ready)
00423 {
00424 u_avr32_scif_oscctrl32_t u_avr32_scif_oscctrl32;
00425
00426
00427 #ifdef AVR32SFW_INPUT_CHECK
00428
00429 if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ)
00430 || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ))
00431 {
00432 return -1;
00433 }
00434
00435 if( (opt->mode < SCIF_OSC_MODE_EXT_CLK)
00436 || (opt->mode > SCIF_OSC_MODE_2PIN_CRYSTAL)
00437 || (opt->mode == SCIF_OSC_MODE_NOT_SUPPORTED_1)
00438 || (opt->mode == SCIF_OSC_MODE_NOT_SUPPORTED_2) )
00439 {
00440 return -1;
00441 }
00442
00443 if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL32_STARTUP_524288_RCOSC)
00444 {
00445 return -1;
00446 }
00447 #endif // AVR32SFW_INPUT_CHECK
00448
00449
00450 u_avr32_scif_oscctrl32.oscctrl32 = AVR32_SCIF.oscctrl32 ;
00451
00452
00453 u_avr32_scif_oscctrl32.OSCCTRL32.mode = opt->mode;
00454 u_avr32_scif_oscctrl32.OSCCTRL32.startup = opt->startup;
00455 u_avr32_scif_oscctrl32.OSCCTRL32.osc32en = ENABLE;
00456
00457 AVR32_ENTER_CRITICAL_REGION( );
00458
00459 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32);
00460
00461
00462 AVR32_SCIF.oscctrl32 = u_avr32_scif_oscctrl32.oscctrl32;
00463 AVR32_LEAVE_CRITICAL_REGION( );
00464
00465 if(true == wait_for_ready)
00466 {
00467
00468 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC32RDY_MASK))
00469 return -1;
00470 }
00471
00472 return PASS;
00473 }
00474
00475
00476 long scif_stop_osc32()
00477 {
00478 unsigned long temp = AVR32_SCIF.oscctrl32;
00479 temp &= ~(AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE << AVR32_SCIF_OSCCTRL32_OSC32EN_OFFSET);
00480
00481 AVR32_ENTER_CRITICAL_REGION( );
00482
00483 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32);
00484
00485
00486 AVR32_SCIF.oscctrl32 = temp;
00487 AVR32_LEAVE_CRITICAL_REGION( );
00488
00489 return PASS;
00490 }
00491
00492
00506 void scif_start_rc8M(void)
00507 {
00508 unsigned int* calibration_bits = (unsigned int*)0x80800200;
00509 AVR32_ENTER_CRITICAL_REGION( );
00510
00511 SCIF_UNLOCK(AVR32_SCIF_RCCR8);
00512 AVR32_SCIF.rccr8 = AVR32_SCIF_RCCR8_RCOSC8_EN_MASK | ((*calibration_bits)&AVR32_SCIF_RCCR8_CALIB_MASK);
00513 AVR32_LEAVE_CRITICAL_REGION( );
00514 }
00515
00516 void scif_stop_rc8M(void)
00517 {
00518 unsigned long temp = AVR32_SCIF.rccr8;
00519
00520 AVR32_ENTER_CRITICAL_REGION( );
00521
00522 SCIF_UNLOCK(AVR32_SCIF_RCCR8);
00523 temp &= ~AVR32_SCIF_RCCR8_RCOSC8_EN_MASK;
00524 AVR32_SCIF.rccr8 = temp;
00525 AVR32_LEAVE_CRITICAL_REGION( );
00526 }
00527
00532 void scif_start_rc120M(void)
00533 {
00534 AVR32_ENTER_CRITICAL_REGION( );
00535
00536 SCIF_UNLOCK(AVR32_SCIF_RC120MCR);
00537 AVR32_SCIF.rc120mcr = AVR32_SCIF_RC120MCR_EN_MASK;
00538 AVR32_LEAVE_CRITICAL_REGION( );
00539 }
00540
00541 void scif_stop_rc120M(void)
00542 {
00543 unsigned long temp = AVR32_SCIF.rc120mcr;
00544
00545 AVR32_ENTER_CRITICAL_REGION( );
00546
00547 SCIF_UNLOCK(AVR32_SCIF_RC120MCR);
00548 temp &= ~AVR32_SCIF_RC120MCR_EN_MASK;
00549 AVR32_SCIF.rc120mcr = temp;
00550 AVR32_LEAVE_CRITICAL_REGION( );
00551 }
00552
00553
00554
00559 long int scif_start_gclk(unsigned int gclk, const scif_gclk_opt_t *opt)
00560 {
00561 #ifdef AVR32SFW_INPUT_CHECK
00562
00563 if( gclk > AVR32_SCIF_GCLK_NUM )
00564 {
00565 return -1;
00566 }
00567
00568 if(( opt->clock_source >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( opt->clock_source < 0 ))
00569 {
00570 return -1;
00571 }
00572 #endif // AVR32SFW_INPUT_CHECK
00573
00574
00575 if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00576 return -1;
00577
00578
00579 AVR32_SCIF.gcctrl[gclk] = ((opt->divider << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK)
00580 |((opt->diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK)
00581 |((opt->clock_source << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK)
00582 |(AVR32_SCIF_GCCTRL_CEN_MASK);
00583
00584 return PASS;
00585 }
00586
00587
00588 long int scif_stop_gclk(unsigned int gclk)
00589 {
00590 unsigned int timeout = SCIF_POLL_TIMEOUT;
00591
00592 #ifdef AVR32SFW_INPUT_CHECK
00593
00594 if( gclk > AVR32_SCIF_GCLK_NUM )
00595 {
00596 return -1;
00597 }
00598 #endif // AVR32SFW_INPUT_CHECK
00599
00600
00601 AVR32_SCIF.gcctrl[gclk] &= ~AVR32_SCIF_GCCTRL_CEN_MASK;
00602
00603
00604 while(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00605 {
00606 if(--timeout == 0)
00607 return -1;
00608 }
00609
00610 return PASS;
00611 }
00612
00613
00614 long int scif_gc_setup(unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor)
00615 {
00616 int restart_gc = false;
00617
00618
00619
00620 divfactor = (divfactor>>1) -1;
00621
00622 #ifdef AVR32SFW_INPUT_CHECK
00623
00624 if( gclk > AVR32_SCIF_GCLK_NUM )
00625 {
00626 return -1;
00627 }
00628
00629 if(( clk_src >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( clk_src < 0 ))
00630 {
00631 return -1;
00632 }
00633
00634 if(diven)
00635 {
00636 if(divfactor >= (1<<AVR32_SCIF_GCCTRL_DIV_SIZE))
00637 return -1;
00638 }
00639 #endif // AVR32SFW_INPUT_CHECK
00640
00641
00642 if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00643 {
00644 restart_gc = true;
00645 if(scif_stop_gclk(gclk) < 0)
00646 return -1;
00647 }
00648
00649
00650 AVR32_SCIF.gcctrl[gclk] = ((divfactor << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK)
00651 |((diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK)
00652 |((clk_src << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK);
00653
00654
00655 if(true == restart_gc)
00656 AVR32_SCIF.gcctrl[gclk] |= AVR32_SCIF_GCCTRL_CEN_MASK ;
00657
00658 return PASS;
00659 }
00660
00661
00662 long int scif_gc_enable(unsigned int gclk)
00663 {
00664 #ifdef AVR32SFW_INPUT_CHECK
00665
00666 if( gclk > AVR32_SCIF_GCLK_NUM )
00667 {
00668 return -1;
00669 }
00670 #endif // AVR32SFW_INPUT_CHECK
00671
00672
00673 if(!(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK))
00674 AVR32_SCIF.gcctrl[gclk] |= AVR32_SCIF_GCCTRL_CEN_MASK;
00675
00676 return PASS;
00677
00678 }
00679
00680 void scif_bod18_enable_irq(void)
00681 {
00682 AVR32_SCIF.ier = AVR32_SCIF_IER_BODDET_MASK ;
00683 }
00684
00685 void scif_bod18_disable_irq(void)
00686 {
00687 Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00688
00689 if (global_interrupt_enabled) Disable_global_interrupt();
00690 AVR32_SCIF.idr = AVR32_SCIF_IDR_BODDET_MASK;
00691 AVR32_SCIF.isr;
00692 if (global_interrupt_enabled) Enable_global_interrupt();
00693 }
00694
00695 void scif_bod18_clear_irq(void)
00696 {
00697 AVR32_SCIF.icr = AVR32_SCIF_ICR_BODDET_MASK;
00698 }
00699
00700 unsigned long scif_bod18_get_irq_status(void)
00701 {
00702 return ((AVR32_SCIF.isr & AVR32_SCIF_ISR_BODDET_MASK) != 0);
00703 }
00704
00705 unsigned long scif_bod18_get_irq_enable_bit(void)
00706 {
00707 return ((AVR32_SCIF.imr & AVR32_SCIF_IMR_BODDET_MASK) != 0);
00708 }
00709
00710 unsigned long scif_bod18_get_level(void)
00711 {
00712 return (AVR32_SCIF.bod & AVR32_SCIF_BOD_LEVEL_MASK) >> AVR32_SCIF_BOD_LEVEL_OFFSET;
00713 }
00714
00715 void scif_bod33_enable_irq(void)
00716 {
00717 AVR32_SCIF.ier = AVR32_SCIF_IER_BOD33DET_MASK ;
00718 }
00719
00720 void scif_bod33_disable_irq(void)
00721 {
00722 Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00723
00724 if (global_interrupt_enabled) Disable_global_interrupt();
00725 AVR32_SCIF.idr = AVR32_SCIF_IDR_BOD33DET_MASK;
00726 AVR32_SCIF.isr;
00727 if (global_interrupt_enabled) Enable_global_interrupt();
00728 }
00729
00730 void scif_bod33_clear_irq(void)
00731 {
00732 AVR32_SCIF.icr = AVR32_SCIF_ICR_BOD33DET_MASK;
00733 }
00734
00735 unsigned long scif_bod33_get_irq_status(void)
00736 {
00737 return ((AVR32_SCIF.isr & AVR32_SCIF_ISR_BOD33DET_MASK) != 0);
00738 }
00739
00740 unsigned long scif_bod33_get_irq_enable_bit(void)
00741 {
00742 return ((AVR32_SCIF.imr & AVR32_SCIF_IMR_BOD33DET_MASK) != 0);
00743 }
00744
00745 unsigned long scif_bod33_get_level(void)
00746 {
00747 return (AVR32_SCIF.bod33 & AVR32_SCIF_BOD33_LEVEL_MASK) >> AVR32_SCIF_BOD33_LEVEL_OFFSET;
00748 }
00749
00750 void scif_bod50_enable_irq(void)
00751 {
00752 AVR32_SCIF.ier = AVR32_SCIF_IER_BOD50DET_MASK ;
00753 }
00754
00755 void scif_bod50_disable_irq(void)
00756 {
00757 Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00758
00759 if (global_interrupt_enabled) Disable_global_interrupt();
00760 AVR32_SCIF.idr = AVR32_SCIF_IDR_BOD50DET_MASK;
00761 AVR32_SCIF.isr;
00762 if (global_interrupt_enabled) Enable_global_interrupt();
00763 }
00764
00765 void scif_bod50_clear_irq(void)
00766 {
00767 AVR32_SCIF.icr = AVR32_SCIF_ICR_BOD50DET_MASK;
00768 }
00769
00770 unsigned long scif_bod50_get_irq_status(void)
00771 {
00772 return ((AVR32_SCIF.isr & AVR32_SCIF_ISR_BOD50DET_MASK) != 0);
00773 }
00774
00775 unsigned long scif_bod50_get_irq_enable_bit(void)
00776 {
00777 return ((AVR32_SCIF.imr & AVR32_SCIF_IMR_BOD50DET_MASK) != 0);
00778 }
00779
00780 unsigned long scif_bod50_get_level(void)
00781 {
00782 return (AVR32_SCIF.bod50 & AVR32_SCIF_BOD50_LEVEL_MASK) >> AVR32_SCIF_BOD50_LEVEL_OFFSET;
00783 }
00784