System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
< data not available > < data not available > < data not available >
Path F:\Xilinx\13.4\ISE_DS\ISE\\lib\nt64;
F:\Xilinx\13.4\ISE_DS\ISE\\bin\nt64;
F:\Xilinx\13.4\ISE_DS\PlanAhead\bin;
F:\Xilinx\13.4\ISE_DS\ISE\bin\nt64;
F:\Xilinx\13.4\ISE_DS\ISE\lib\nt64;
F:\Xilinx\13.4\ISE_DS\common\bin\nt64;
F:\Xilinx\13.4\ISE_DS\common\lib\nt64;
C:\Program Files (x86)\AMD APP\bin\x86_64;
C:\Program Files (x86)\AMD APP\bin\x86;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
c:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;
C:\Program Files\Java\jdk1.6.0_24\bin;
C:\Program Files (x86)\Atmel\AVR Studio 5.0\AVR Toolchain\bin;
C:\Program Files (x86)\Java\jre6\bin;
C:\cygwin\bin;
C:\Program Files (x86)\Dia\bin
< data not available > < data not available > < data not available >
XILINX F:\Xilinx\13.4\ISE_DS\ISE\ < data not available > < data not available > < data not available >
XILINX_DSP F:\Xilinx\13.4\ISE_DS\ISE < data not available > < data not available > < data not available >
XILINX_PLANAHEAD F:\Xilinx\13.4\ISE_DS\PlanAhead < data not available > < data not available > < data not available >
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   cpu.prj  
-ifmt   mixed MIXED
-ofn   cpu  
-ofmt   NGC NGC
-p   xc3s500e-5-pq208  
-top   cpu  
-opt_mode Optimization Goal Speed SPEED
-opt_level Optimization Effort 1 1
-iuc Use synthesis Constraints File NO NO
-keep_hierarchy Keep Hierarchy No NO
-netlist_hierarchy Netlist Hierarchy As_Optimized as_optimized
-rtlview Generate RTL Schematic Yes NO
-glob_opt Global Optimization Goal AllClockNets ALLCLOCKNETS
-read_cores Read Cores YES YES
-write_timing_constraints Write Timing Constraints NO NO
-cross_clock_analysis Cross Clock Analysis NO NO
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100%
-bram_utilization_ratio BRAM Utilization Ratio 100 100%
-verilog2001 Verilog 2001 YES YES
-fsm_extract   YES YES
-fsm_encoding   Auto AUTO
-safe_implementation   No NO
-fsm_style   LUT LUT
-ram_extract   Yes YES
-ram_style   Auto AUTO
-rom_extract   Yes YES
-shreg_extract   YES YES
-rom_style   Auto AUTO
-auto_bram_packing   NO NO
-resource_sharing   YES YES
-async_to_sync   NO NO
-mult_style   Auto AUTO
-iobuf   YES YES
-max_fanout   500 500
-bufg   24 24
-register_duplication   YES YES
-register_balancing   No NO
-optimize_primitives   NO NO
-use_clock_enable   Yes YES
-use_sync_set   Yes YES
-use_sync_reset   Yes YES
-iob   Auto AUTO
-equivalent_register_removal   YES YES
-slice_utilization_ratio_maxmargin   5 0%
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed AMD Phenom(tm) II X4 945 Processor/3007 MHz <  data not available  > <  data not available  > <  data not available  >
Host beist <  data not available  > <  data not available  > <  data not available  >
OS Name Microsoft Windows 7 , 64-bit <  data not available  > <  data not available  > <  data not available  >
OS Release Service Pack 1 (build 7601) <  data not available  > <  data not available  > <  data not available  >