ssc_i2s.h File Reference


Detailed Description

SSC I2S example driver.

This file defines a useful set of functions for the SSC I2S interface on AVR32 devices. The driver handles normal polled usage and direct memory access (PDC) usage.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file ssc_i2s.h.

#include <avr32/io.h>

Go to the source code of this file.

Defines

#define SSC_I2S_TIMEOUT_VALUE   10000

Enumerations

enum  {
  SSC_I2S_ERROR = -1, SSC_I2S_OK = 0, SSC_I2S_TIMEOUT = 1, SSC_I2S_ERROR_ARGUMENT,
  SSC_I2S_ERROR_RX, SSC_I2S_ERROR_TX
}
 Error codes used by SSC I2S driver. More...
enum  {
  SSC_I2S_MODE_STEREO_OUT = 1, SSC_I2S_MODE_STEREO_OUT_EXT_CLK, SSC_I2S_MODE_SLAVE_STEREO_OUT, SSC_I2S_MODE_SLAVE_STEREO_IN,
  SSC_I2S_MODE_STEREO_OUT_MONO_IN, SSC_I2S_MODE_RIGHT_IN, SSC_I2S_MODE_STEREO_IN, SSC_I2S_MODE_STEREO_OUT_STEREO_IN
}
 SSC I2S modes. More...

Functions

void ssc_i2s_disable_interrupts (volatile avr32_ssc_t *ssc, unsigned long int_mask)
 Disables the specified SSC interrupts.
void ssc_i2s_enable_interrupts (volatile avr32_ssc_t *ssc, unsigned long int_mask)
 Enables the specified SSC interrupts.
unsigned long ssc_i2s_get_status (volatile avr32_ssc_t *ssc)
 Returns the SSC status.
int ssc_i2s_init (volatile avr32_ssc_t *ssc, unsigned int sample_frequency, unsigned int data_bit_res, unsigned int frame_bit_res, unsigned char mode, unsigned int pba_hz)
 Sets up registers and intializes SSC for use as I2S.
void ssc_i2s_reset (volatile avr32_ssc_t *ssc)
 Resets the SSC module.
int ssc_i2s_transfer (volatile avr32_ssc_t *ssc, unsigned int data)
 Transfers a single message of data.


Define Documentation

#define SSC_I2S_TIMEOUT_VALUE   10000

Definition at line 60 of file ssc_i2s.h.

Referenced by ssc_i2s_transfer().


Enumeration Type Documentation

anonymous enum

Error codes used by SSC I2S driver.

Enumerator:
SSC_I2S_ERROR 
SSC_I2S_OK 
SSC_I2S_TIMEOUT 
SSC_I2S_ERROR_ARGUMENT 
SSC_I2S_ERROR_RX 
SSC_I2S_ERROR_TX 

Definition at line 65 of file ssc_i2s.h.

00066 {
00067   SSC_I2S_ERROR = -1,
00068   SSC_I2S_OK = 0,
00069   SSC_I2S_TIMEOUT = 1,
00070   SSC_I2S_ERROR_ARGUMENT,
00071   SSC_I2S_ERROR_RX,
00072   SSC_I2S_ERROR_TX
00073 };

anonymous enum

SSC I2S modes.

Enumerator:
SSC_I2S_MODE_STEREO_OUT  Two output channels.
SSC_I2S_MODE_STEREO_OUT_EXT_CLK  Two output channels sampled with an external clock received from the SSC_RX_CLOCK line.
SSC_I2S_MODE_SLAVE_STEREO_OUT  Two output channels controlled by the DAC.
SSC_I2S_MODE_SLAVE_STEREO_IN  Two input channels controlled by the DAC.
SSC_I2S_MODE_STEREO_OUT_MONO_IN  Two output, one input channel.
SSC_I2S_MODE_RIGHT_IN  Right channel in. Used because one SSC only can manage one input channel at a time.
SSC_I2S_MODE_STEREO_IN  Two input channels.
SSC_I2S_MODE_STEREO_OUT_STEREO_IN  Two output channels and two input channels.

Definition at line 76 of file ssc_i2s.h.


Function Documentation

void ssc_i2s_disable_interrupts ( volatile avr32_ssc_t *  ssc,
unsigned long  int_mask 
)

Disables the specified SSC interrupts.

Parameters:
ssc Base address of the SSC instance.
int_mask Bit-mask of SSC interrupts (AVR32_SSC_IDR_x_MASK).

Definition at line 408 of file ssc_i2s.c.

00409 {
00410   Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00411 
00412   if (global_interrupt_enabled) Disable_global_interrupt();
00413   ssc->idr = int_mask;
00414   ssc->sr;
00415   if (global_interrupt_enabled) Enable_global_interrupt();
00416 }

void ssc_i2s_enable_interrupts ( volatile avr32_ssc_t *  ssc,
unsigned long  int_mask 
)

Enables the specified SSC interrupts.

Parameters:
ssc Base address of the SSC instance.
int_mask Bit-mask of SSC interrupts (AVR32_SSC_IER_x_MASK).

Definition at line 419 of file ssc_i2s.c.

00420 {
00421   ssc->ier = int_mask;
00422 }

unsigned long ssc_i2s_get_status ( volatile avr32_ssc_t *  ssc  ) 

Returns the SSC status.

Parameters:
ssc Base address of the SSC instance.
Returns:
The SSC Status Register.

Definition at line 425 of file ssc_i2s.c.

Referenced by main().

00426 {
00427   return ssc->sr;
00428 }

int ssc_i2s_init ( volatile avr32_ssc_t *  ssc,
unsigned int  sample_frequency,
unsigned int  data_bit_res,
unsigned int  frame_bit_res,
unsigned char  mode,
unsigned int  pba_hz 
)

Sets up registers and intializes SSC for use as I2S.

Parameters:
ssc Pointer to the correct volatile avr32_ssc_t struct
sample_frequency The sample frequency given in Hz
data_bit_res Number of significant data bits in an I2S channel frame
frame_bit_res Total number of bits in an I2S channel frame
mode I2S-mode
  • SSC_I2S_MODE_STEREO_OUT
  • SSC_I2S_MODE_STEREO_OUT_EXT_CLK
  • SSC_I2S_MODE_SLAVE_STEREO_OUT
  • SSC_I2S_MODE_STEREO_OUT_MONO_IN
  • SSC_I2S_MODE_RIGHT_IN
  • SSC_I2S_MODE_STEREO_IN
  • SSC_I2S_MODE_STEREO_OUT_STEREO_IN
pba_hz The clock speed of the PBA bus in Hz.
Returns:
Status
Return values:
SSC_I2S_OK when no error occured.
SSC_I2S_ERROR_ARGUMENT when invalid arguments are passed

Todo:
check input values

Definition at line 89 of file ssc_i2s.c.

References set_clock_divider(), SSC_I2S_MODE_RIGHT_IN, SSC_I2S_MODE_SLAVE_STEREO_IN, SSC_I2S_MODE_SLAVE_STEREO_OUT, SSC_I2S_MODE_STEREO_OUT, SSC_I2S_MODE_STEREO_OUT_EXT_CLK, SSC_I2S_MODE_STEREO_OUT_MONO_IN, SSC_I2S_OK, and ssc_i2s_reset().

Referenced by main().

00095 {
00097 
00098   /* Reset */
00099   ssc_i2s_reset(ssc);
00100 
00101   if (mode == SSC_I2S_MODE_SLAVE_STEREO_OUT)
00102   {
00103     ssc->cmr = AVR32_SSC_CMR_DIV_NOT_ACTIVE << AVR32_SSC_CMR_DIV_OFFSET;
00104 
00105     ssc->tcmr = AVR32_SSC_TCMR_CKS_TK_PIN               << AVR32_SSC_TCMR_CKS_OFFSET    |
00106                 AVR32_SSC_TCMR_CKO_INPUT_ONLY           << AVR32_SSC_TCMR_CKO_OFFSET    |
00107                 0                                       << AVR32_SSC_TCMR_CKI_OFFSET    |
00108                 AVR32_SSC_TCMR_CKG_NONE                 << AVR32_SSC_TCMR_CKG_OFFSET    |
00109                 AVR32_SSC_TCMR_START_DETECT_ANY_EDGE_TF << AVR32_SSC_TCMR_START_OFFSET  |
00110                 1                                       << AVR32_SSC_TCMR_STTDLY_OFFSET |
00111                 0                                       << AVR32_SSC_TCMR_PERIOD_OFFSET;
00112 #ifdef AVR32_SSC_220_H_INCLUDED
00113     ssc->tfmr = (data_bit_res - 1)             << AVR32_SSC_TFMR_DATLEN_OFFSET  |
00114                 0                              << AVR32_SSC_TFMR_DATDEF_OFFSET  |
00115                 1                              << AVR32_SSC_TFMR_MSBF_OFFSET    |
00116                 (1 - 1)                        << AVR32_SSC_TFMR_DATNB_OFFSET   |
00117                 0                              << AVR32_SSC_TFMR_FSLEN_OFFSET   |
00118                 AVR32_SSC_TFMR_FSOS_INPUT_ONLY << AVR32_SSC_TFMR_FSOS_OFFSET    |
00119                 0                              << AVR32_SSC_TFMR_FSDEN_OFFSET   |
00120                 0                              << AVR32_SSC_TFMR_FSEDGE_OFFSET;
00121 #else
00122     ssc->tfmr = (data_bit_res - 1)             << AVR32_SSC_TFMR_DATLEN_OFFSET  |
00123                 0                              << AVR32_SSC_TFMR_DATDEF_OFFSET  |
00124                 1                              << AVR32_SSC_TFMR_MSBF_OFFSET    |
00125                 (1 - 1)                        << AVR32_SSC_TFMR_DATNB_OFFSET   |
00126                 0                              << AVR32_SSC_TFMR_FSLEN_OFFSET   |
00127                 AVR32_SSC_TFMR_FSOS_INPUT_ONLY << AVR32_SSC_TFMR_FSOS_OFFSET    |
00128                 0                              << AVR32_SSC_TFMR_FSDEN_OFFSET   |
00129                 0                              << AVR32_SSC_TFMR_FSEDGE_OFFSET  |
00130                 0                              << AVR32_SSC_TFMR_FSLENHI_OFFSET;
00131 #endif
00132     ssc->cr = AVR32_SSC_CR_TXEN_MASK;
00133   }
00134   else if (mode == SSC_I2S_MODE_SLAVE_STEREO_IN)
00135   {
00136     ssc->cmr = AVR32_SSC_CMR_DIV_NOT_ACTIVE << AVR32_SSC_CMR_DIV_OFFSET;
00137     ssc->tcmr = 0;
00138     ssc->tfmr = 0;
00139     ssc->rcmr = (AVR32_SSC_RCMR_CKS_RK_PIN << AVR32_SSC_RCMR_CKS_OFFSET) |
00140                 (1                             << AVR32_SSC_RCMR_CKI_OFFSET)|
00141                 (AVR32_SSC_RCMR_CKO_INPUT_ONLY << AVR32_SSC_RCMR_CKO_OFFSET) |
00142                 (1                         << AVR32_SSC_RCMR_STTDLY_OFFSET ) |
00143                 (AVR32_SSC_RCMR_START_DETECT_FALLING_RF << AVR32_SSC_RCMR_START_OFFSET) 
00144     ;
00145 
00146 #ifdef AVR32_SSC_220_H_INCLUDED
00147     ssc->rfmr = (data_bit_res - 1)                                 << AVR32_SSC_RFMR_DATLEN_OFFSET                              |
00148                 1                                                  << AVR32_SSC_RFMR_MSBF_OFFSET                                |
00149                 (1 - 1)                                            << AVR32_SSC_RFMR_DATNB_OFFSET                               |
00150                 (((frame_bit_res - 1)                              << AVR32_SSC_RFMR_FSLEN_OFFSET) & AVR32_SSC_RFMR_FSLEN_MASK) |
00151                 AVR32_SSC_RFMR_FSOS_INPUT_ONLY                     << AVR32_SSC_RFMR_FSOS_OFFSET                                |
00152                 1                                                  << AVR32_SSC_RFMR_FSEDGE_OFFSET;
00153 #else
00154     ssc->rfmr = (data_bit_res - 1)                                 << AVR32_SSC_RFMR_DATLEN_OFFSET                              |
00155                 1                                                  << AVR32_SSC_RFMR_MSBF_OFFSET                                |
00156                 (1 - 1)                                            << AVR32_SSC_RFMR_DATNB_OFFSET                               |
00157                 (((frame_bit_res - 1)                              << AVR32_SSC_RFMR_FSLEN_OFFSET) & AVR32_SSC_RFMR_FSLEN_MASK) |
00158                 AVR32_SSC_RFMR_FSOS_INPUT_ONLY                     << AVR32_SSC_RFMR_FSOS_OFFSET                                |
00159                 1                                                  << AVR32_SSC_RFMR_FSEDGE_OFFSET                              |
00160                 ((frame_bit_res - 1) >> AVR32_SSC_RFMR_FSLEN_SIZE) << AVR32_SSC_RFMR_FSLENHI_OFFSET;
00161 #endif
00162 
00163     ssc->cr = AVR32_SSC_CR_RXEN_MASK;
00164 
00165   }
00166   else
00167   {
00168     // Possible states:
00169     // SSC_I2S_MODE_STEREO_OUT,
00170     // SSC_I2S_MODE_STEREO_OUT_EXT_CLK,
00171     // SSC_I2S_MODE_STEREO_OUT_MONO_IN,
00172     // SSC_I2S_MODE_RIGHT_IN,
00173     // SSC_I2S_MODE_STEREO_IN,
00174     // SSC_I2S_MODE_STEREO_OUT_STEREO_IN
00175 
00176     unsigned long txen_mask = 0x00000000,
00177                   rxen_mask = 0x00000000;
00178 
00179     if (mode != SSC_I2S_MODE_STEREO_OUT_EXT_CLK)
00180     {
00181       /* Set clock divider */
00182       set_clock_divider(ssc, 2 * sample_frequency * frame_bit_res, pba_hz);
00183     }
00184 
00185     /* SSC can only receive one channel of audio input.  In order
00186      * to use two inputs, two SSC's must be used. The first (master)
00187      * deals with both output channels and the left input, and should
00188      * be set to mode=SSC_I2S_MODE_STEREO_OUT_MONO_IN, and the second to
00189      * mode=SSC_I2S_MODE_RIGHT_IN. The second SSC should be connected to the
00190      * first SSC's in the following way:
00191      * master-ssc:TF -> slave-ssc:RF,
00192      * master-ssc:TK -> slave-ssc:RK
00193      */
00194 
00195     /* If only slave I2S SSC, do not set transmit registers */
00196     if (mode != SSC_I2S_MODE_RIGHT_IN)
00197     {
00198       // Possible states:
00199       // SSC_I2S_MODE_STEREO_OUT,
00200       // SSC_I2S_MODE_STEREO_OUT_EXT_CLK,
00201       // SSC_I2S_MODE_STEREO_OUT_MONO_IN,
00202       // SSC_I2S_MODE_STEREO_IN,
00203       // SSC_I2S_MODE_STEREO_OUT_STEREO_IN
00204 
00205       if (mode != SSC_I2S_MODE_STEREO_OUT_EXT_CLK)
00206       {
00207         // Possible states:
00208         // SSC_I2S_MODE_STEREO_OUT,
00209         // SSC_I2S_MODE_STEREO_OUT_MONO_IN,
00210         // SSC_I2S_MODE_STEREO_IN,
00211         // SSC_I2S_MODE_STEREO_OUT_STEREO_IN
00212 
00213         /* Set transmit clock mode:
00214          *   CKS - use divided clock,
00215          *   CKO - transmit continous clock on TK
00216          *   CKI - shift data on falling clock
00217          *   CKG - transmit continous clock on TK
00218          *   START - on falling TF(WS) edge
00219          *   STTDLY - TF toggles before last bit of last word, not before
00220          *            first bit on next word. Therefore: delay one cycle.
00221          *   PERIOD - generate framesync for each sample (FS is generated
00222          *            every (PERIOD + 1) * 2 clock)
00223          */
00224         ssc->tcmr = AVR32_SSC_TCMR_CKS_DIV_CLOCK              << AVR32_SSC_TCMR_CKS_OFFSET    |
00225                     AVR32_SSC_TCMR_CKO_CONTINOUS_CLOCK_OUTPUT << AVR32_SSC_TCMR_CKO_OFFSET    |
00226                     0                                         << AVR32_SSC_TCMR_CKI_OFFSET    |
00227                     AVR32_SSC_TCMR_CKG_NONE                   << AVR32_SSC_TCMR_CKG_OFFSET    |
00228                     AVR32_SSC_TCMR_START_DETECT_ANY_EDGE_TF   << AVR32_SSC_TCMR_START_OFFSET  |
00229                     1                                         << AVR32_SSC_TCMR_STTDLY_OFFSET |
00230                     (frame_bit_res - 1)                       << AVR32_SSC_TCMR_PERIOD_OFFSET;
00231       }
00232       else
00233       {
00234         // Possible states:
00235         // SSC_I2S_MODE_STEREO_OUT_EXT_CLK
00236 
00237         /* Set transmit clock mode:
00238          *   CKS - use RX clock,
00239          *   CKO - transmit continous clock on TK
00240          *   CKI - shift data on falling clock
00241          *   CKG - transmit continous clock on TK
00242          *   START - on falling TF(WS) edge
00243          *   STTDLY - TF toggles before last bit of last word, not before
00244          *            first bit on next word. Therefore: delay one cycle.
00245          *   PERIOD - generate framesync for each sample (FS is generated
00246          *            every (PERIOD + 1) * 2 clock)
00247          */
00248         ssc->tcmr = AVR32_SSC_TCMR_CKS_RK_CLOCK               << AVR32_SSC_TCMR_CKS_OFFSET    |
00249                     AVR32_SSC_TCMR_CKO_CONTINOUS_CLOCK_OUTPUT << AVR32_SSC_TCMR_CKO_OFFSET    |
00250                     0                                         << AVR32_SSC_TCMR_CKI_OFFSET    |
00251                     AVR32_SSC_TCMR_CKG_NONE                   << AVR32_SSC_TCMR_CKG_OFFSET    |
00252                     AVR32_SSC_TCMR_START_DETECT_ANY_EDGE_TF   << AVR32_SSC_TCMR_START_OFFSET  |
00253                     1                                         << AVR32_SSC_TCMR_STTDLY_OFFSET |
00254                     (frame_bit_res - 1)                       << AVR32_SSC_TCMR_PERIOD_OFFSET;
00255         /* Set receive clock mode:
00256          *  CKS - uses RK pin
00257          */
00258         ssc->rcmr = (AVR32_SSC_RCMR_CKS_RK_PIN << AVR32_SSC_RCMR_CKS_OFFSET);
00259       }
00260 
00261       /* Set transmit frame mode:
00262        *  DATLEN - one sample for one channel
00263        *  DATDEF - Default to zero,
00264        *  MSBF - transmit msb first,
00265        *  DATNB - Transfer two words (left+right),
00266        *  FSLEN - Frame sync is entire left channel
00267        *  FSOS - transmit negative pulse on WS (start sync on left channel)
00268        *  FSDEN - Do not use transmit frame sync data
00269        *  FSEDGE - detect frame sync positive edge
00270        */
00271 #ifdef AVR32_SSC_220_H_INCLUDED
00272       ssc->tfmr = (data_bit_res - 1)                                 << AVR32_SSC_TFMR_DATLEN_OFFSET                              |
00273                   0                                                  << AVR32_SSC_TFMR_DATDEF_OFFSET                              |
00274                   1                                                  << AVR32_SSC_TFMR_MSBF_OFFSET                                |
00275                   (1 - 1)                                            << AVR32_SSC_TFMR_DATNB_OFFSET                               |
00276                   (((frame_bit_res - 1)                              << AVR32_SSC_TFMR_FSLEN_OFFSET) & AVR32_SSC_TFMR_FSLEN_MASK) |
00277                   AVR32_SSC_TFMR_FSOS_NEG_PULSE                      << AVR32_SSC_TFMR_FSOS_OFFSET                                |
00278                   0                                                  << AVR32_SSC_TFMR_FSDEN_OFFSET                               |
00279                   1                                                  << AVR32_SSC_TFMR_FSEDGE_OFFSET;
00280 #else
00281       ssc->tfmr = (data_bit_res - 1)                                 << AVR32_SSC_TFMR_DATLEN_OFFSET                              |
00282                   0                                                  << AVR32_SSC_TFMR_DATDEF_OFFSET                              |
00283                   1                                                  << AVR32_SSC_TFMR_MSBF_OFFSET                                |
00284                   (1 - 1)                                            << AVR32_SSC_TFMR_DATNB_OFFSET                               |
00285                   (((frame_bit_res - 1)                              << AVR32_SSC_TFMR_FSLEN_OFFSET) & AVR32_SSC_TFMR_FSLEN_MASK) |
00286                   AVR32_SSC_TFMR_FSOS_NEG_PULSE                      << AVR32_SSC_TFMR_FSOS_OFFSET                                |
00287                   0                                                  << AVR32_SSC_TFMR_FSDEN_OFFSET                               |
00288                   1                                                  << AVR32_SSC_TFMR_FSEDGE_OFFSET                              |
00289                   ((frame_bit_res - 1) >> AVR32_SSC_TFMR_FSLEN_SIZE) << AVR32_SSC_TFMR_FSLENHI_OFFSET;
00290 #endif
00291       txen_mask = AVR32_SSC_CR_TXEN_MASK;
00292     }
00293 
00294     /* If receiving data, set receiving clock register */
00295     if ( (mode != SSC_I2S_MODE_STEREO_OUT) && (mode != SSC_I2S_MODE_STEREO_OUT_EXT_CLK) )
00296     {
00297       // Possible states:
00298       // SSC_I2S_MODE_STEREO_OUT_MONO_IN,
00299       // SSC_I2S_MODE_RIGHT_IN,
00300       // SSC_I2S_MODE_STEREO_IN,
00301       // SSC_I2S_MODE_STEREO_OUT_STEREO_IN
00302 
00303       if ( (mode == SSC_I2S_MODE_STEREO_OUT_MONO_IN) || (mode == SSC_I2S_MODE_RIGHT_IN) )
00304       {
00305           /* Set receive clock mode:
00306            *  CKS - left ch uses TK, right (slave) uses RK pin
00307            *  CKO - No clock output,
00308            *  CKI - shift data on rising edge,
00309            *  CKG - No clock output,
00310            *  START - left ch starts when transmit starts, right starts on
00311            *          word-select (RF) rising edge
00312            *  STTDLY - RF toggles before last bit of last word, not before
00313            *           first bit on next word. Therefore, delay one cycle.
00314            *  PERIOD - No FS generation
00315            */
00316           ssc->rcmr =
00317             (( mode == SSC_I2S_MODE_RIGHT_IN ? AVR32_SSC_RCMR_CKS_RK_PIN : AVR32_SSC_RCMR_CKS_TK_CLOCK )
00318                                            << AVR32_SSC_RCMR_CKS_OFFSET)|
00319             (AVR32_SSC_RCMR_CKO_INPUT_ONLY << AVR32_SSC_RCMR_CKO_OFFSET)|
00320             (1                             << AVR32_SSC_RCMR_CKI_OFFSET)|
00321             (AVR32_SSC_RCMR_CKG_NONE       << AVR32_SSC_RCMR_CKG_OFFSET)|
00322             (( mode == SSC_I2S_MODE_RIGHT_IN ? AVR32_SSC_RCMR_START_DETECT_RISING_RF : AVR32_SSC_RCMR_START_TRANSMIT_START )
00323                                            << AVR32_SSC_RCMR_START_OFFSET)|
00324             (1                             << AVR32_SSC_RCMR_STTDLY_OFFSET)|
00325             (0                             << AVR32_SSC_RCMR_PERIOD_OFFSET);
00326 
00327           /* Set receive frame mode:
00328            *  DATLEN - bits per sample
00329            *  LOOP - no loopback
00330            *  MSBF - msb first
00331            *  DATNB - transmit one per sync
00332            *  FSLEN - no generate framesync
00333            *  FSOS - do not generate framesync
00334            *  FSEDGE - detect frame sync positive edge
00335            */
00336           ssc->rfmr =
00337             ((data_bit_res-1)               << AVR32_SSC_RFMR_DATLEN_OFFSET)|
00338             (0                              << AVR32_SSC_RFMR_LOOP_OFFSET)|
00339             (1                              << AVR32_SSC_RFMR_MSBF_OFFSET)|
00340             (0                              << AVR32_SSC_RFMR_DATNB_OFFSET)|
00341             (0                              << AVR32_SSC_RFMR_FSLEN_OFFSET)|
00342             (AVR32_SSC_RFMR_FSOS_INPUT_ONLY << AVR32_SSC_RFMR_FSOS_OFFSET)|
00343             (0                              << AVR32_SSC_RFMR_FSEDGE_OFFSET);
00344 
00345             rxen_mask = AVR32_SSC_CR_RXEN_MASK;
00346         }
00347         else
00348         {
00349             // Possible states:
00350             // SSC_I2S_MODE_STEREO_IN,
00351             // SSC_I2S_MODE_STEREO_OUT_STEREO_IN
00352 
00353             ssc->rcmr = AVR32_SSC_RCMR_CKS_TK_CLOCK               << AVR32_SSC_RCMR_CKS_OFFSET    |
00354                         AVR32_SSC_RCMR_CKO_CONTINOUS_CLOCK_OUTPUT << AVR32_SSC_RCMR_CKO_OFFSET    |
00355                         0                                         << AVR32_SSC_RCMR_CKI_OFFSET    |
00356                         AVR32_SSC_RCMR_CKG_NONE                   << AVR32_SSC_RCMR_CKG_OFFSET    |
00357                         AVR32_SSC_RCMR_START_DETECT_ANY_EDGE_RF   << AVR32_SSC_RCMR_START_OFFSET  |
00358                         1                                         << AVR32_SSC_RCMR_STTDLY_OFFSET |
00359                         (frame_bit_res - 1)                       << AVR32_SSC_RCMR_PERIOD_OFFSET;
00360 
00361 #ifdef AVR32_SSC_220_H_INCLUDED
00362             ssc->rfmr = (data_bit_res - 1)                                 << AVR32_SSC_RFMR_DATLEN_OFFSET                              |
00363                         1                                                  << AVR32_SSC_RFMR_MSBF_OFFSET                                |
00364                         (1 - 1)                                            << AVR32_SSC_RFMR_DATNB_OFFSET                               |
00365                         (((frame_bit_res - 1)                              << AVR32_SSC_RFMR_FSLEN_OFFSET) & AVR32_SSC_TFMR_FSLEN_MASK) |
00366                         AVR32_SSC_RFMR_FSOS_NEG_PULSE                      << AVR32_SSC_RFMR_FSOS_OFFSET                                |
00367                         1                                                  << AVR32_SSC_RFMR_FSEDGE_OFFSET;
00368 #else
00369             ssc->rfmr = (data_bit_res - 1)                                 << AVR32_SSC_RFMR_DATLEN_OFFSET                              |
00370                         1                                                  << AVR32_SSC_RFMR_MSBF_OFFSET                                |
00371                         (1 - 1)                                            << AVR32_SSC_RFMR_DATNB_OFFSET                               |
00372                         (((frame_bit_res - 1)                              << AVR32_SSC_RFMR_FSLEN_OFFSET) & AVR32_SSC_TFMR_FSLEN_MASK) |
00373                         AVR32_SSC_RFMR_FSOS_NEG_PULSE                      << AVR32_SSC_RFMR_FSOS_OFFSET                                |
00374                         1                                                  << AVR32_SSC_RFMR_FSEDGE_OFFSET                              |
00375                         ((frame_bit_res - 1) >> AVR32_SSC_RFMR_FSLEN_SIZE) << AVR32_SSC_RFMR_FSLENHI_OFFSET;
00376 #endif
00377             rxen_mask = AVR32_SSC_CR_RXEN_MASK;
00378         }
00379 
00380       }
00381     /* Enable transceiver and/or receiver */
00382     ssc->cr = txen_mask | rxen_mask;
00383   }
00384 
00385   return SSC_I2S_OK;
00386 }

void ssc_i2s_reset ( volatile avr32_ssc_t *  ssc  ) 

Resets the SSC module.

Parameters:
ssc pointer to the correct volatile avr32_ssc_t struct

Definition at line 82 of file ssc_i2s.c.

Referenced by ssc_i2s_init().

00083 {
00084   /* Software reset SSC */
00085   ssc->cr = AVR32_SSC_CR_SWRST_MASK;
00086 }

int ssc_i2s_transfer ( volatile avr32_ssc_t *  ssc,
unsigned int  data 
)

Transfers a single message of data.

Parameters:
ssc Pointer to the correct volatile avr32_ssc_t struct
data The data to transfer
Returns:
Status
Return values:
SSC_I2S_OK when no error occured.
SSC_I2S_TIMEOUT when a timeout occured while trying to transfer

Definition at line 389 of file ssc_i2s.c.

References SSC_I2S_OK, SSC_I2S_TIMEOUT, and SSC_I2S_TIMEOUT_VALUE.

Referenced by main().

00390 {
00391   unsigned int timeout = SSC_I2S_TIMEOUT_VALUE;
00392 
00393   while( ( ssc->sr & (1<<AVR32_SSC_SR_TXRDY_OFFSET) ) == 0 &&
00394       timeout > 0 ) {
00395     timeout--;
00396   }
00397 
00398   if( timeout <= 0 ) {
00399     return SSC_I2S_TIMEOUT;
00400   }
00401 
00402   ssc->thr = data;
00403 
00404   return SSC_I2S_OK;
00405 }


Generated on Fri Feb 19 02:26:28 2010 for AVR32 UC3 - SSC Driver for I²S by  doxygen 1.5.5