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00045 #include "dsp.h"
00046 #include "preprocessor.h"
00047
00048 #if !defined(FORCE_ALL_GENERICS) && \
00049 !defined(FORCE_GENERIC_OP16_LN) && \
00050 defined(TARGET_SPECIFIC_OP16_LN)
00051
00052 #if (defined __GNUC__)
00053 # define ASM_INSTRUCT_COMPACKED(str) str
00054 # define ASM_INSTRUCT_EXTENDED(str) str
00055 #elif __ICCAVR32__
00056 # define ASM_INSTRUCT_COMPACKED(str) str":C"
00057 # define ASM_INSTRUCT_EXTENDED(str) str":E"
00058 #endif
00059
00060
00061 #if (defined __GNUC__)
00062 # define CST_MIN "%[CST_MIN__]"
00063 # define CST_ONE "%[CST_ONE__]"
00064 # define CST_LESS_ONE "%[CST_LESS_ONE__]"
00065 # define CST_INV_NINE "%[CST_INV_NINE__]"
00066 # define CST_LESS_INV_SEVEN "%[CST_LESS_INV_SEVEN__]"
00067 # define CST_LESS_INV_FIVE "%[CST_LESS_INV_FIVE__]"
00068 # define CST_LESS_INV_THREE "%[CST_LESS_INV_THREE__]"
00069 # define CST_LN_TWO "%[CST_LN_TWO__]"
00070 #elif __ICCAVR32__
00071 # define CST_MIN ASTRINGZ(-1 << (DSP16_QA+DSP16_QB-1))
00072 # if DSP16_QB >= 15
00073 # define CST_ONE ASTRINGZ((1 << 15) - 1)
00074 # else
00075 # define CST_ONE ASTRINGZ(1 << DSP16_QB)
00076 # endif
00077 # define CST_LESS_ONE ASTRINGZ(-1 << DSP16_QB)
00078 # define CST_INV_NINE ASTRINGZ(0x00000E38 >> (DSP16_QA - 1))
00079 # define CST_LESS_INV_SEVEN ASTRINGZ(0xFFFFEDB7 >> (DSP16_QA - 1))
00080 # define CST_LESS_INV_FIVE ASTRINGZ(0xFFFFE667 >> (DSP16_QA - 1))
00081 # define CST_LESS_INV_THREE ASTRINGZ(0xFFFFD556 >> (DSP16_QA - 1))
00082 # define CST_LN_TWO ASTRINGZ(0x000058B9 >> (DSP16_QA - 1))
00083 #endif
00084
00085
00086
00088 #if (defined __GNUC__)
00089 __attribute__((__naked__))
00090 __attribute__((__noinline__))
00091 #elif __ICCAVR32__
00092 # pragma shadow_registers=full
00093 # pragma optimize=none no_inline
00094 #endif
00095 S32 dsp16_op_ln_raw(dsp16_t num)
00096 {
00097 __asm__ __volatile__ (
00098 "pushm r0-r3, lr\n\t"
00099
00100
00101 "cp.w r12, 0\n\t"
00102 ASM_INSTRUCT_COMPACKED("brlt __dsp16_sqrt_end_err")"\n\t"
00103
00104
00105 "clz r0, r12\n\t"
00106 "sub r0, r0, "ASTRINGZ(32 - DSP16_QB)"\n\t"
00107
00108
00109 "lsl r12, r12, r0\n\t"
00110
00111
00112 "sub r1, r12, "CST_ONE"\n\t"
00113 "lsl r1, r1, "ASTRINGZ(DSP16_QB)"\n\t"
00114 "sub r2, r12, "CST_LESS_ONE"\n\t"
00115
00116 "divs r2, r1, r2\n\t"
00117
00118
00119 "mul r1, r2, r2\n\t"
00120
00121 "asr r1, r1, "ASTRINGZ(DSP16_QB)"\n\t"
00122
00123
00124 "mov r3, "CST_INV_NINE"\n\t"
00125 "mul r3, r1, r3\n\t"
00126 "asr r3, r3, "ASTRINGZ(DSP16_QB)"\n\t"
00127
00128 "sub r3, r3, "CST_LESS_INV_SEVEN"\n\t"
00129 "mul r3, r1, r3\n\t"
00130 "asr r3, r3, "ASTRINGZ(DSP16_QB)"\n\t"
00131
00132 "sub r3, r3, "CST_LESS_INV_FIVE"\n\t"
00133 "mul r3, r1, r3\n\t"
00134 "asr r3, r3, "ASTRINGZ(DSP16_QB)"\n\t"
00135
00136 "sub r3, r3, "CST_LESS_INV_THREE"\n\t"
00137 "mul r3, r1, r3\n\t"
00138 "asr r3, r3, "ASTRINGZ(DSP16_QB)"\n\t"
00139
00140 "sub r3, r3, "CST_LESS_ONE"\n\t"
00141 "mul r3, r2, r3\n\t"
00142 "asr r3, r3, "ASTRINGZ(DSP16_QB - 1)"\n\t"
00143
00144
00145 "mov r1, "CST_LN_TWO"\n\t"
00146 "mul r0, r0, r1\n\t"
00147 "sub r12, r3, r0\n\t"
00148
00149 "__dsp16_sqrt_end_fct:\n\t"
00150 "popm r0-r3, pc\n"
00151
00152
00153 "__dsp16_sqrt_end_err:\n\t"
00154 "mov r12, "CST_MIN"\n\t"
00155 "popm r0-r3, pc\n\t"
00156 #if (defined __GNUC__)
00157 :
00158 :
00159 [CST_MIN__] "i" (DSP_Q_MIN(DSP16_QA, DSP16_QB)),
00160 [CST_ONE__] "i" (DSP16_Q(1.)),
00161 [CST_LESS_ONE__] "i" (DSP16_Q(-1.)),
00162 [CST_INV_NINE__] "i" (DSP16_Q(1./9.)),
00163 [CST_LESS_INV_SEVEN__] "i" (DSP16_Q(-1./7.)),
00164 [CST_LESS_INV_FIVE__] "i" (DSP16_Q(-1./5.)),
00165 [CST_LESS_INV_THREE__] "i" (DSP16_Q(-1./3.)),
00166 [CST_LN_TWO__] "i" (DSP16_Q(CST_LN_2))
00167 #endif
00168 );
00169
00170 return 0;
00171 }
00172
00173 #endif