Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:13.4 (WebPack) - O.87xd Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s500e
Project ID (random number) 11e796194aec441d874674c311111814.D24152BDF22D76739BA8D67D54F565BE.36 Target Package: pq208
Registration ID 201013689_0_0_430 Target Speed: -5
Date Generated 2012-05-18T08:09:59 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name AMD Phenom(tm) II X4 945 Processor CPU Speed 3007 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=4
  • 10-bit adder=1
  • 16-bit adder=2
  • 3-bit adder=1
Counters=33
  • 5-bit up counter=32
  • 8-bit up counter=1
Multiplexers=36
  • 1-bit 4-to-1 multiplexer=33
  • 16-bit 32-to-1 multiplexer=1
  • 16-bit 4-to-1 multiplexer=1
  • 16-bit 8-to-1 multiplexer=1
RAMs=34
  • 1024x16-bit dual-port block RAM=1
  • 16x16-bit dual-port distributed RAM=32
  • 2048x16-bit dual-port block RAM=1
ROMs=96
  • 16x1-bit ROM=64
  • 32x1-bit ROM=32
Registers=1964
  • Flip-Flops=1964
Xors=32
  • 1-bit xor2=32
MiscellaneousStatistics
  • AGG_BONDED_IO=98
  • AGG_IO=98
  • AGG_SLICE=3849
  • NUM_4_INPUT_LUT=6532
  • NUM_BONDED_IBUF=17
  • NUM_BONDED_IOB=81
  • NUM_BUFGMUX=1
  • NUM_CYMUX=45
  • NUM_DP_RAM=1024
  • NUM_LUT_RT=37
  • NUM_RAMB16=3
  • NUM_SLICEL=3273
  • NUM_SLICEM=576
  • NUM_SLICE_FF=1934
  • NUM_XOR=40
NetStatistics
  • NumNets_Active=6979
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=59
  • NumNodesOfType_Active_BRAMDUMMY=100
  • NumNodesOfType_Active_CLKPIN=2191
  • NumNodesOfType_Active_CNTRLPIN=2116
  • NumNodesOfType_Active_DOUBLE=20192
  • NumNodesOfType_Active_DUMMY=23394
  • NumNodesOfType_Active_DUMMYBANK=55
  • NumNodesOfType_Active_DUMMYESC=97
  • NumNodesOfType_Active_GLOBAL=245
  • NumNodesOfType_Active_HFULLHEX=340
  • NumNodesOfType_Active_HLONG=72
  • NumNodesOfType_Active_HUNIHEX=1839
  • NumNodesOfType_Active_INPUT=25706
  • NumNodesOfType_Active_IOBOUTPUT=97
  • NumNodesOfType_Active_OMUX=6034
  • NumNodesOfType_Active_OUTPUT=6737
  • NumNodesOfType_Active_PREBXBY=6275
  • NumNodesOfType_Active_VFULLHEX=1522
  • NumNodesOfType_Active_VLONG=349
  • NumNodesOfType_Active_VUNIHEX=1992
  • NumNodesOfType_Gnd_BRAMADDR=5
  • NumNodesOfType_Gnd_BRAMDUMMY=14
  • NumNodesOfType_Gnd_DOUBLE=16
  • NumNodesOfType_Gnd_DUMMYBANK=3
  • NumNodesOfType_Gnd_INPUT=25
  • NumNodesOfType_Gnd_OMUX=8
  • NumNodesOfType_Gnd_OUTPUT=9
  • NumNodesOfType_Gnd_PREBXBY=7
  • NumNodesOfType_Gnd_VFULLHEX=2
  • NumNodesOfType_Gnd_VLONG=1
  • NumNodesOfType_Gnd_VUNIHEX=1
  • NumNodesOfType_Vcc_BRAMDUMMY=6
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_INPUT=39
  • NumNodesOfType_Vcc_PREBXBY=33
  • NumNodesOfType_Vcc_VCCOUT=37
SiteStatistics
  • IBUF-DIFFM=6
  • IBUF-DIFFS=6
  • IOB-DIFFM=40
  • IOB-DIFFS=37
  • SLICEL-SLICEM=1372
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=17
  • IBUF_INBUF=17
  • IBUF_PAD=17
  • IOB=81
  • IOB_INBUF=80
  • IOB_OUTBUF=81
  • IOB_PAD=81
  • RAMB16=3
  • RAMB16_RAMB16=3
  • RAMB16_RAMB16A=3
  • RAMB16_RAMB16B=3
  • SLICEL=3273
  • SLICEL_C1VDD=3
  • SLICEL_CYMUXF=24
  • SLICEL_CYMUXG=21
  • SLICEL_F=2700
  • SLICEL_F5MUX=578
  • SLICEL_F6MUX=64
  • SLICEL_FFX=1000
  • SLICEL_FFY=934
  • SLICEL_G=2680
  • SLICEL_GNDF=21
  • SLICEL_GNDG=21
  • SLICEL_XORF=20
  • SLICEL_XORG=20
  • SLICEM=576
  • SLICEM_F=576
  • SLICEM_F5MUX=64
  • SLICEM_F6MUX=64
  • SLICEM_G=576
  • SLICEM_WSGEN=512
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:17]
IOB
  • O1=[O1_INV:0] [O1:81]
  • T1=[T1_INV:16] [T1:64]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:81]
  • TRI=[TRI_INV:16] [TRI:64]
IOB_PAD
  • DRIVEATTRBOX=[12:81]
  • IOATTRBOX=[LVCMOS25:81]
  • SLEW=[SLOW:81]
RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:3]
  • CLKB=[CLKB_INV:0] [CLKB:3]
  • ENA=[ENA_INV:0] [ENA:3]
  • ENB=[ENB_INV:0] [ENB:3]
  • SSRA=[SSRA_INV:0] [SSRA:3]
  • SSRB=[SSRB_INV:0] [SSRB:3]
  • WEA=[WEA:3] [WEA_INV:0]
  • WEB=[WEB:3] [WEB_INV:0]
RAMB16_RAMB16A
  • CLKA=[CLKA_INV:0] [CLKA:3]
  • ENA=[ENA_INV:0] [ENA:3]
  • PORTA_ATTR=[2048X9:2] [1024X18:1]
  • SSRA=[SSRA_INV:0] [SSRA:3]
  • WEA=[WEA:3] [WEA_INV:0]
  • WRITEMODEA=[WRITE_FIRST:1] [READ_FIRST:2]
RAMB16_RAMB16B
  • CLKB=[CLKB_INV:0] [CLKB:3]
  • ENB=[ENB_INV:0] [ENB:3]
  • PORTB_ATTR=[2048X9:2] [1024X18:1]
  • SSRB=[SSRB_INV:0] [SSRB:3]
  • WEB=[WEB:3] [WEB_INV:0]
  • WRITEMODEB=[WRITE_FIRST:3]
SLICEL
  • BX=[BX_INV:0] [BX:636]
  • BY=[BY:558] [BY_INV:1]
  • CE=[CE:210] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:20]
  • CLK=[CLK:1673] [CLK_INV:0]
  • SR=[SR:1169] [SR_INV:145]
SLICEL_CYMUXF
  • 0=[0:24] [0_INV:0]
  • 1=[1_INV:0] [1:24]
SLICEL_CYMUXG
  • 0=[0:21] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:578] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:64] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:145] [CE_INV:0]
  • CK=[CK:1000] [CK_INV:0]
  • D=[D:1000] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:931] [INIT1:69]
  • FFX_SR_ATTR=[SRLOW:931] [SRHIGH:69]
  • LATCH_OR_FF=[FF:1000]
  • REV=[REV_INV:0] [REV:4]
  • SR=[SR:844] [SR_INV:125]
  • SYNC_ATTR=[ASYNC:865] [SYNC:135]
SLICEL_FFY
  • CE=[CE:157] [CE_INV:0]
  • CK=[CK:934] [CK_INV:0]
  • D=[D:933] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:746] [INIT1:188]
  • FFY_SR_ATTR=[SRLOW:746] [SRHIGH:188]
  • LATCH_OR_FF=[FF:934]
  • REV=[REV_INV:0] [REV:2]
  • SR=[SR:460] [SR_INV:115]
  • SYNC_ATTR=[ASYNC:690] [SYNC:244]
SLICEL_XORF
  • 1=[1_INV:0] [1:20]
SLICEM
  • BX=[BX_INV:0] [BX:64]
  • BY=[BY:576] [BY_INV:0]
  • CLK=[CLK:512] [CLK_INV:0]
  • SR=[SR:512] [SR_INV:0]
SLICEM_F
  • DI=[DI:512] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:512]
  • LUT_OR_MEM=[LUT:64] [RAM:512]
SLICEM_F5MUX
  • S0=[S0:64] [S0_INV:0]
SLICEM_F6MUX
  • S0=[S0:64] [S0_INV:0]
SLICEM_G
  • DI=[DI:512] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:512]
  • LUT_OR_MEM=[LUT:64] [RAM:512]
SLICEM_WSGEN
  • CK=[CK:512] [CK_INV:0]
  • WE=[WE_INV:0] [WE:512]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=17
  • PAD=17
IBUF_INBUF
  • IN=17
  • OUT=17
IBUF_PAD
  • PAD=17
IOB
  • I=80
  • O1=81
  • PAD=81
  • T1=80
IOB_INBUF
  • IN=80
  • OUT=80
IOB_OUTBUF
  • IN=81
  • OUT=81
  • TRI=80
IOB_PAD
  • PAD=81
RAMB16
  • ADDRA10=3
  • ADDRA11=3
  • ADDRA12=3
  • ADDRA13=3
  • ADDRA3=2
  • ADDRA4=3
  • ADDRA5=3
  • ADDRA6=3
  • ADDRA7=3
  • ADDRA8=3
  • ADDRA9=3
  • ADDRB10=3
  • ADDRB11=3
  • ADDRB12=3
  • ADDRB13=3
  • ADDRB3=2
  • ADDRB4=3
  • ADDRB5=3
  • ADDRB6=3
  • ADDRB7=3
  • ADDRB8=3
  • ADDRB9=3
  • CLKA=3
  • CLKB=3
  • DIA0=3
  • DIA1=3
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA2=3
  • DIA3=3
  • DIA4=3
  • DIA5=3
  • DIA6=3
  • DIA7=3
  • DIA8=1
  • DIA9=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB2=1
  • DIB3=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=3
  • DIPA1=1
  • DIPB0=1
  • DIPB1=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOB0=3
  • DOB1=3
  • DOB10=1
  • DOB11=1
  • DOB12=1
  • DOB13=1
  • DOB14=1
  • DOB15=1
  • DOB2=3
  • DOB3=3
  • DOB4=3
  • DOB5=3
  • DOB6=3
  • DOB7=2
  • DOB8=1
  • DOB9=1
  • DOPB0=1
  • ENA=3
  • ENB=3
  • SSRA=3
  • SSRB=3
  • WEA=3
  • WEB=3
RAMB16_RAMB16
  • ADDRA=3
  • ADDRB=3
  • DIA=3
  • DIB=3
  • DOA=3
  • DOB=3
RAMB16_RAMB16A
  • ADDRA=3
  • ADDRA10=3
  • ADDRA11=3
  • ADDRA12=3
  • ADDRA13=3
  • ADDRA3=2
  • ADDRA4=3
  • ADDRA5=3
  • ADDRA6=3
  • ADDRA7=3
  • ADDRA8=3
  • ADDRA9=3
  • CLKA=3
  • DIA=3
  • DIA0=3
  • DIA1=3
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA2=3
  • DIA3=3
  • DIA4=3
  • DIA5=3
  • DIA6=3
  • DIA7=3
  • DIA8=1
  • DIA9=1
  • DIPA0=3
  • DIPA1=1
  • DOA=3
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • ENA=3
  • SSRA=3
  • WEA=3
RAMB16_RAMB16B
  • ADDRB=3
  • ADDRB10=3
  • ADDRB11=3
  • ADDRB12=3
  • ADDRB13=3
  • ADDRB3=2
  • ADDRB4=3
  • ADDRB5=3
  • ADDRB6=3
  • ADDRB7=3
  • ADDRB8=3
  • ADDRB9=3
  • CLKB=3
  • DIB=3
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB2=1
  • DIB3=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPB0=1
  • DIPB1=1
  • DOB=3
  • DOB0=3
  • DOB1=3
  • DOB10=1
  • DOB11=1
  • DOB12=1
  • DOB13=1
  • DOB14=1
  • DOB15=1
  • DOB2=3
  • DOB3=3
  • DOB4=3
  • DOB5=3
  • DOB6=3
  • DOB7=2
  • DOB8=1
  • DOB9=1
  • DOPB0=1
  • ENB=3
  • SSRB=3
  • WEB=3
SLICEL
  • BX=636
  • BY=559
  • CE=210
  • CIN=20
  • CLK=1673
  • COUT=21
  • F1=2700
  • F2=2680
  • F3=2292
  • F4=1815
  • F5=96
  • FX=32
  • FXINA=64
  • FXINB=64
  • G1=2680
  • G2=2660
  • G3=2255
  • G4=1831
  • SR=1314
  • X=1741
  • XQ=1000
  • Y=1759
  • YQ=934
SLICEL_C1VDD
  • 1=3
SLICEL_CYMUXF
  • 0=24
  • 1=24
  • OUT=24
  • S0=24
SLICEL_CYMUXG
  • 0=21
  • 1=21
  • OUT=21
  • S0=21
SLICEL_F
  • A1=2700
  • A2=2680
  • A3=2292
  • A4=1815
  • D=2700
SLICEL_F5MUX
  • F=578
  • G=578
  • OUT=578
  • S0=578
SLICEL_F6MUX
  • 0=64
  • 1=64
  • OUT=64
  • S0=64
SLICEL_FFX
  • CE=145
  • CK=1000
  • D=1000
  • Q=1000
  • REV=4
  • SR=969
SLICEL_FFY
  • CE=157
  • CK=934
  • D=934
  • Q=934
  • REV=2
  • SR=575
SLICEL_G
  • A1=2680
  • A2=2660
  • A3=2255
  • A4=1831
  • D=2680
SLICEL_GNDF
  • 0=21
SLICEL_GNDG
  • 0=21
SLICEL_XORF
  • 0=20
  • 1=20
  • O=20
SLICEL_XORG
  • 0=20
  • 1=20
  • O=20
SLICEM
  • BX=64
  • BY=576
  • CLK=512
  • F1=576
  • F2=576
  • F3=576
  • F4=512
  • F5=64
  • FX=64
  • FXINA=64
  • FXINB=64
  • G1=576
  • G2=576
  • G3=576
  • G4=512
  • SR=512
  • X=512
  • Y=512
SLICEM_F
  • A1=576
  • A2=576
  • A3=576
  • A4=512
  • D=576
  • DI=512
  • WF1=512
  • WF2=512
  • WF3=512
  • WF4=512
  • WS=512
SLICEM_F5MUX
  • F=64
  • G=64
  • OUT=64
  • S0=64
SLICEM_F6MUX
  • 0=64
  • 1=64
  • OUT=64
  • S0=64
SLICEM_G
  • A1=576
  • A2=576
  • A3=576
  • A4=512
  • D=576
  • DI=512
  • WG1=512
  • WG2=512
  • WG3=512
  • WG4=512
  • WS=512
SLICEM_WSGEN
  • CK=512
  • WE=512
  • WSF=512
  • WSG=512
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-pq208-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-pq208-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 36 35 0 0 0 0 0
map 39 39 0 0 0 0 0
netgen 1 1 0 0 0 0 0
ngdbuild 39 39 0 0 0 0 0
par 39 38 0 0 0 0 0
trce 37 37 0 0 0 0 0
xst 121 120 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/ite_c_overview.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/toplevel_test
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserBrowsedStrategyFiles=/home/jonemil/Xilinx/13.4/ISE_DS/ISE/data/default.xds PROP_intProjectCreationTimestamp=2012-02-06T17:12:59
PROP_intWbtProjectID=D24152BDF22D76739BA8D67D54F565BE PROP_intWbtProjectIteration=36
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_selectedSimRootSourceNode_behav=work.toplevel_test
PROP_xilxBitgCfg_GenOpt_ASCIIFile=true PROP_xilxBitgCfg_GenOpt_BitFile=false
PROP_AutoTop=false PROP_CompxlibEdkSimLib=true
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s500e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=pq208
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-5
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VHDL=29
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=358 NGDBUILD_NUM_FDC=1101 NGDBUILD_NUM_FDCE=64
NGDBUILD_NUM_FDE=32 NGDBUILD_NUM_FDR=41 NGDBUILD_NUM_FDRE=75 NGDBUILD_NUM_FDRS=3
NGDBUILD_NUM_FDRSE=3 NGDBUILD_NUM_FDS=129 NGDBUILD_NUM_FDSE=128 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=16 NGDBUILD_NUM_INV=6 NGDBUILD_NUM_IOBUF=80 NGDBUILD_NUM_LUT1=36
NGDBUILD_NUM_LUT2=777 NGDBUILD_NUM_LUT2_D=29 NGDBUILD_NUM_LUT2_L=4 NGDBUILD_NUM_LUT3=1000
NGDBUILD_NUM_LUT3_D=12 NGDBUILD_NUM_LUT3_L=1 NGDBUILD_NUM_LUT4=2751 NGDBUILD_NUM_LUT4_D=47
NGDBUILD_NUM_LUT4_L=848 NGDBUILD_NUM_MUXCY=45 NGDBUILD_NUM_MUXF5=642 NGDBUILD_NUM_MUXF6=80
NGDBUILD_NUM_MUXF7=32 NGDBUILD_NUM_MUXF8=16 NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_RAM16X1D=512
NGDBUILD_NUM_RAMB16_S18_S18=1 NGDBUILD_NUM_RAMB16_S9_S9=2 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=40
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=358 NGDBUILD_NUM_FDC=1101 NGDBUILD_NUM_FDCE=64
NGDBUILD_NUM_FDE=32 NGDBUILD_NUM_FDR=41 NGDBUILD_NUM_FDRE=75 NGDBUILD_NUM_FDRS=3
NGDBUILD_NUM_FDRSE=3 NGDBUILD_NUM_FDS=129 NGDBUILD_NUM_FDSE=128 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=96 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=6 NGDBUILD_NUM_LUT1=36
NGDBUILD_NUM_LUT2=777 NGDBUILD_NUM_LUT2_D=29 NGDBUILD_NUM_LUT2_L=4 NGDBUILD_NUM_LUT3=1000
NGDBUILD_NUM_LUT3_D=12 NGDBUILD_NUM_LUT3_L=1 NGDBUILD_NUM_LUT4=2751 NGDBUILD_NUM_LUT4_D=47
NGDBUILD_NUM_LUT4_L=848 NGDBUILD_NUM_MUXCY=45 NGDBUILD_NUM_MUXF5=642 NGDBUILD_NUM_MUXF6=80
NGDBUILD_NUM_MUXF7=32 NGDBUILD_NUM_MUXF8=16 NGDBUILD_NUM_OBUF=1 NGDBUILD_NUM_OBUFT=80
NGDBUILD_NUM_RAMB16_S18_S18=1 NGDBUILD_NUM_RAMB16_S9_S9=2 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=40
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s500e-5-pq208 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=ieee
Fuse Resource Usage=1871 ms, 37856 KB
Total Signals=4877
Total Nets=49237
Total Blocks=657
Total Processes=1312
Total Simulation Time=1293 us
Simulation Resource Usage=26.8322 sec, 542167 KB
Simulation Mode=gui
Hardware CoSim=0