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00048 #include "power_clocks_lib.h"
00049
00050
00052 #if UC3L
00053 static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param);
00054 #endif
00055
00056 #if UC3C
00057 static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param);
00058 #endif
00059
00060 long int pcl_configure_clocks(pcl_freq_param_t *param)
00061 {
00062 #ifndef AVR32_PM_VERSION_RESETVALUE
00063
00064 return(pm_configure_clocks(param));
00065 #else
00066 #ifdef AVR32_PM_410_H_INCLUDED
00067
00068 return(pcl_configure_clocks_uc3c(param));
00069 #else
00070
00071 return(pcl_configure_clocks_uc3l(param));
00072 #endif
00073 #endif
00074 }
00075
00076
00078 #if UC3L
00079
00080 static long int pcl_configure_synchronous_clocks( pm_clk_src_t main_clk_src,
00081 unsigned long main_clock_freq_hz,
00082 pcl_freq_param_t *param);
00083
00084 long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param)
00085 {
00086
00087
00088
00089
00090
00091
00092
00093
00094 #ifdef AVR32SFW_INPUT_CHECK
00095
00096 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00097 return(-1);
00098 #endif
00099
00100 #ifdef AVR32SFW_INPUT_CHECK
00101
00102 if((param->cpu_f > SCIF_SLOWCLOCK_FREQ_HZ) || (param->pba_f > SCIF_SLOWCLOCK_FREQ_HZ)
00103 || (param->pbb_f > SCIF_SLOWCLOCK_FREQ_HZ))
00104 return(-1);
00105 #endif
00106
00107 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_SLOW, SCIF_SLOWCLOCK_FREQ_HZ, param));
00108 }
00109
00110
00111 long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param)
00112 {
00113
00114
00115
00116
00117
00118
00119
00120
00121 #ifdef AVR32SFW_INPUT_CHECK
00122
00123 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00124 return(-1);
00125 #endif
00126
00127 #ifdef AVR32SFW_INPUT_CHECK
00128
00129 if((param->cpu_f > SCIF_RC120M_FREQ_HZ) || (param->pba_f > SCIF_RC120M_FREQ_HZ)
00130 || (param->pbb_f > SCIF_RC120M_FREQ_HZ))
00131 return(-1);
00132 #endif
00133
00134
00135 scif_start_rc120M();
00136
00137 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, param));
00138 }
00139
00140
00141 long int pcl_configure_clocks_osc0(pcl_freq_param_t *param)
00142 {
00143
00144
00145
00146
00147
00148
00149
00150
00151
00152 unsigned long main_clock_freq;
00153
00154
00155 #ifdef AVR32SFW_INPUT_CHECK
00156
00157 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00158 return(-1);
00159 #endif
00160
00161 main_clock_freq = param->osc0_f;
00162 #ifdef AVR32SFW_INPUT_CHECK
00163
00164 if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
00165 || (param->pbb_f > main_clock_freq))
00166 return(-1);
00167 #endif
00168
00169 scif_configure_osc_crystalmode(SCIF_OSC0, main_clock_freq);
00170
00171 scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
00172
00173 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_OSC0, main_clock_freq, param));
00174 }
00175
00176
00177 long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param)
00178 {
00179
00180
00181
00182
00183
00184
00185
00186
00187
00188 unsigned long main_clock_freq;
00189 scif_gclk_opt_t *pgc_dfllif_ref_opt;
00190
00191
00192 #ifdef AVR32SFW_INPUT_CHECK
00193
00194 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00195 return(-1);
00196 #endif
00197
00198 main_clock_freq = param->dfll_f;
00199 #ifdef AVR32SFW_INPUT_CHECK
00200
00201 if((main_clock_freq > SCIF_DFLL_MAXFREQ_HZ) || (main_clock_freq < SCIF_DFLL_MINFREQ_HZ))
00202 return(-1);
00203
00204 if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
00205 || (param->pbb_f > main_clock_freq))
00206 return(-1);
00207 #endif
00208 pgc_dfllif_ref_opt = (scif_gclk_opt_t *)param->pextra_params;
00209
00210
00211
00212 scif_dfll0_closedloop_configure_and_start(pgc_dfllif_ref_opt, main_clock_freq, TRUE);
00213
00214 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_DFLL0, main_clock_freq, param));
00215 }
00216
00217
00218 static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param)
00219 {
00220
00221
00222
00223
00224
00225
00226
00227
00228
00229
00230
00231
00232
00233
00234
00235
00236
00237
00238
00239
00240 #ifdef AVR32SFW_INPUT_CHECK
00241
00242 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00243 return(-1);
00244 #endif
00245
00246 if(PCL_MC_RCSYS == param->main_clk_src)
00247 {
00248 return(pcl_configure_clocks_rcsys(param));
00249 }
00250 else if(PCL_MC_RC120M == param->main_clk_src)
00251 {
00252 return(pcl_configure_clocks_rc120m(param));
00253 }
00254 else if(PCL_MC_OSC0 == param->main_clk_src)
00255 {
00256 return(pcl_configure_clocks_osc0(param));
00257 }
00258 else
00259 {
00260 return(pcl_configure_clocks_dfll0(param));
00261 }
00262 }
00263
00264 static long int pcl_configure_synchronous_clocks(pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param)
00265 {
00266
00267
00268
00269 pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f);
00270
00271
00272
00273
00274 #if UC3L
00275 flashcdw_set_flash_waitstate_and_readmode(param->cpu_f);
00276 #elif UC3C
00277 flashc_set_flash_waitstate_and_readmode(param->cpu_f);
00278 #endif
00279
00280
00281
00282
00283
00284 pm_set_mclk_source(main_clk_src);
00285
00286 return PASS;
00287 }
00288
00289 #endif // UC3L device-specific implementation
00290
00292 #if UC3C
00293 static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param)
00294 {
00295 #define PM_MAX_MUL ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1)
00296 #define AVR32_PM_PBA_MAX_FREQ 66000000
00297 #define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ 240000000
00298 #define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ 160000000
00299
00300
00301
00302
00303
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00305
00306
00307
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00309
00310
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00313
00314
00315 unsigned long in_cpu_f = param->cpu_f;
00316 unsigned long in_osc0_f = param->osc0_f;
00317 unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
00318 unsigned long pll_freq, rest;
00319 Bool b_div2_pba, b_div2_cpu;
00320
00321
00322 scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f);
00323
00324 scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
00325
00326 pm_set_mclk_source(PM_CLK_SRC_OSC0);
00327
00328
00329 if (in_cpu_f == in_osc0_f)
00330 {
00331 param->cpu_f = in_osc0_f;
00332 param->pba_f = in_osc0_f;
00333 return PASS;
00334 }
00335 else if (in_cpu_f < in_osc0_f)
00336 {
00337
00338 }
00339
00340 rest = in_cpu_f % in_osc0_f;
00341
00342 for (div = 1; div < 32; div++)
00343 {
00344 if ((div * rest) % in_osc0_f == 0)
00345 break;
00346 }
00347 if (div == 32)
00348 return FAIL;
00349
00350 mul = (in_cpu_f * div) / in_osc0_f;
00351
00352 if (mul > PM_MAX_MUL)
00353 return FAIL;
00354
00355
00356 while (!(div % 2))
00357 {
00358 div /= 2;
00359 div2_cpu++;
00360 }
00361
00362
00363
00364
00365
00366 while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
00367 {
00368 if (2 * mul > PM_MAX_MUL)
00369 break;
00370 mul *= 2;
00371 div2_cpu++;
00372 }
00373
00374 if (div2_cpu != 0)
00375 {
00376 div2_cpu--;
00377 div2_en = 1;
00378 }
00379
00380 pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
00381
00382
00383 param->cpu_f = pll_freq / (1 << div2_cpu);
00384 mul--;
00385
00386 scif_pll_opt_t opt;
00387
00388 opt.osc = SCIF_OSC0,
00389 opt.lockcount = 16,
00390 opt.div = div,
00391 opt.mul = mul,
00392 opt.pll_div2 = div2_en,
00393 opt.pll_wbwdisable = 0,
00394 opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0,
00395
00396
00397 scif_pll_setup(SCIF_PLL0, opt);
00398
00399
00400 scif_pll_enable(SCIF_PLL0);
00401
00402
00403 scif_wait_for_pll_locked(SCIF_PLL0) ;
00404
00405 rest = pll_freq;
00406 while (rest > AVR32_PM_PBA_MAX_FREQ ||
00407 rest != param->pba_f)
00408 {
00409 div2_pba++;
00410 rest = pll_freq / (1 << div2_pba);
00411 if (rest < param->pba_f)
00412 break;
00413 }
00414
00415
00416 param->pba_f = pll_freq / (1 << div2_pba);
00417
00418
00419 if (div2_cpu)
00420 {
00421 b_div2_cpu = TRUE;
00422 div2_cpu--;
00423 }
00424 else
00425 b_div2_cpu = FALSE;
00426
00427 if (div2_pba)
00428 {
00429 b_div2_pba = TRUE;
00430 div2_pba--;
00431 }
00432 else
00433 b_div2_pba = FALSE;
00434
00435 if (b_div2_cpu == TRUE )
00436 {
00437 pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu);
00438 pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu);
00439 pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu);
00440 }
00441 if (b_div2_pba == TRUE )
00442 {
00443 pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba);
00444 pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba);
00445 }
00446
00447
00448 flashc_set_flash_waitstate_and_readmode(param->cpu_f);
00449
00450
00451 pm_set_mclk_source(PM_CLK_SRC_PLL0);
00452
00453 return PASS;
00454 }
00455 #endif // UC3C device-specific implementation
00456
00457 long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup)
00458 {
00459 #ifndef AVR32_PM_VERSION_RESETVALUE
00460
00461 if(PCL_OSC0 == osc)
00462 {
00463
00464
00465 pm_switch_to_osc0(&AVR32_PM, fcrystal, startup);
00466 }
00467 else
00468 {
00469 return PCL_NOT_SUPPORTED;
00470 }
00471 #else
00472
00473 #if AVR32_PM_VERSION_RESETVALUE < 0x400
00474 return PCL_NOT_SUPPORTED;
00475 #else
00476 if(PCL_OSC0 == osc)
00477 {
00478
00479 scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal);
00480
00481 scif_enable_osc(SCIF_OSC0, startup, true);
00482
00483 #if UC3L
00484 flashcdw_set_flash_waitstate_and_readmode(fcrystal);
00485 #elif UC3C
00486 flashc_set_flash_waitstate_and_readmode(fcrystal);
00487 #endif
00488
00489 pm_set_mclk_source(PM_CLK_SRC_OSC0);
00490 }
00491 else
00492 {
00493 return PCL_NOT_SUPPORTED;
00494 }
00495 #endif
00496 #endif
00497 return PASS;
00498 }
00499
00500 long int pcl_configure_usb_clock(void)
00501 {
00502 #ifndef AVR32_PM_VERSION_RESETVALUE
00503
00504 pm_configure_usb_clock();
00505 return PASS;
00506 #else
00507 #ifdef AVR32_PM_410_H_INCLUDED
00508 const scif_pll_opt_t opt = {
00509 .osc = SCIF_OSC0,
00510 .lockcount = 16,
00511 .div = 1,
00512 .mul = 5,
00513 .pll_div2 = 1,
00514 .pll_wbwdisable = 0,
00515 .pll_freq = 1,
00516 };
00517
00518
00519 scif_pll_setup(SCIF_PLL1, opt);
00520
00521
00522 scif_pll_enable(SCIF_PLL1);
00523
00524
00525 scif_wait_for_pll_locked(SCIF_PLL1) ;
00526
00527
00528
00529 scif_gc_setup(AVR32_SCIF_GCLK_USB,
00530 SCIF_GCCTRL_PLL1,
00531 AVR32_SCIF_GC_NO_DIV_CLOCK,
00532 0);
00533
00534 scif_gc_enable(AVR32_SCIF_GCLK_USB);
00535 return PASS;
00536 #else
00537 return PCL_NOT_SUPPORTED;
00538 #endif
00539 #endif
00540 }
00541
00542
00543 #if UC3L
00544 #else
00545 void pcl_write_gplp(unsigned long gplp, unsigned long value)
00546 {
00547 #ifndef AVR32_PM_VERSION_RESETVALUE
00548
00549 pm_write_gplp(&AVR32_PM,gplp,value);
00550 #else
00551 scif_write_gplp(gplp,value);
00552 #endif
00553 }
00554
00555 unsigned long pcl_read_gplp(unsigned long gplp)
00556 {
00557 #ifndef AVR32_PM_VERSION_RESETVALUE
00558
00559 return pm_read_gplp(&AVR32_PM,gplp);
00560 #else
00561 return scif_read_gplp(gplp);
00562 #endif
00563 }
00564 #endif