scif_uc3c.c File Reference


Detailed Description

System Control InterFace(SCIF) driver.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file scif_uc3c.c.

#include "compiler.h"
#include "scif_uc3c.h"

Go to the source code of this file.

Data Structures

union  u_avr32_scif_oscctrl32_t
union  u_avr32_scif_oscctrl_t
union  u_avr32_scif_pll_t

Functions

void scif_bod18_clear_irq (void)
 Clears the 1.8V Brown-Out Detector interrupt flag.
void scif_bod18_disable_irq (void)
 Disables the 1.8V Brown-Out Detector interrupt.
void scif_bod18_enable_irq (void)
 Enables the 1.8V Brown-Out Detector interrupt.
unsigned long scif_bod18_get_irq_enable_bit (void)
 Gets the 1.8V Brown-Out Detector interrupt enable status.
unsigned long scif_bod18_get_irq_status (void)
 Gets the 1.8V Brown-Out Detector interrupt flag.
unsigned long scif_bod18_get_level (void)
 Gets the triggering threshold of the 1.8V Brown-Out Detector.
void scif_bod33_clear_irq (void)
 Clears the 3.3V Brown-Out Detector interrupt flag.
void scif_bod33_disable_irq (void)
 Disables the 3.3V Brown-Out Detector interrupt.
void scif_bod33_enable_irq (void)
 Enables the 3.3V Brown-Out Detector interrupt.
unsigned long scif_bod33_get_irq_enable_bit (void)
 Gets the 3.3V Brown-Out Detector interrupt enable status.
unsigned long scif_bod33_get_irq_status (void)
 Gets the 3.3V Brown-Out Detector interrupt flag.
unsigned long scif_bod33_get_level (void)
 Gets the triggering threshold of the 3.3V Brown-Out Detector.
void scif_bod50_clear_irq (void)
 Clears the 5.0V Brown-Out Detector interrupt flag.
void scif_bod50_disable_irq (void)
 Disables the 5.0V Brown-Out Detector interrupt.
void scif_bod50_enable_irq (void)
 Enables the 5.0V Brown-Out Detector interrupt.
unsigned long scif_bod50_get_irq_enable_bit (void)
 Gets the 5.0V Brown-Out Detector interrupt enable status.
unsigned long scif_bod50_get_irq_status (void)
 Gets the 5.0V Brown-Out Detector interrupt flag.
unsigned long scif_bod50_get_level (void)
 Gets the triggering threshold of the 5.0V Brown-Out Detector.
long int scif_configure_osc_crystalmode (scif_osc_t osc, unsigned int fcrystal)
 Configure an oscillator in crystal mode.
long int scif_configure_osc_extmode (scif_osc_t osc)
 Configure an external clock as input clock.
long int scif_enable_extosc (scif_osc_t osc)
 Enable external clock.
long int scif_enable_osc (scif_osc_t osc, unsigned int startup, bool wait_for_ready)
 Enable an oscillator with a given startup time.
long int scif_gc_enable (unsigned int gclk)
 Enable a generic clock.
long int scif_gc_setup (unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor)
 Setup a generic clock.
bool scif_is_osc_ready (scif_osc_t osc)
 Is an oscillator stable and ready to be used as clock source?
static long int scif_pclksr_statushigh_wait (unsigned long statusMask)
 Wait for a status high in the Power and Clocks status register.
long int scif_pll_disable (scif_pll_t pll)
 This function will disable a PLL.
long int scif_pll_enable (scif_pll_t pll)
 This function will enable a PLL.
long int scif_pll_setup (scif_pll_t pll, const scif_pll_opt_t opt)
 PLL0/PLL1 Functions.
unsigned long scif_read_gplp (unsigned long gplp)
 Read the content of the SCIF GPLP registers.
long int scif_start_gclk (unsigned int gclk, const scif_gclk_opt_t *opt)
 Generic Clock Functions.
long int scif_start_osc (scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready)
 Interrupt Functions.
long int scif_start_osc32 (const scif_osc32_opt_t *opt, bool wait_for_ready)
 OSC32 Functions.
void scif_start_rc120M (void)
 120MHz RCosc Functions
void scif_start_rc8M (void)
 Calibration Functions.
long int scif_stop_gclk (unsigned int gclk)
 Stop a generic clock.
long int scif_stop_osc (scif_osc_t osc)
 Stop an oscillator.
long scif_stop_osc32 ()
 Stop the OSC32 oscillator.
void scif_stop_rc120M (void)
 Stop the 120MHz internal RCosc (RC120M) clock.
void scif_stop_rc8M (void)
 Stop the 8MHz internal RCosc (RC8M) clock.
long int scif_wait_for_pll_locked (scif_pll_t pll)
 This function will wait for PLL locked.
void scif_write_gplp (int gplp, unsigned long value)
 Write into the SCIF GPLP registers.


Function Documentation

void scif_bod18_clear_irq ( void   ) 

Clears the 1.8V Brown-Out Detector interrupt flag.

Definition at line 695 of file scif_uc3c.c.

00696 {
00697   AVR32_SCIF.icr = AVR32_SCIF_ICR_BODDET_MASK;
00698 }

void scif_bod18_disable_irq ( void   ) 

Disables the 1.8V Brown-Out Detector interrupt.

Definition at line 685 of file scif_uc3c.c.

00686 {
00687   Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00688 
00689   if (global_interrupt_enabled) Disable_global_interrupt();
00690   AVR32_SCIF.idr = AVR32_SCIF_IDR_BODDET_MASK;
00691   AVR32_SCIF.isr;
00692   if (global_interrupt_enabled) Enable_global_interrupt();
00693 }

void scif_bod18_enable_irq ( void   ) 

Enables the 1.8V Brown-Out Detector interrupt.

Definition at line 680 of file scif_uc3c.c.

00681 {
00682   AVR32_SCIF.ier = AVR32_SCIF_IER_BODDET_MASK ;
00683 }

unsigned long scif_bod18_get_irq_enable_bit ( void   ) 

Gets the 1.8V Brown-Out Detector interrupt enable status.

Return values:
0 BOD interrupt disabled.
1 BOD interrupt enabled.

Definition at line 705 of file scif_uc3c.c.

00706 {
00707   return ((AVR32_SCIF.imr & AVR32_SCIF_IMR_BODDET_MASK) != 0);
00708 }

unsigned long scif_bod18_get_irq_status ( void   ) 

Gets the 1.8V Brown-Out Detector interrupt flag.

Return values:
0 No BOD interrupt.
1 BOD interrupt pending.

Definition at line 700 of file scif_uc3c.c.

00701 {
00702   return ((AVR32_SCIF.isr & AVR32_SCIF_ISR_BODDET_MASK) != 0);
00703 }

unsigned long scif_bod18_get_level ( void   ) 

Gets the triggering threshold of the 1.8V Brown-Out Detector.

Definition at line 710 of file scif_uc3c.c.

00711 {
00712   return (AVR32_SCIF.bod & AVR32_SCIF_BOD_LEVEL_MASK) >> AVR32_SCIF_BOD_LEVEL_OFFSET;
00713 }

void scif_bod33_clear_irq ( void   ) 

Clears the 3.3V Brown-Out Detector interrupt flag.

Definition at line 730 of file scif_uc3c.c.

00731 {
00732   AVR32_SCIF.icr = AVR32_SCIF_ICR_BOD33DET_MASK;
00733 }

void scif_bod33_disable_irq ( void   ) 

Disables the 3.3V Brown-Out Detector interrupt.

Definition at line 720 of file scif_uc3c.c.

00721 {
00722    Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00723 
00724   if (global_interrupt_enabled) Disable_global_interrupt();
00725   AVR32_SCIF.idr = AVR32_SCIF_IDR_BOD33DET_MASK;
00726   AVR32_SCIF.isr;
00727   if (global_interrupt_enabled) Enable_global_interrupt();
00728 }

void scif_bod33_enable_irq ( void   ) 

Enables the 3.3V Brown-Out Detector interrupt.

Definition at line 715 of file scif_uc3c.c.

00716 {
00717   AVR32_SCIF.ier = AVR32_SCIF_IER_BOD33DET_MASK ;
00718 }

unsigned long scif_bod33_get_irq_enable_bit ( void   ) 

Gets the 3.3V Brown-Out Detector interrupt enable status.

Return values:
0 BOD interrupt disabled.
1 BOD interrupt enabled.

Definition at line 740 of file scif_uc3c.c.

00741 {
00742   return ((AVR32_SCIF.imr & AVR32_SCIF_IMR_BOD33DET_MASK) != 0);
00743 }

unsigned long scif_bod33_get_irq_status ( void   ) 

Gets the 3.3V Brown-Out Detector interrupt flag.

Return values:
0 No BOD interrupt.
1 BOD interrupt pending.

Definition at line 735 of file scif_uc3c.c.

00736 {
00737   return ((AVR32_SCIF.isr & AVR32_SCIF_ISR_BOD33DET_MASK) != 0);
00738 }

unsigned long scif_bod33_get_level ( void   ) 

Gets the triggering threshold of the 3.3V Brown-Out Detector.

Definition at line 745 of file scif_uc3c.c.

00746 {
00747   return (AVR32_SCIF.bod33 & AVR32_SCIF_BOD33_LEVEL_MASK) >> AVR32_SCIF_BOD33_LEVEL_OFFSET;
00748 }

void scif_bod50_clear_irq ( void   ) 

Clears the 5.0V Brown-Out Detector interrupt flag.

Definition at line 765 of file scif_uc3c.c.

00766 {
00767   AVR32_SCIF.icr = AVR32_SCIF_ICR_BOD50DET_MASK;
00768 }

void scif_bod50_disable_irq ( void   ) 

Disables the 5.0V Brown-Out Detector interrupt.

Definition at line 755 of file scif_uc3c.c.

00756 {
00757    Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00758 
00759   if (global_interrupt_enabled) Disable_global_interrupt();
00760   AVR32_SCIF.idr = AVR32_SCIF_IDR_BOD50DET_MASK;
00761   AVR32_SCIF.isr;
00762   if (global_interrupt_enabled) Enable_global_interrupt();
00763 }

void scif_bod50_enable_irq ( void   ) 

Enables the 5.0V Brown-Out Detector interrupt.

Definition at line 750 of file scif_uc3c.c.

00751 {
00752   AVR32_SCIF.ier = AVR32_SCIF_IER_BOD50DET_MASK ;
00753 }

unsigned long scif_bod50_get_irq_enable_bit ( void   ) 

Gets the 5.0V Brown-Out Detector interrupt enable status.

Return values:
0 BOD interrupt disabled.
1 BOD interrupt enabled.

Definition at line 775 of file scif_uc3c.c.

00776 {
00777   return ((AVR32_SCIF.imr & AVR32_SCIF_IMR_BOD50DET_MASK) != 0);
00778 }

unsigned long scif_bod50_get_irq_status ( void   ) 

Gets the 5.0V Brown-Out Detector interrupt flag.

Return values:
0 No BOD interrupt.
1 BOD interrupt pending.

Definition at line 770 of file scif_uc3c.c.

00771 {
00772   return ((AVR32_SCIF.isr & AVR32_SCIF_ISR_BOD50DET_MASK) != 0);
00773 }

unsigned long scif_bod50_get_level ( void   ) 

Gets the triggering threshold of the 5.0V Brown-Out Detector.

Definition at line 780 of file scif_uc3c.c.

00781 {
00782   return (AVR32_SCIF.bod50 & AVR32_SCIF_BOD50_LEVEL_MASK) >> AVR32_SCIF_BOD50_LEVEL_OFFSET;
00783 }

long int scif_configure_osc_crystalmode ( scif_osc_t  osc,
unsigned int  fcrystal 
)

Configure an oscillator in crystal mode.

Parameters:
osc The oscillator to configure [INPUT]
fcrystal Crystal frequency (Hz) [INPUT]
Returns:
Status.
Return values:
0 Oscillator successfully configured.
<0 Error configuring the oscillator.

Definition at line 228 of file scif_uc3c.c.

00229 {
00230   u_avr32_scif_oscctrl_t   u_avr32_scif_oscctrl;
00231   
00232   if (osc == SCIF_OSC0)
00233   {    
00234     // Read Register
00235     u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0] = AVR32_SCIF.OSCCTRL[SCIF_OSC0] ;    
00236     // Modify : Configure the oscillator mode to crystal and set the gain according to the
00237     // cyrstal frequency.
00238     u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
00239     u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].gain = (fcrystal <  900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
00240                                                    (fcrystal < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
00241                                                    (fcrystal < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
00242                                                                           AVR32_SCIF_OSCCTRL0_GAIN_G3;
00243     AVR32_ENTER_CRITICAL_REGION( );
00244     // Unlock the write-protected OSCCTRL0 register
00245     SCIF_UNLOCK(AVR32_SCIF_OSCCTRL);
00246     // Write Back
00247     AVR32_SCIF.OSCCTRL[SCIF_OSC0] = u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0];
00248     AVR32_LEAVE_CRITICAL_REGION( );
00249   }
00250   else
00251   { 
00252     // Read Register
00253     u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1] = AVR32_SCIF.OSCCTRL[SCIF_OSC1] ;    
00254     // Modify : Configure the oscillator mode to crystal and set the gain according to the
00255     // cyrstal frequency.
00256     u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1].mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
00257     u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1].gain = (fcrystal <  900000) ? AVR32_SCIF_OSCCTRL1_GAIN_G0 :
00258                                                    (fcrystal < 3000000) ? AVR32_SCIF_OSCCTRL1_GAIN_G1 :
00259                                                    (fcrystal < 8000000) ? AVR32_SCIF_OSCCTRL1_GAIN_G2 :
00260                                                                           AVR32_SCIF_OSCCTRL1_GAIN_G3;
00261     AVR32_ENTER_CRITICAL_REGION( );
00262     // Unlock the write-protected OSCCTRL1 register
00263     SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4);
00264     // Write Back
00265     AVR32_SCIF.OSCCTRL[SCIF_OSC1] = u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1];
00266     AVR32_LEAVE_CRITICAL_REGION( );
00267   }
00268 
00269   return PASS;
00270 }

long int scif_configure_osc_extmode ( scif_osc_t  osc  ) 

Configure an external clock as input clock.

Parameters:
osc The external clock to configure [INPUT]
Returns:
Status.
Return values:
0 External clock successfully configured.
<0 Error configuring the external clock.

Definition at line 272 of file scif_uc3c.c.

References u_avr32_scif_oscctrl_t::OSCCTRL, SCIF_OSC_MODE_EXT_CLK, and SCIF_UNLOCK.

00273 {
00274   u_avr32_scif_oscctrl_t   u_avr32_scif_oscctrl;
00275   
00276       // Read Register
00277     u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ;
00278     // Modify : Configure the oscillator mode to crystal and set the gain according to the
00279     // cyrstal frequency.
00280     u_avr32_scif_oscctrl.OSCCTRL[osc].mode = SCIF_OSC_MODE_EXT_CLK;
00281     AVR32_ENTER_CRITICAL_REGION( );
00282     // Unlock the write-protected OSCCTRL0 register
00283     SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);
00284     // Write Back
00285     AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc];
00286     AVR32_LEAVE_CRITICAL_REGION( );
00287 
00288   return PASS;
00289 }

long int scif_enable_extosc ( scif_osc_t  osc  ) 

Enable external clock.

Parameters:
osc The oscillator to configure [INPUT]
Returns:
Status.
Return values:
0 Oscillator successfully started
<0 Error starting the oscillator.

Definition at line 318 of file scif_uc3c.c.

References u_avr32_scif_oscctrl_t::OSCCTRL, and SCIF_UNLOCK.

00319 {
00320 
00321   u_avr32_scif_oscctrl_t   u_avr32_scif_oscctrl;
00322 
00323   // Read Register
00324   u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ;    
00325   // Modify : Enable the osc.
00326   u_avr32_scif_oscctrl.OSCCTRL[osc].oscen = ENABLE;
00327   AVR32_ENTER_CRITICAL_REGION( );
00328   // Unlock the write-protected OSCCTRL0 register
00329   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);
00330   // Write Back
00331   AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc];
00332   AVR32_LEAVE_CRITICAL_REGION( );
00333   
00334   return PASS;
00335 }

long int scif_enable_osc ( scif_osc_t  osc,
unsigned int  startup,
bool  wait_for_ready 
)

Enable an oscillator with a given startup time.

Parameters:
osc The oscillator to configure [INPUT]
startup Oscillator startup time (one of AVR32_SCIF_OSCCTRLx_STARTUP_x_RCOSC) [INPUT]
wait_for_ready Wait for the oscillator to be stable before return [INPUT]
Returns:
Status.
Return values:
0 Oscillator successfully started
<0 Error starting the oscillator.

Definition at line 291 of file scif_uc3c.c.

00292 {
00293 
00294   u_avr32_scif_oscctrl_t   u_avr32_scif_oscctrl;
00295 
00296   // Read Register
00297   u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ;      
00298   // Modify: Configure the oscillator startup and enable the osc.
00299   u_avr32_scif_oscctrl.OSCCTRL[osc].startup = startup;
00300   u_avr32_scif_oscctrl.OSCCTRL[osc].oscen = ENABLE;
00301   AVR32_ENTER_CRITICAL_REGION( );
00302   // Unlock the write-protected OSCCTRL0 register
00303   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);
00304   // Write Back
00305   AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc];
00306   AVR32_LEAVE_CRITICAL_REGION( );
00307 
00308   if(true == wait_for_ready)
00309   {
00310     // Wait until OSC0 is stable and ready to be used.
00311     if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK))
00312       return -1;
00313   }
00314       
00315   return PASS;
00316 }

long int scif_gc_enable ( unsigned int  gclk  ) 

Enable a generic clock.

Parameters:
gclk generic clock number (0 for gc0...)
Returns:
Status.
Return values:
0 Success.
<0 An error occured.

Definition at line 662 of file scif_uc3c.c.

Referenced by local_start_gc().

00663 {
00664 #ifdef AVR32SFW_INPUT_CHECK
00665   // Check that the generic clock number is correct
00666   if( gclk > AVR32_SCIF_GCLK_NUM )
00667   {
00668     return -1;
00669   }
00670 #endif  // AVR32SFW_INPUT_CHECK
00671 
00672   // If the generic clock is already enabled, do nothing.
00673   if(!(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK))
00674     AVR32_SCIF.gcctrl[gclk] |= AVR32_SCIF_GCCTRL_CEN_MASK;
00675     
00676   return PASS;
00677 
00678 }

long int scif_gc_setup ( unsigned int  gclk,
scif_gcctrl_oscsel_t  clk_src,
unsigned int  diven,
unsigned int  divfactor 
)

Setup a generic clock.

Parameters:
gclk generic clock number (0 for gc0...)
clk_src The input clock source to use for the generic clock
diven Generic clock divisor enable
divfactor Generic clock divisor
Note:
If the generic clock is already enabled, this function will disable it, apply the configuration then restart the generic clock.
Returns:
Status.
Return values:
0 Success.
<0 An error occured.

Definition at line 614 of file scif_uc3c.c.

Referenced by local_start_gc().

00615 {
00616   int restart_gc = false;
00617   
00618   
00619   // Change the division factor to conform to the equation: fgclk = fsrc/divfactor = fsrc/(2*(div+1))
00620   divfactor = (divfactor>>1) -1;
00621 
00622 #ifdef AVR32SFW_INPUT_CHECK
00623   // Check that the generic clock number is correct
00624   if( gclk > AVR32_SCIF_GCLK_NUM )
00625   {
00626     return -1;
00627   }
00628   // Check that the clock source for the generic clock is correct.
00629   if(( clk_src >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( clk_src < 0 ))
00630   {
00631     return -1;
00632   }
00633   // Check that the required division factor is correct.
00634   if(diven)
00635   {
00636     if(divfactor >= (1<<AVR32_SCIF_GCCTRL_DIV_SIZE))
00637       return -1;
00638   }
00639 #endif  // AVR32SFW_INPUT_CHECK
00640 
00641   // If the generic clock is already enabled, disable it before changing its setup.
00642   if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00643   {
00644     restart_gc = true;
00645     if(scif_stop_gclk(gclk) < 0)
00646       return -1;  // Could not stop the generic clock.
00647   }
00648 
00649   // Setup the generic clock.
00650   AVR32_SCIF.gcctrl[gclk] = ((divfactor << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK)
00651                             |((diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK)
00652                             |((clk_src << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK);
00653                             
00654   // Restart the gc if it previously was enabled.
00655   if(true == restart_gc)
00656     AVR32_SCIF.gcctrl[gclk] |= AVR32_SCIF_GCCTRL_CEN_MASK ;
00657 
00658   return PASS;
00659 }

bool scif_is_osc_ready ( scif_osc_t  osc  ) 

Is an oscillator stable and ready to be used as clock source?

Parameters:
osc The oscillator [INPUT]
Returns:
Status.
Return values:
true oscillator stable and ready
false oscillator not enabled or not ready.

Definition at line 197 of file scif_uc3c.c.

00198 {
00199   if (osc == SCIF_OSC0)
00200   {
00201     return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC0RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC0RDY_OFFSET);
00202   }
00203   else
00204   {
00205     return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC1RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC1RDY_OFFSET);  
00206   }
00207 }

static long int scif_pclksr_statushigh_wait ( unsigned long  statusMask  )  [static]

Wait for a status high in the Power and Clocks status register.

Parameters:
statusMask Mask field of the status to poll [INPUT]
Returns:
Status.
Return values:
0 Status is high.
<0 SCIF_POLL_TIMEOUT Timeout expired before the status was high.

Definition at line 88 of file scif_uc3c.c.

References SCIF_POLL_TIMEOUT.

Referenced by scif_dfll0_closedloop_start(), scif_dfll0_openloop_start(), scif_dfll0_openloop_stop(), scif_dfll0_openloop_updatefreq(), scif_enable_osc(), scif_start_osc(), and scif_start_osc32().

00089 {
00090   unsigned int  timeout = SCIF_POLL_TIMEOUT;
00091   
00092   while(!(AVR32_SCIF.pclksr & statusMask))
00093   {
00094     if(--timeout == 0)
00095       return -1;
00096   }
00097   return PASS;
00098 }

long int scif_pll_disable ( scif_pll_t  pll  ) 

This function will disable a PLL.

Parameters:
pll The PLL to configure [INPUT]
Returns:
Status.
Return values:
0 PLL successfully started
<0 Error starting the PLL.

Definition at line 382 of file scif_uc3c.c.

References u_avr32_scif_pll_t::PLL, and SCIF_UNLOCK.

00383 {
00384 
00385   u_avr32_scif_pll_t   u_avr32_scif_pll;
00386 
00387   // Read Register
00388   u_avr32_scif_pll.PLL[pll] = AVR32_SCIF.PLL[pll] ;
00389   // Modify Configuration 
00390   u_avr32_scif_pll.PLL[pll].pllen = DISABLE;
00391   AVR32_ENTER_CRITICAL_REGION( );
00392   // Unlock the write-protected PLL0 register
00393   SCIF_UNLOCK(AVR32_SCIF_PLL + 4*pll); 
00394   // Write Back
00395   AVR32_SCIF.PLL[pll] = u_avr32_scif_pll.PLL[pll];
00396   AVR32_LEAVE_CRITICAL_REGION( );
00397 
00398   return PASS;
00399 }

long int scif_pll_enable ( scif_pll_t  pll  ) 

This function will enable a PLL.

Parameters:
pll The PLL to configure [INPUT]
Returns:
Status.
Return values:
0 PLL successfully started
<0 Error starting the PLL.

Definition at line 363 of file scif_uc3c.c.

References u_avr32_scif_pll_t::PLL, and SCIF_UNLOCK.

00364 {
00365 
00366   u_avr32_scif_pll_t   u_avr32_scif_pll;
00367   
00368     // Read Register
00369     u_avr32_scif_pll.PLL[pll] = AVR32_SCIF.PLL[pll] ;
00370     // Modify Configuration 
00371     u_avr32_scif_pll.PLL[pll].pllen = ENABLE;
00372     AVR32_ENTER_CRITICAL_REGION( );
00373     // Unlock the write-protected PLL0 register
00374     SCIF_UNLOCK(AVR32_SCIF_PLL + 4*pll); 
00375     // Write Back
00376     AVR32_SCIF.PLL[pll] = u_avr32_scif_pll.PLL[pll];
00377     AVR32_LEAVE_CRITICAL_REGION( );
00378   
00379   return PASS;
00380 }

long int scif_pll_setup ( scif_pll_t  pll,
const scif_pll_opt_t  opt 
)

PLL0/PLL1 Functions.

This function will setup a PLL.

Definition at line 340 of file scif_uc3c.c.

References scif_pll_opt_t::div, scif_pll_opt_t::lockcount, scif_pll_opt_t::mul, scif_pll_opt_t::osc, u_avr32_scif_pll_t::PLL, scif_pll_opt_t::pll_div2, scif_pll_opt_t::pll_freq, scif_pll_opt_t::pll_wbwdisable, and SCIF_UNLOCK.

00341 {
00342 
00343   u_avr32_scif_pll_t   u_avr32_scif_pll;
00344 
00345   // Read Register
00346   u_avr32_scif_pll.PLL[pll] = AVR32_SCIF.PLL[pll] ;
00347   // Modify Configuration 
00348   u_avr32_scif_pll.PLL[pll].pllosc  = opt.osc;
00349   u_avr32_scif_pll.PLL[pll].pllopt  = opt.pll_freq | (opt.pll_div2 << 1) | (opt.pll_wbwdisable << 2);
00350   u_avr32_scif_pll.PLL[pll].plldiv   = opt.div;
00351   u_avr32_scif_pll.PLL[pll].pllmul  = opt.mul;
00352   u_avr32_scif_pll.PLL[pll].pllcount= opt.lockcount;
00353   AVR32_ENTER_CRITICAL_REGION( );
00354   // Unlock the write-protected PLL0 register
00355   SCIF_UNLOCK(AVR32_SCIF_PLL + 4*pll); 
00356   // Write Back
00357   AVR32_SCIF.PLL[pll] = u_avr32_scif_pll.PLL[pll];
00358   AVR32_LEAVE_CRITICAL_REGION( );
00359 
00360   return PASS;
00361 }

unsigned long scif_read_gplp ( unsigned long  gplp  ) 

Read the content of the SCIF GPLP registers.

Parameters:
gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
Returns:
The content of the chosen GPLP register.

Definition at line 100 of file scif_uc3c.c.

00101 {
00102   return AVR32_SCIF.gplp[gplp];
00103 }

long int scif_start_gclk ( unsigned int  gclk,
const scif_gclk_opt_t opt 
)

Generic Clock Functions.

Setup and start a generic clock.

Definition at line 559 of file scif_uc3c.c.

00560 {
00561 #ifdef AVR32SFW_INPUT_CHECK
00562   // Check that the generic clock number is correct
00563   if( gclk > AVR32_SCIF_GCLK_NUM )
00564   {
00565     return -1;
00566   }
00567   // Check that the clock source for the generic clock is correct.
00568   if(( opt->clock_source >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( opt->clock_source < 0 ))
00569   {
00570     return -1;
00571   }
00572 #endif  // AVR32SFW_INPUT_CHECK
00573 
00574   // If the generic clock is already enabled, return an error.
00575   if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00576     return -1;
00577 
00578   // Configure & start the generic clock.
00579   AVR32_SCIF.gcctrl[gclk] = ((opt->divider << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK)
00580                             |((opt->diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK)
00581                             |((opt->clock_source << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK)
00582                             |(AVR32_SCIF_GCCTRL_CEN_MASK);
00583 
00584   return PASS;
00585 }

long int scif_start_osc ( scif_osc_t  osc,
const scif_osc_opt_t opt,
bool  wait_for_ready 
)

Interrupt Functions.

Configure and start an OSC0/OSC1 oscillator.

Power and Clocks Status Functions OSC0/OSC1 Functions

Definition at line 128 of file scif_uc3c.c.

00129 {
00130   u_avr32_scif_oscctrl_t   u_avr32_scif_oscctrl;
00131   
00132 #ifdef AVR32SFW_INPUT_CHECK
00133   // Check that the input frequency is in the supported frequency range.
00134   if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ)
00135       || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ))
00136   {
00137     return -1;
00138   }
00139   // Check : for OSC0/OSC1, only 2 modes are supported
00140   if( (opt->mode != SCIF_OSC_MODE_EXT_CLK)
00141       && (opt->mode != SCIF_OSC_MODE_2PIN_CRYSTAL))
00142   {
00143     return -1;
00144   }
00145   
00146   if (osc == SCIF_OSC0)
00147   {
00148     // Check that the startup value is in the supported range.
00149     if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC)
00150     {
00151       return -1;
00152     }
00153     // Check that the gain value is in the supported range.
00154     if(opt->gain > AVR32_SCIF_OSCCTRL0_GAIN_G3)
00155     {
00156       return -1;
00157     }
00158   }
00159   else
00160   {
00161     // Check that the startup value is in the supported range.
00162     if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL1_STARTUP_16384_RCOSC)
00163     {
00164       return -1;
00165     }
00166     // Check that the gain value is in the supported range.
00167     if(opt->gain > AVR32_SCIF_OSCCTRL1_GAIN_G3)
00168     {
00169       return -1;
00170     }  
00171   }
00172 #endif  // AVR32SFW_INPUT_CHECK
00173   // Read Register
00174   u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ;
00175   // Modify: Configure & start OSC0.
00176   u_avr32_scif_oscctrl.OSCCTRL[osc].mode = opt->mode;
00177   u_avr32_scif_oscctrl.OSCCTRL[osc].gain = opt->gain;
00178   u_avr32_scif_oscctrl.OSCCTRL[osc].startup = opt->startup;
00179   u_avr32_scif_oscctrl.OSCCTRL[osc].oscen = ENABLE;
00180   AVR32_ENTER_CRITICAL_REGION( );
00181   // Unlock the write-protected OSCCTRL0 register
00182   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);    
00183   // Write Back
00184   AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc];
00185   AVR32_LEAVE_CRITICAL_REGION( );
00186 
00187   if(true == wait_for_ready)
00188   {
00189     // Wait until OSC0 is stable and ready to be used.
00190     if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK))
00191       return -1;
00192   }
00193   return PASS;
00194 }

long int scif_start_osc32 ( const scif_osc32_opt_t opt,
bool  wait_for_ready 
)

OSC32 Functions.

Configure and start the OSC32 oscillator.

Definition at line 422 of file scif_uc3c.c.

00423 {
00424   u_avr32_scif_oscctrl32_t  u_avr32_scif_oscctrl32;
00425   
00426   
00427 #ifdef AVR32SFW_INPUT_CHECK
00428   // Check that the input frequency is in the supported frequency range.
00429   if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ)
00430       || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ))
00431   {
00432     return -1;
00433   }
00434   // Check : for OSC0/OSC1, only 2 modes are supported
00435   if( (opt->mode < SCIF_OSC_MODE_EXT_CLK)
00436       || (opt->mode > SCIF_OSC_MODE_2PIN_CRYSTAL)
00437       || (opt->mode == SCIF_OSC_MODE_NOT_SUPPORTED_1)
00438       || (opt->mode == SCIF_OSC_MODE_NOT_SUPPORTED_2) )
00439   {
00440     return -1;
00441   }
00442   // Check that the startup value is in the supported range.
00443   if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL32_STARTUP_524288_RCOSC)
00444   {
00445     return -1;
00446   }
00447 #endif  // AVR32SFW_INPUT_CHECK
00448 
00449   // Read Register
00450   u_avr32_scif_oscctrl32.oscctrl32 = AVR32_SCIF.oscctrl32 ;  
00451   
00452   // Modify : Configure & start OSC32.
00453   u_avr32_scif_oscctrl32.OSCCTRL32.mode = opt->mode;
00454   u_avr32_scif_oscctrl32.OSCCTRL32.startup = opt->startup;
00455   u_avr32_scif_oscctrl32.OSCCTRL32.osc32en = ENABLE;
00456   
00457   AVR32_ENTER_CRITICAL_REGION( );
00458   // Unlock the write-protected OSCCTRL32 register
00459   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32);
00460   
00461   // Write Back
00462   AVR32_SCIF.oscctrl32 = u_avr32_scif_oscctrl32.oscctrl32;
00463   AVR32_LEAVE_CRITICAL_REGION( );
00464 
00465   if(true == wait_for_ready)
00466   {
00467     // Wait until OSC32 is stable and ready to be used.
00468     if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC32RDY_MASK))
00469       return -1;
00470   }
00471   
00472   return PASS;
00473 }

void scif_start_rc120M ( void   ) 

120MHz RCosc Functions

Start the 120MHz internal RCosc (RC120M) clock.

Definition at line 532 of file scif_uc3c.c.

00533 {
00534   AVR32_ENTER_CRITICAL_REGION( );
00535   // Unlock the write-protected RC120MCR register
00536   SCIF_UNLOCK(AVR32_SCIF_RC120MCR);
00537   AVR32_SCIF.rc120mcr = AVR32_SCIF_RC120MCR_EN_MASK;
00538   AVR32_LEAVE_CRITICAL_REGION( );
00539 }

void scif_start_rc8M ( void   ) 

Calibration Functions.

Start the 8MHz internal RCosc (RC8M) clock.

Critical Path Oscillator Functions 8MHz RCosc Functions

Definition at line 506 of file scif_uc3c.c.

References SCIF_UNLOCK.

00507 {
00508   unsigned int* calibration_bits = (unsigned int*)0x80800200;
00509   AVR32_ENTER_CRITICAL_REGION( );
00510   // Unlock the write-protected RC8MCR register
00511   SCIF_UNLOCK(AVR32_SCIF_RCCR8);
00512   AVR32_SCIF.rccr8 = AVR32_SCIF_RCCR8_RCOSC8_EN_MASK | ((*calibration_bits)&AVR32_SCIF_RCCR8_CALIB_MASK);
00513   AVR32_LEAVE_CRITICAL_REGION( );
00514 }

long int scif_stop_gclk ( unsigned int  gclk  ) 

Stop a generic clock.

Parameters:
gclk The generic clock number to stop.
Note:
To avoid an infinite loop, this function checks the Clock enable flag SCIF_POLL_TIMEOUT times.
Returns:
Status.
Return values:
0 Success.
<0 Unable to stop generic clock.

Definition at line 588 of file scif_uc3c.c.

Referenced by scif_gc_setup().

00589 {
00590   unsigned int  timeout = SCIF_POLL_TIMEOUT;
00591   
00592 #ifdef AVR32SFW_INPUT_CHECK
00593   // Check that the generic clock number is correct
00594   if( gclk > AVR32_SCIF_GCLK_NUM )
00595   {
00596     return -1;
00597   }
00598 #endif  // AVR32SFW_INPUT_CHECK
00599 
00600   // Stop the generic clock.
00601   AVR32_SCIF.gcctrl[gclk] &= ~AVR32_SCIF_GCCTRL_CEN_MASK;
00602   
00603   // Wait until the generic clock is actually stopped.
00604   while(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00605   {
00606     if(--timeout == 0)
00607       return -1;
00608   }
00609   
00610   return PASS;
00611 }

long int scif_stop_osc ( scif_osc_t  osc  ) 

Stop an oscillator.

Parameters:
osc The oscillator to stop
Returns:
Status.
Return values:
0 Oscillator successfully stopped.
<0 An error occured when stopping the oscillator.

Definition at line 210 of file scif_uc3c.c.

00211 {
00212 
00213   unsigned long temp;
00214 
00215   temp = AVR32_SCIF.oscctrl[osc];
00216   temp &= ~(AVR32_SCIF_OSCCTRL_OSCEN_DISABLE << AVR32_SCIF_OSCCTRL_OSCEN_OFFSET);
00217   AVR32_ENTER_CRITICAL_REGION( );
00218   // Unlock the write-protected OSCCTRL0 register
00219   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);
00220   // Stop OSC0.
00221   AVR32_SCIF.oscctrl[osc] = temp;
00222   AVR32_LEAVE_CRITICAL_REGION( );
00223       
00224   return PASS;
00225 }

long scif_stop_osc32 (  ) 

Stop the OSC32 oscillator.

Returns:
Status.
Return values:
0 Oscillator successfully stopped.
<0 An error occured when stopping the oscillator.

Definition at line 476 of file scif_uc3c.c.

00477 {
00478   unsigned long temp = AVR32_SCIF.oscctrl32;
00479   temp &= ~(AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE << AVR32_SCIF_OSCCTRL32_OSC32EN_OFFSET);
00480 
00481   AVR32_ENTER_CRITICAL_REGION( );
00482   // Unlock the write-protected OSCCTRL32 register
00483   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32);
00484   
00485   // Stop OSC32.
00486   AVR32_SCIF.oscctrl32 = temp;
00487   AVR32_LEAVE_CRITICAL_REGION( );
00488 
00489   return PASS;
00490 }

void scif_stop_rc120M ( void   ) 

Stop the 120MHz internal RCosc (RC120M) clock.

Definition at line 541 of file scif_uc3c.c.

00542 {
00543   unsigned long temp = AVR32_SCIF.rc120mcr;
00544 
00545   AVR32_ENTER_CRITICAL_REGION( );
00546   // Unlock the write-protected RC120MCR register
00547   SCIF_UNLOCK(AVR32_SCIF_RC120MCR);
00548   temp &= ~AVR32_SCIF_RC120MCR_EN_MASK;
00549   AVR32_SCIF.rc120mcr = temp;
00550   AVR32_LEAVE_CRITICAL_REGION( );
00551 }

void scif_stop_rc8M ( void   ) 

Stop the 8MHz internal RCosc (RC8M) clock.

Definition at line 516 of file scif_uc3c.c.

References SCIF_UNLOCK.

00517 {
00518   unsigned long temp = AVR32_SCIF.rccr8;
00519   
00520   AVR32_ENTER_CRITICAL_REGION( );
00521   // Unlock the write-protected RC8MCR register
00522   SCIF_UNLOCK(AVR32_SCIF_RCCR8);
00523   temp &= ~AVR32_SCIF_RCCR8_RCOSC8_EN_MASK;
00524   AVR32_SCIF.rccr8 = temp;
00525   AVR32_LEAVE_CRITICAL_REGION( );
00526 }

long int scif_wait_for_pll_locked ( scif_pll_t  pll  ) 

This function will wait for PLL locked.

Parameters:
pll The PLL to configure [INPUT]
Returns:
Status.
Return values:
0 PLL successfully started
<0 Error starting the PLL.

Definition at line 401 of file scif_uc3c.c.

References SCIF_PLL0.

00402 {
00403   
00404   if (pll == SCIF_PLL0)
00405   { 
00406       // Wait until PLL0 is stable and ready to be used.
00407       while(!(AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_PLL0_LOCK_MASK));
00408   }
00409   else
00410   {
00411       // Wait until PLL1 is stable and ready to be used.
00412       while(!(AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_PLL1_LOCK_MASK));
00413   }
00414   
00415   return PASS;
00416 }

void scif_write_gplp ( int  gplp,
unsigned long  value 
)

Write into the SCIF GPLP registers.

Parameters:
gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
value Value to write

Definition at line 106 of file scif_uc3c.c.

References SCIF_UNLOCK.

00107 {
00108   SCIF_UNLOCK(AVR32_SCIF_GPLP + 4*gplp); 
00109   AVR32_SCIF.gplp[gplp] = value;
00110 }


Generated on Fri Feb 19 02:26:20 2010 for AVR32 UC3 - SCIF Driver Example 1 by  doxygen 1.5.5