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00048 #include <avr32/io.h>
00049 #include "compiler.h"
00050 #include "tc.h"
00051
00052
00053 int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel)
00054 {
00055
00056 if (channel >= TC_NUMBER_OF_CHANNELS)
00057 return TC_INVALID_ARGUMENT;
00058
00059 return tc->channel[channel].imr;
00060 }
00061
00062
00063 int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield)
00064 {
00065 Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00066
00067
00068 if (channel >= TC_NUMBER_OF_CHANNELS)
00069 return TC_INVALID_ARGUMENT;
00070
00071
00072 tc->channel[channel].ier = bitfield->etrgs << AVR32_TC_ETRGS_OFFSET |
00073 bitfield->ldrbs << AVR32_TC_LDRBS_OFFSET |
00074 bitfield->ldras << AVR32_TC_LDRAS_OFFSET |
00075 bitfield->cpcs << AVR32_TC_CPCS_OFFSET |
00076 bitfield->cpbs << AVR32_TC_CPBS_OFFSET |
00077 bitfield->cpas << AVR32_TC_CPAS_OFFSET |
00078 bitfield->lovrs << AVR32_TC_LOVRS_OFFSET |
00079 bitfield->covfs << AVR32_TC_COVFS_OFFSET;
00080
00081
00082 if (global_interrupt_enabled) Disable_global_interrupt();
00083 tc->channel[channel].idr = (~bitfield->etrgs & 1) << AVR32_TC_ETRGS_OFFSET |
00084 (~bitfield->ldrbs & 1) << AVR32_TC_LDRBS_OFFSET |
00085 (~bitfield->ldras & 1) << AVR32_TC_LDRAS_OFFSET |
00086 (~bitfield->cpcs & 1) << AVR32_TC_CPCS_OFFSET |
00087 (~bitfield->cpbs & 1) << AVR32_TC_CPBS_OFFSET |
00088 (~bitfield->cpas & 1) << AVR32_TC_CPAS_OFFSET |
00089 (~bitfield->lovrs & 1) << AVR32_TC_LOVRS_OFFSET |
00090 (~bitfield->covfs & 1) << AVR32_TC_COVFS_OFFSET;
00091 tc->channel[channel].sr;
00092 if (global_interrupt_enabled) Enable_global_interrupt();
00093
00094 return 0;
00095 }
00096
00097
00098 int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src)
00099 {
00100
00101 if (channel >= TC_NUMBER_OF_CHANNELS || ext_clk_sig_src >= 1 << AVR32_TC_BMR_TC0XC0S_SIZE)
00102 return TC_INVALID_ARGUMENT;
00103
00104
00105 tc->bmr = (tc->bmr & ~(AVR32_TC_BMR_TC0XC0S_MASK << (channel * AVR32_TC_BMR_TC0XC0S_SIZE))) |
00106 (ext_clk_sig_src << (channel * AVR32_TC_BMR_TC0XC0S_SIZE));
00107
00108 return 0;
00109 }
00110
00111
00112 int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt)
00113 {
00114
00115 if (opt->channel >= TC_NUMBER_OF_CHANNELS)
00116 return TC_INVALID_ARGUMENT;
00117
00118
00119 tc->channel[opt->channel].cmr = opt->ldrb << AVR32_TC_LDRB_OFFSET |
00120 opt->ldra << AVR32_TC_LDRA_OFFSET |
00121 0 << AVR32_TC_WAVE_OFFSET |
00122 opt->cpctrg << AVR32_TC_CPCTRG_OFFSET |
00123 opt->abetrg << AVR32_TC_ABETRG_OFFSET |
00124 opt->etrgedg << AVR32_TC_ETRGEDG_OFFSET|
00125 opt->ldbdis << AVR32_TC_LDBDIS_OFFSET |
00126 opt->ldbstop << AVR32_TC_LDBSTOP_OFFSET |
00127 opt->burst << AVR32_TC_BURST_OFFSET |
00128 opt->clki << AVR32_TC_CLKI_OFFSET |
00129 opt->tcclks << AVR32_TC_TCCLKS_OFFSET;
00130
00131 return 0;
00132 }
00133
00134
00135 int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt)
00136 {
00137
00138 if (opt->channel >= TC_NUMBER_OF_CHANNELS)
00139 return TC_INVALID_ARGUMENT;
00140
00141
00142 tc->channel[opt->channel].cmr = opt->bswtrg << AVR32_TC_BSWTRG_OFFSET |
00143 opt->beevt << AVR32_TC_BEEVT_OFFSET |
00144 opt->bcpc << AVR32_TC_BCPC_OFFSET |
00145 opt->bcpb << AVR32_TC_BCPB_OFFSET |
00146 opt->aswtrg << AVR32_TC_ASWTRG_OFFSET |
00147 opt->aeevt << AVR32_TC_AEEVT_OFFSET |
00148 opt->acpc << AVR32_TC_ACPC_OFFSET |
00149 opt->acpa << AVR32_TC_ACPA_OFFSET |
00150 1 << AVR32_TC_WAVE_OFFSET |
00151 opt->wavsel << AVR32_TC_WAVSEL_OFFSET |
00152 opt->enetrg << AVR32_TC_ENETRG_OFFSET |
00153 opt->eevt << AVR32_TC_EEVT_OFFSET |
00154 opt->eevtedg << AVR32_TC_EEVTEDG_OFFSET |
00155 opt->cpcdis << AVR32_TC_CPCDIS_OFFSET |
00156 opt->cpcstop << AVR32_TC_CPCSTOP_OFFSET |
00157 opt->burst << AVR32_TC_BURST_OFFSET |
00158 opt->clki << AVR32_TC_CLKI_OFFSET |
00159 opt->tcclks << AVR32_TC_TCCLKS_OFFSET;
00160
00161 return 0;
00162 }
00163
00164
00165 int tc_start(volatile avr32_tc_t *tc, unsigned int channel)
00166 {
00167
00168 if (channel >= TC_NUMBER_OF_CHANNELS)
00169 return TC_INVALID_ARGUMENT;
00170
00171
00172 tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK | AVR32_TC_CLKEN_MASK;
00173
00174 return 0;
00175 }
00176
00177
00178 int tc_stop(volatile avr32_tc_t *tc, unsigned int channel)
00179 {
00180
00181 if (channel >= TC_NUMBER_OF_CHANNELS)
00182 return TC_INVALID_ARGUMENT;
00183
00184
00185 tc->channel[channel].ccr = AVR32_TC_CLKDIS_MASK;
00186
00187 return 0;
00188 }
00189
00190
00191 int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel)
00192 {
00193
00194 if (channel >= TC_NUMBER_OF_CHANNELS)
00195 return TC_INVALID_ARGUMENT;
00196
00197
00198 tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK;
00199
00200 return 0;
00201 }
00202
00203
00204 void tc_sync_trigger(volatile avr32_tc_t *tc)
00205 {
00206
00207 tc->bcr = AVR32_TC_BCR_SYNC_MASK;
00208 }
00209
00210
00211 void tc_sync_start(volatile avr32_tc_t *tc)
00212 {
00213 unsigned int i;
00214
00215 for(i=0; i<TC_NUMBER_OF_CHANNELS;i++)
00216 tc->channel[i].ccr = AVR32_TC_CLKEN_MASK;
00217
00218
00219 tc->bcr = AVR32_TC_BCR_SYNC_MASK;
00220 }
00221
00222
00223 int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel)
00224 {
00225
00226 if (channel >= TC_NUMBER_OF_CHANNELS)
00227 return TC_INVALID_ARGUMENT;
00228
00229 return tc->channel[channel].sr;
00230 }
00231
00232
00233 int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel)
00234 {
00235
00236 if (channel >= TC_NUMBER_OF_CHANNELS)
00237 return TC_INVALID_ARGUMENT;
00238
00239 return Rd_bitfield(tc->channel[channel].cv, AVR32_TC_CV_MASK);
00240 }
00241
00242
00243 int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel)
00244 {
00245
00246 if (channel >= TC_NUMBER_OF_CHANNELS)
00247 return TC_INVALID_ARGUMENT;
00248
00249 return Rd_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK);
00250 }
00251
00252
00253 int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel)
00254 {
00255
00256 if (channel >= TC_NUMBER_OF_CHANNELS)
00257 return TC_INVALID_ARGUMENT;
00258
00259 return Rd_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK);
00260 }
00261
00262
00263 int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel)
00264 {
00265
00266 if (channel >= TC_NUMBER_OF_CHANNELS)
00267 return TC_INVALID_ARGUMENT;
00268
00269 return Rd_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK);
00270 }
00271
00272
00273 int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
00274 {
00275
00276 if (channel >= TC_NUMBER_OF_CHANNELS)
00277 return TC_INVALID_ARGUMENT;
00278
00279
00280 if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
00281 Wr_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK, value);
00282
00283 return value;
00284 }
00285
00286
00287 int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
00288 {
00289
00290 if (channel >= TC_NUMBER_OF_CHANNELS)
00291 return TC_INVALID_ARGUMENT;
00292
00293
00294 if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
00295 Wr_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK, value);
00296
00297 return value;
00298 }
00299
00300
00301 int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
00302 {
00303
00304 if (channel >= TC_NUMBER_OF_CHANNELS)
00305 return TC_INVALID_ARGUMENT;
00306
00307
00308 if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
00309 Wr_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK, value);
00310
00311 return value;
00312 }