EMB Project Status (06/14/2010 - 18:30:12) | |||
Project File: | EMB.ise | Implementation State: | Programming File Not Generated |
Module Name: | toplevel |
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No Errors |
Target Device: | xc3s500e-5pq208 |
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1 Warning |
Product Version: | ISE 11.1 |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Setup: 0, Hold: 0, Component Switching Limit: 0) (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 551 | 9,312 | 5% | ||
Number of 4 input LUTs | 210 | 9,312 | 2% | ||
Number of occupied Slices | 503 | 4,656 | 10% | ||
Number of Slices containing only related logic | 503 | 503 | 100% | ||
Number of Slices containing unrelated logic | 0 | 503 | 0% | ||
Total Number of 4 input LUTs | 210 | 9,312 | 2% | ||
Number of bonded IOBs | 98 | 158 | 62% | ||
Number of RAMB16s | 4 | 20 | 20% | ||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Average Fanout of Non-Clock Nets | 2.20 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Mon Jun 14 18:28:20 2010 | 0 | 1 Warning | 3 Infos | |
Translation Report | Current | Mon Jun 14 18:28:40 2010 | 0 | 0 | 0 | |
Map Report | Current | Mon Jun 14 18:29:04 2010 | 0 | 0 | 5 Infos | |
Place and Route Report | Current | Mon Jun 14 18:29:44 2010 | 0 | 0 | 0 | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Mon Jun 14 18:29:52 2010 | 0 | 0 | 2 Infos | |
Bitgen Report | Current | Mon Jun 14 18:30:10 2010 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated |