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00049 #include "compiler.h"
00050 #include "usart.h"
00051
00052
00053
00056
00057
00058
00065 #if (defined __GNUC__)
00066 __attribute__((__always_inline__))
00067 #endif
00068 static __inline__ int usart_mode_is_multidrop(volatile avr32_usart_t *usart)
00069 {
00070 return ((usart->mr >> AVR32_USART_MR_PAR_OFFSET) & AVR32_USART_MR_PAR_MULTI) == AVR32_USART_MR_PAR_MULTI;
00071 }
00072
00073
00089 static int usart_set_async_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, unsigned long pba_hz)
00090 {
00091 unsigned int over = (pba_hz >= 16 * baudrate) ? 16 : 8;
00092 unsigned int cd_fp = ((1 << AVR32_USART_BRGR_FP_SIZE) * pba_hz + (over * baudrate) / 2) / (over * baudrate);
00093 unsigned int cd = cd_fp >> AVR32_USART_BRGR_FP_SIZE;
00094 unsigned int fp = cd_fp & ((1 << AVR32_USART_BRGR_FP_SIZE) - 1);
00095
00096 if (cd < 1 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1)
00097 return USART_INVALID_INPUT;
00098
00099 usart->mr = (usart->mr & ~(AVR32_USART_MR_USCLKS_MASK |
00100 AVR32_USART_MR_SYNC_MASK |
00101 AVR32_USART_MR_OVER_MASK)) |
00102 AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET |
00103 ((over == 16) ? AVR32_USART_MR_OVER_X16 : AVR32_USART_MR_OVER_X8) << AVR32_USART_MR_OVER_OFFSET;
00104
00105 usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET |
00106 fp << AVR32_USART_BRGR_FP_OFFSET;
00107
00108 return USART_SUCCESS;
00109 }
00110
00111
00126 static int usart_set_sync_master_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, unsigned long pba_hz)
00127 {
00128 unsigned int cd = (pba_hz + baudrate / 2) / baudrate;
00129
00130 if (cd < 1 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1)
00131 return USART_INVALID_INPUT;
00132
00133 usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) |
00134 AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET |
00135 AVR32_USART_MR_SYNC_MASK;
00136
00137 usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET;
00138
00139 return USART_SUCCESS;
00140 }
00141
00142
00150 static int usart_set_sync_slave_baudrate(volatile avr32_usart_t *usart)
00151 {
00152 usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) |
00153 AVR32_USART_MR_USCLKS_SCK << AVR32_USART_MR_USCLKS_OFFSET |
00154 AVR32_USART_MR_SYNC_MASK;
00155
00156 return USART_SUCCESS;
00157 }
00158
00159
00173 static int usart_set_iso7816_clock(volatile avr32_usart_t *usart, unsigned int clock, unsigned long pba_hz)
00174 {
00175 unsigned int cd = (pba_hz + clock / 2) / clock;
00176
00177 if (cd < 1 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1)
00178 return USART_INVALID_INPUT;
00179
00180 usart->mr = (usart->mr & ~(AVR32_USART_MR_USCLKS_MASK |
00181 AVR32_USART_MR_SYNC_MASK |
00182 AVR32_USART_MR_OVER_MASK)) |
00183 AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET |
00184 AVR32_USART_MR_OVER_X16 << AVR32_USART_MR_OVER_OFFSET;
00185
00186 usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET;
00187
00188 return USART_SUCCESS;
00189 }
00190
00191
00192 #if defined(AVR32_USART_400_H_INCLUDED) || \
00193 defined(AVR32_USART_410_H_INCLUDED) || \
00194 defined(AVR32_USART_420_H_INCLUDED) || \
00195 defined(AVR32_USART_440_H_INCLUDED) || \
00196 defined(AVR32_USART_602_H_INCLUDED)
00197
00198
00212 static int usart_set_spi_master_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, unsigned long pba_hz)
00213 {
00214 unsigned int cd = (pba_hz + baudrate / 2) / baudrate;
00215
00216 if (cd < 4 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1)
00217 return USART_INVALID_INPUT;
00218
00219 usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) |
00220 AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET;
00221
00222 usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET;
00223
00224 return USART_SUCCESS;
00225 }
00226
00227
00235 static int usart_set_spi_slave_baudrate(volatile avr32_usart_t *usart)
00236 {
00237 usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) |
00238 AVR32_USART_MR_USCLKS_SCK << AVR32_USART_MR_USCLKS_OFFSET;
00239
00240 return USART_SUCCESS;
00241 }
00242
00243
00244 #endif // USART rev. >= 4.0.0
00245
00246
00248
00249
00250
00253
00254
00255
00256 void usart_reset(volatile avr32_usart_t *usart)
00257 {
00258 Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00259
00260
00261
00262 if (global_interrupt_enabled) Disable_global_interrupt();
00263 usart->idr = 0xFFFFFFFF;
00264 usart->csr;
00265 if (global_interrupt_enabled) Enable_global_interrupt();
00266
00267
00268 usart->mr = 0;
00269 usart->rtor = 0;
00270 usart->ttgr = 0;
00271
00272
00273
00274 usart->cr = AVR32_USART_CR_RSTRX_MASK |
00275 AVR32_USART_CR_RSTTX_MASK |
00276 AVR32_USART_CR_RSTSTA_MASK |
00277 AVR32_USART_CR_RSTIT_MASK |
00278 AVR32_USART_CR_RSTNACK_MASK |
00279 #ifndef AVR32_USART_440_H_INCLUDED
00280
00281 AVR32_USART_CR_DTRDIS_MASK |
00282 #endif
00283 AVR32_USART_CR_RTSDIS_MASK;
00284 }
00285
00286
00287 int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00288 {
00289
00290 usart_reset(usart);
00291
00292
00293 if (!opt ||
00294 opt->charlength < 5 || opt->charlength > 9 ||
00295 opt->paritytype > 7 ||
00296 opt->stopbits > 2 + 255 ||
00297 opt->channelmode > 3 ||
00298 usart_set_async_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)
00299 return USART_INVALID_INPUT;
00300
00301 if (opt->charlength == 9)
00302 {
00303
00304 usart->mr |= AVR32_USART_MR_MODE9_MASK;
00305 }
00306 else
00307 {
00308
00309 usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;
00310 }
00311
00312 usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |
00313 opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET;
00314
00315 if (opt->stopbits > USART_2_STOPBITS)
00316 {
00317
00318 usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;
00319
00320 usart->ttgr = opt->stopbits - USART_2_STOPBITS;
00321 }
00322 else
00323
00324 usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;
00325
00326
00327 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00328 AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET;
00329
00330
00331
00332 usart->cr = AVR32_USART_CR_RXEN_MASK |
00333 AVR32_USART_CR_TXEN_MASK;
00334
00335 return USART_SUCCESS;
00336 }
00337
00338
00339 int usart_init_rs232_tx_only(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00340 {
00341
00342 usart_reset(usart);
00343
00344
00345 if (!opt ||
00346 opt->charlength < 5 || opt->charlength > 9 ||
00347 opt->paritytype > 7 ||
00348 opt->stopbits == 1 || opt->stopbits > 2 + 255 ||
00349 opt->channelmode > 3 ||
00350 usart_set_sync_master_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)
00351 return USART_INVALID_INPUT;
00352
00353 if (opt->charlength == 9)
00354 {
00355
00356 usart->mr |= AVR32_USART_MR_MODE9_MASK;
00357 }
00358 else
00359 {
00360
00361 usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;
00362 }
00363
00364 usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |
00365 opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET;
00366
00367 if (opt->stopbits > USART_2_STOPBITS)
00368 {
00369
00370 usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;
00371
00372 usart->ttgr = opt->stopbits - USART_2_STOPBITS;
00373 }
00374 else
00375
00376 usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;
00377
00378
00379 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00380 AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET;
00381
00382
00383
00384
00385 usart->cr = AVR32_USART_CR_TXEN_MASK;
00386
00387 return USART_SUCCESS;
00388 }
00389
00390
00391 int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00392 {
00393
00394 if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)
00395 return USART_INVALID_INPUT;
00396
00397
00398 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00399 AVR32_USART_MR_MODE_HARDWARE << AVR32_USART_MR_MODE_OFFSET;
00400
00401 return USART_SUCCESS;
00402 }
00403
00404
00405 int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00406 {
00407
00408 if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)
00409 return USART_INVALID_INPUT;
00410
00411
00412 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00413 AVR32_USART_MR_MODE_MODEM << AVR32_USART_MR_MODE_OFFSET;
00414
00415 return USART_SUCCESS;
00416 }
00417
00418
00419 int usart_init_sync_master(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00420 {
00421
00422 usart_reset(usart);
00423
00424
00425 if (!opt ||
00426 opt->charlength < 5 || opt->charlength > 9 ||
00427 opt->paritytype > 7 ||
00428 opt->stopbits == 1 || opt->stopbits > 2 + 255 ||
00429 opt->channelmode > 3 ||
00430 usart_set_sync_master_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)
00431 return USART_INVALID_INPUT;
00432
00433 if (opt->charlength == 9)
00434 {
00435
00436 usart->mr |= AVR32_USART_MR_MODE9_MASK;
00437 }
00438 else
00439 {
00440
00441 usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;
00442 }
00443
00444 usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |
00445 opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET;
00446
00447 if (opt->stopbits > USART_2_STOPBITS)
00448 {
00449
00450 usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;
00451
00452 usart->ttgr = opt->stopbits - USART_2_STOPBITS;
00453 }
00454 else
00455
00456 usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;
00457
00458
00459 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00460 AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET |
00461 AVR32_USART_MR_CLKO_MASK;
00462
00463
00464
00465 usart->cr = AVR32_USART_CR_RXEN_MASK |
00466 AVR32_USART_CR_TXEN_MASK;
00467
00468 return USART_SUCCESS;
00469 }
00470
00471
00472 int usart_init_sync_slave(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00473 {
00474
00475 usart_reset(usart);
00476
00477
00478 if (!opt ||
00479 opt->charlength < 5 || opt->charlength > 9 ||
00480 opt->paritytype > 7 ||
00481 opt->stopbits == 1 || opt->stopbits > 2 + 255 ||
00482 opt->channelmode > 3 ||
00483 usart_set_sync_slave_baudrate(usart) == USART_INVALID_INPUT)
00484 return USART_INVALID_INPUT;
00485
00486 if (opt->charlength == 9)
00487 {
00488
00489 usart->mr |= AVR32_USART_MR_MODE9_MASK;
00490 }
00491 else
00492 {
00493
00494 usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;
00495 }
00496
00497 usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |
00498 opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET;
00499
00500 if (opt->stopbits > USART_2_STOPBITS)
00501 {
00502
00503 usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;
00504
00505 usart->ttgr = opt->stopbits - USART_2_STOPBITS;
00506 }
00507 else
00508
00509 usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;
00510
00511
00512 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00513 AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET;
00514
00515
00516
00517 usart->cr = AVR32_USART_CR_RXEN_MASK |
00518 AVR32_USART_CR_TXEN_MASK;
00519
00520 return USART_SUCCESS;
00521 }
00522
00523
00524 int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00525 {
00526
00527 if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)
00528 return USART_INVALID_INPUT;
00529
00530
00531 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00532 AVR32_USART_MR_MODE_RS485 << AVR32_USART_MR_MODE_OFFSET;
00533
00534 return USART_SUCCESS;
00535 }
00536
00537
00538 int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt,
00539 long pba_hz, unsigned char irda_filter)
00540 {
00541
00542 if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)
00543 return USART_INVALID_INPUT;
00544
00545
00546 usart->ifr = irda_filter;
00547
00548
00549 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00550 AVR32_USART_MODE_IRDA << AVR32_USART_MR_MODE_OFFSET |
00551 AVR32_USART_MR_FILTER_MASK;
00552
00553 return USART_SUCCESS;
00554 }
00555
00556
00557 int usart_init_iso7816(volatile avr32_usart_t *usart, const usart_iso7816_options_t *opt, int t, long pba_hz)
00558 {
00559
00560 usart_reset(usart);
00561
00562
00563 if (!opt ||
00564 opt->paritytype > 1)
00565 return USART_INVALID_INPUT;
00566
00567 if (t == 0)
00568 {
00569
00570
00571 usart->mr = AVR32_USART_MR_MODE_ISO7816_T0 << AVR32_USART_MR_MODE_OFFSET |
00572 AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET |
00573 opt->bit_order << AVR32_USART_MR_MSBF_OFFSET;
00574 }
00575 else if (t == 1)
00576 {
00577
00578
00579 if (opt->bit_order != 0 ||
00580 opt->max_iterations != 0)
00581 return USART_INVALID_INPUT;
00582
00583
00584
00585 usart->mr = AVR32_USART_MR_MODE_ISO7816_T1 << AVR32_USART_MR_MODE_OFFSET |
00586 AVR32_USART_MR_NBSTOP_1 << AVR32_USART_MR_NBSTOP_OFFSET;
00587 }
00588 else
00589 return USART_INVALID_INPUT;
00590
00591 if (usart_set_iso7816_clock(usart, opt->iso7816_hz, pba_hz) == USART_INVALID_INPUT)
00592 return USART_INVALID_INPUT;
00593
00594
00595 usart->fidi = opt->fidi_ratio;
00596
00597
00598 usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |
00599 AVR32_USART_MR_CLKO_MASK |
00600 opt->inhibit_nack << AVR32_USART_MR_INACK_OFFSET |
00601 opt->dis_suc_nack << AVR32_USART_MR_DSNACK_OFFSET |
00602 opt->max_iterations << AVR32_USART_MR_MAX_ITERATION_OFFSET;
00603
00604
00605 usart_iso7816_enable_receiver(usart);
00606
00607 return USART_SUCCESS;
00608 }
00609
00610
00611 #if defined(AVR32_USART_400_H_INCLUDED) || \
00612 defined(AVR32_USART_410_H_INCLUDED) || \
00613 defined(AVR32_USART_420_H_INCLUDED) || \
00614 defined(AVR32_USART_440_H_INCLUDED) || \
00615 defined(AVR32_USART_602_H_INCLUDED)
00616
00617
00618 int usart_init_lin_master(volatile avr32_usart_t *usart, unsigned long baudrate, long pba_hz)
00619 {
00620
00621 usart_reset(usart);
00622
00623
00624 if (usart_set_async_baudrate(usart, baudrate, pba_hz) == USART_INVALID_INPUT)
00625 return USART_INVALID_INPUT;
00626
00627 usart->mr |= AVR32_USART_MR_MODE_LIN_MASTER << AVR32_USART_MR_MODE_OFFSET;
00628
00629
00630
00631 usart->cr = AVR32_USART_CR_RXEN_MASK |
00632 AVR32_USART_CR_TXEN_MASK;
00633
00634 return USART_SUCCESS;
00635 }
00636
00637
00638 int usart_init_lin_slave(volatile avr32_usart_t *usart, unsigned long baudrate, long pba_hz)
00639 {
00640
00641 usart_reset(usart);
00642
00643
00644 if (usart_set_async_baudrate(usart, baudrate, pba_hz) == USART_INVALID_INPUT)
00645 return USART_INVALID_INPUT;
00646
00647 usart->mr |= AVR32_USART_MR_MODE_LIN_SLAVE << AVR32_USART_MR_MODE_OFFSET;
00648
00649
00650
00651 usart->cr = AVR32_USART_CR_RXEN_MASK |
00652 AVR32_USART_CR_TXEN_MASK;
00653
00654 return USART_SUCCESS;
00655 }
00656
00657
00658 int usart_init_spi_master(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz)
00659 {
00660
00661 usart_reset(usart);
00662
00663
00664 if (!opt ||
00665 opt->charlength < 5 || opt->charlength > 9 ||
00666 opt->spimode > 3 ||
00667 opt->channelmode > 3 ||
00668 usart_set_spi_master_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)
00669 return USART_INVALID_INPUT;
00670
00671 if (opt->charlength == 9)
00672 {
00673
00674 usart->mr |= AVR32_USART_MR_MODE9_MASK;
00675 }
00676 else
00677 {
00678
00679 usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;
00680 }
00681
00682 usart->mr |= AVR32_USART_MR_MODE_SPI_MASTER << AVR32_USART_MR_MODE_OFFSET |
00683 ((opt->spimode & 0x1) ^ 0x1) << AVR32_USART_MR_SYNC_OFFSET |
00684 opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET |
00685 (opt->spimode >> 1) << AVR32_USART_MR_MSBF_OFFSET |
00686 AVR32_USART_MR_CLKO_MASK;
00687
00688
00689
00690 usart->cr = AVR32_USART_CR_RXEN_MASK |
00691 AVR32_USART_CR_TXEN_MASK;
00692
00693 return USART_SUCCESS;
00694 }
00695
00696
00697 int usart_init_spi_slave(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz)
00698 {
00699
00700 usart_reset(usart);
00701
00702
00703 if (!opt ||
00704 opt->charlength < 5 || opt->charlength > 9 ||
00705 opt->spimode > 3 ||
00706 opt->channelmode > 3 ||
00707 usart_set_spi_slave_baudrate(usart) == USART_INVALID_INPUT)
00708 return USART_INVALID_INPUT;
00709
00710 if (opt->charlength == 9)
00711 {
00712
00713 usart->mr |= AVR32_USART_MR_MODE9_MASK;
00714 }
00715 else
00716 {
00717
00718 usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;
00719 }
00720
00721 usart->mr |= AVR32_USART_MR_MODE_SPI_SLAVE << AVR32_USART_MR_MODE_OFFSET |
00722 ((opt->spimode & 0x1) ^ 0x1) << AVR32_USART_MR_SYNC_OFFSET |
00723 opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET |
00724 (opt->spimode >> 1) << AVR32_USART_MR_MSBF_OFFSET;
00725
00726
00727
00728 usart->cr = AVR32_USART_CR_RXEN_MASK |
00729 AVR32_USART_CR_TXEN_MASK;
00730
00731 return USART_SUCCESS;
00732 }
00733
00734
00735 #endif // USART rev. >= 4.0.0
00736
00737
00739
00740
00741
00742 #if defined(AVR32_USART_400_H_INCLUDED) || \
00743 defined(AVR32_USART_410_H_INCLUDED) || \
00744 defined(AVR32_USART_420_H_INCLUDED) || \
00745 defined(AVR32_USART_440_H_INCLUDED) || \
00746 defined(AVR32_USART_602_H_INCLUDED)
00747
00748
00751
00752
00753
00754 int usart_spi_selectChip(volatile avr32_usart_t *usart)
00755 {
00756
00757 usart->cr = AVR32_USART_CR_RTSEN_MASK;
00758
00759 return USART_SUCCESS;
00760 }
00761
00762
00763 int usart_spi_unselectChip(volatile avr32_usart_t *usart)
00764 {
00765 int timeout = USART_DEFAULT_TIMEOUT;
00766
00767 do
00768 {
00769 if (!timeout--) return USART_FAILURE;
00770 } while (!usart_tx_empty(usart));
00771
00772
00773 usart->cr = AVR32_USART_CR_RTSDIS_MASK;
00774
00775 return USART_SUCCESS;
00776 }
00777
00778
00780
00781
00782 #endif // USART rev. >= 4.0.0
00783
00784
00785
00788
00789
00790
00791 int usart_send_address(volatile avr32_usart_t *usart, int address)
00792 {
00793
00794 if (!usart_mode_is_multidrop(usart)) return USART_MODE_FAULT;
00795
00796
00797 usart->cr = AVR32_USART_CR_SENDA_MASK;
00798
00799
00800 usart_bw_write_char(usart, address);
00801
00802 return USART_SUCCESS;
00803 }
00804
00805
00806 int usart_write_char(volatile avr32_usart_t *usart, int c)
00807 {
00808 if (usart_tx_ready(usart))
00809 {
00810 usart->thr = (c << AVR32_USART_THR_TXCHR_OFFSET) & AVR32_USART_THR_TXCHR_MASK;
00811 return USART_SUCCESS;
00812 }
00813 else
00814 return USART_TX_BUSY;
00815 }
00816
00817
00818 int usart_putchar(volatile avr32_usart_t *usart, int c)
00819 {
00820 int timeout = USART_DEFAULT_TIMEOUT;
00821
00822 if (c == '\n')
00823 {
00824 do
00825 {
00826 if (!timeout--) return USART_FAILURE;
00827 } while (usart_write_char(usart, '\r') != USART_SUCCESS);
00828
00829 timeout = USART_DEFAULT_TIMEOUT;
00830 }
00831
00832 do
00833 {
00834 if (!timeout--) return USART_FAILURE;
00835 } while (usart_write_char(usart, c) != USART_SUCCESS);
00836
00837 return USART_SUCCESS;
00838 }
00839
00840
00841 int usart_read_char(volatile avr32_usart_t *usart, int *c)
00842 {
00843
00844
00845 if (usart->csr & (AVR32_USART_CSR_OVRE_MASK |
00846 AVR32_USART_CSR_FRAME_MASK |
00847 AVR32_USART_CSR_PARE_MASK))
00848 return USART_RX_ERROR;
00849
00850
00851 if (usart_test_hit(usart))
00852 {
00853 *c = (usart->rhr & AVR32_USART_RHR_RXCHR_MASK) >> AVR32_USART_RHR_RXCHR_OFFSET;
00854 return USART_SUCCESS;
00855 }
00856 else
00857 return USART_RX_EMPTY;
00858 }
00859
00860
00861 int usart_getchar(volatile avr32_usart_t *usart)
00862 {
00863 int c, ret;
00864
00865 while ((ret = usart_read_char(usart, &c)) == USART_RX_EMPTY);
00866
00867 if (ret == USART_RX_ERROR)
00868 return USART_FAILURE;
00869
00870 return c;
00871 }
00872
00873
00874 void usart_write_line(volatile avr32_usart_t *usart, const char *string)
00875 {
00876 while (*string != '\0')
00877 usart_putchar(usart, *string++);
00878 }
00879
00880
00881 int usart_get_echo_line(volatile avr32_usart_t *usart)
00882 {
00883 int rx_char;
00884 int retval = USART_SUCCESS;
00885
00886 while (1)
00887 {
00888 rx_char = usart_getchar(usart);
00889 if (rx_char == USART_FAILURE)
00890 {
00891 usart_write_line(usart, "Error!!!\n");
00892 retval = USART_FAILURE;
00893 break;
00894 }
00895 if (rx_char == '\x03')
00896 {
00897 retval = USART_FAILURE;
00898 break;
00899 }
00900 usart_putchar(usart, rx_char);
00901 if (rx_char == '\r')
00902 {
00903 usart_putchar(usart, '\n');
00904 break;
00905 }
00906 }
00907
00908 return retval;
00909 }
00910
00911