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00046 #include "pm_uc3c.h"
00047
00048 #ifndef AVR32_PM_VERSION_RESETVALUE
00049 #error Cannot use this software module with the current device.
00050 #else
00051 #if AVR32_PM_VERSION_RESETVALUE < 0x400
00052 #error Cannot use this software module with the current device
00053 #endif
00054 #endif
00055
00058
00059
00060 typedef union
00061 {
00062 unsigned long cfdctrl;
00063 avr32_pm_cfdctrl_t CFDCTRL;
00064 } u_avr32_pm_cfdctrl_t;
00065
00066 typedef union
00067 {
00068 unsigned long cpusel;
00069 avr32_pm_cpusel_t CPUSEL;
00070 } u_avr32_pm_cpusel_t;
00071
00072 typedef union
00073 {
00074 unsigned long pbasel;
00075 avr32_pm_pbasel_t PBASEL;
00076 } u_avr32_pm_pbasel_t;
00077
00078 typedef union
00079 {
00080 unsigned long pbbsel;
00081 avr32_pm_pbbsel_t PBBSEL;
00082 } u_avr32_pm_pbbsel_t;
00083
00084 typedef union
00085 {
00086 unsigned long pbcsel;
00087 avr32_pm_pbcsel_t PBCSEL;
00088 } u_avr32_pm_pbcsel_t;
00089
00091
00092
00097 long pm_set_mclk_source(pm_clk_src_t src)
00098 {
00099
00100 AVR32_ENTER_CRITICAL_REGION( );
00101 PM_UNLOCK(AVR32_PM_MCCTRL);
00102 AVR32_PM.mcctrl = src;
00103 AVR32_LEAVE_CRITICAL_REGION( );
00104
00105 return PASS;
00106 }
00107
00108 long pm_config_mainclk_safety(bool cfd, bool final)
00109 {
00110 u_avr32_pm_cfdctrl_t u_avr32_pm_cfdctrl = {AVR32_PM.cfdctrl};
00111
00112
00113 if(AVR32_PM.cfdctrl & AVR32_PM_CFDCTRL_SFV_MASK)
00114 return -1;
00115
00116
00117 AVR32_ENTER_CRITICAL_REGION( );
00118
00119 u_avr32_pm_cfdctrl.CFDCTRL.cfden = cfd;
00120 u_avr32_pm_cfdctrl.CFDCTRL.sfv = final;
00121
00122 PM_UNLOCK(AVR32_PM_CFDCTRL);
00123 AVR32_PM.cfdctrl = u_avr32_pm_cfdctrl.cfdctrl;
00124 AVR32_LEAVE_CRITICAL_REGION( );
00125
00126 return PASS;
00127 }
00128
00129 long pm_set_clk_domain_div(pm_clk_domain_t clock_domain, pm_divratio_t divratio)
00130 {
00131 u_avr32_pm_cpusel_t u_avr32_pm_cpusel = {AVR32_PM.cpusel};
00132
00133
00134
00135
00136
00137
00138
00139 #ifdef AVR32SFW_INPUT_CHECK
00140
00141 if((divratio > PM_CPUSEL_DIVRATIO_MAX)||(divratio < 0))
00142 return -1;
00143 #endif
00144
00145
00146 if(!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK))
00147 return -1;
00148
00149
00150 u_avr32_pm_cpusel.CPUSEL.cpudiv= 1;
00151 u_avr32_pm_cpusel.CPUSEL.cpusel = divratio;
00152 AVR32_ENTER_CRITICAL_REGION( );
00153
00154 PM_UNLOCK(AVR32_PM_CPUSEL + clock_domain*sizeof(avr32_pm_cpusel_t));
00155
00156 *(&(AVR32_PM.cpusel) + clock_domain)= u_avr32_pm_cpusel.cpusel;
00157 AVR32_LEAVE_CRITICAL_REGION( );
00158
00159 return PASS;
00160 }
00161
00162 long pm_disable_clk_domain_div(pm_clk_domain_t clock_domain)
00163 {
00164 u_avr32_pm_cpusel_t u_avr32_pm_cpusel = {AVR32_PM.cpusel};
00165
00166
00167
00168
00169
00170
00171
00172
00173 if(!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK))
00174 return -1;
00175
00176
00177 u_avr32_pm_cpusel.CPUSEL.cpudiv= DISABLE;
00178 AVR32_ENTER_CRITICAL_REGION( );
00179
00180 PM_UNLOCK(AVR32_PM_CPUSEL + clock_domain*sizeof(avr32_pm_cpusel_t));
00181
00182 *(&(AVR32_PM.cpusel) + clock_domain)= u_avr32_pm_cpusel.cpusel;
00183 AVR32_LEAVE_CRITICAL_REGION( );
00184
00185 return PASS;
00186 }
00187
00188 long pm_wait_for_clk_ready(void)
00189 {
00190 unsigned int timeout = PM_POLL_TIMEOUT;
00191 while (!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK))
00192 {
00193 if(--timeout == 0)
00194 return -1;
00195 }
00196 return PASS;
00197 }
00198
00199
00200
00205 long pm_enable_module(unsigned long module)
00206 {
00207 unsigned long domain = module>>5;
00208
00209
00210 unsigned long *regptr = (unsigned long*)(&(AVR32_PM.cpumask) + domain);
00211 unsigned long regvalue;
00212
00213
00214
00215 regvalue = *regptr;
00216
00217 regvalue |= (1<<(module%32));
00218 AVR32_ENTER_CRITICAL_REGION( );
00219
00220 PM_UNLOCK(AVR32_PM_CPUMASK + domain*sizeof(avr32_pm_cpumask_t));
00221
00222 *regptr = regvalue;
00223 AVR32_LEAVE_CRITICAL_REGION( );
00224
00225 return PASS;
00226 }
00227
00228 long pm_disable_module(unsigned long module)
00229 {
00230 unsigned long domain = module>>5;
00231
00232
00233 volatile unsigned long *regptr = (volatile unsigned long*)(&(AVR32_PM.cpumask) + domain);
00234 unsigned long regvalue;
00235
00236
00237
00238 regvalue = *regptr;
00239
00240 regvalue &= ~(1<<(module%32));
00241 AVR32_ENTER_CRITICAL_REGION( );
00242
00243 PM_UNLOCK(AVR32_PM_CPUMASK + domain*sizeof(avr32_pm_cpumask_t));
00244
00245 *regptr = regvalue;
00246 AVR32_LEAVE_CRITICAL_REGION( );
00247
00248 return PASS;
00249 }
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