Definition in file main.c.
#include <string.h>
#include "pm.h"
#include "flashc.h"
#include "gpio.h"
#include "spi.h"
#include "delay.h"
#include "ctrl_access.h"
#include "fsaccess.h"
#include "FreeRTOS.h"
#include "task.h"
#include "serial.h"
#include "navigation.h"
#include "supervisor.h"
#include "shell.h"
#include "cptime.h"
#include "conf_ctrlpanel.h"
#include "conf_at45dbx.h"
#include "conf_sd_mmc_spi.h"
Go to the source code of this file.
Defines | |
#define | AT45DBX_ENABLE_NPCS_PIN(NPCS, unused) {AT45DBX_SPI_NPCS##NPCS##_PIN, AT45DBX_SPI_NPCS##NPCS##_FUNCTION}, |
#define | mainSUPERVISOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) |
Init the microcontroller & the board shared resources. | |
Functions | |
int | main (void) |
1) Initialize the microcontroller and the shared hardware resources of the board. | |
static void | prv_at45dbx_resources_init (void) |
Initialize AT45DBX resources: GPIO, SPI and AT45DBX. | |
static void | prv_clk_gen_start (void) |
static void | prv_sd_mmc_resources_init (void) |
Initializes SD/MMC resources: GPIO, SPI and SD/MMC. | |
void | vApplicationStackOverflowHook (xTaskHandle *pxTask, signed portCHAR *pcTaskName) |
Variables | |
const char *const | pcCtrlPanelVersion = "GCC "__VERSION__" "__DATE__" "__TIME__" ATMEL_CONTROLPANEL_AVR32_UC3_10400"CRLF |
#define AT45DBX_ENABLE_NPCS_PIN | ( | NPCS, | |||
unused | ) | {AT45DBX_SPI_NPCS##NPCS##_PIN, AT45DBX_SPI_NPCS##NPCS##_FUNCTION}, |
Referenced by prv_at45dbx_resources_init().
#define mainSUPERVISOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) |
main | ( | void | ) |
1) Initialize the microcontroller and the shared hardware resources of the board.
2) Launch the Ctrl Panel modules. 3) Start FreeRTOS.
Definition at line 123 of file main.c.
References CP_CPU_SPEED, LUN_ID_AT45DBX_MEM, mainSUPERVISOR_TASK_PRIORITY, prv_at45dbx_resources_init(), prv_clk_gen_start(), prv_sd_mmc_resources_init(), v_cptime_Init(), and vSupervisor_Start().
00124 { 00125 // Disable the WDT. 00126 // wdt_disable(); 00127 00128 //** 00129 //** 1) Initialize the microcontroller and the shared hardware resources of the board. 00130 //** 00131 00132 // switch to external oscillator 0 00133 pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP); 00134 00135 // Initialize the delay driver. 00136 delay_init(CP_CPU_SPEED); 00137 00138 // Init USB & MACB clock. 00139 prv_clk_gen_start(); 00140 00141 // initialize AT45DBX resources: GPIO, SPI and AT45DBX 00142 prv_at45dbx_resources_init(); 00143 00144 #if SD_MMC_SPI_MEM == ENABLE 00145 prv_sd_mmc_resources_init(); 00146 #endif 00147 00148 // Setup the LED's for output. 00149 LED_Off( LED0 ); LED_Off( LED1 ); LED_Off( LED2 ); LED_Off( LED3 ); 00150 LED_Off( LED4 ); LED_Off( LED5 ); LED_Off( LED6 ); LED_Off( LED7 ); 00151 // vParTestInitialise(); 00152 00153 // Init the memory module. 00154 if( FALSE == ctrl_access_init() ) 00155 { 00156 // TODO: Add msg on LCD. 00157 // gpio_clr_gpio_pin( 60 ); 00158 while( 1 ); 00159 } 00160 00161 /* check if the AT45DBX mem is OK */ 00162 while( CTRL_GOOD != mem_test_unit_ready( LUN_ID_AT45DBX_MEM ) ) 00163 { 00164 // TODO: Add msg on LCD. 00165 // gpio_clr_gpio_pin( 61 ); 00166 } 00167 00168 // Init the FAT navigation module. 00169 if( FALSE == b_fsaccess_init() ) 00170 { 00171 // TODO: Add msg on LCD. 00172 // gpio_clr_gpio_pin( 62 ); 00173 while( 1 ); 00174 } 00175 00176 // Init the time module. 00177 v_cptime_Init(); 00178 00179 //** 00180 //** 2) Launch the Control Panel supervisor task that will in turn create all 00181 //** the necessary tasks. 00182 //** 00183 vSupervisor_Start( mainSUPERVISOR_TASK_PRIORITY ); 00184 00185 //** 00186 //** 3) Start FreeRTOS. 00187 //** 00188 // Use preemptive scheduler define configUSE_PREEMPTION as 1 in portmacro.h 00189 vTaskStartScheduler(); 00190 00191 /* Should never reach this point so why not returning the meaning of life. */ 00192 return 42; 00193 }
static void prv_at45dbx_resources_init | ( | void | ) | [static] |
Initialize AT45DBX resources: GPIO, SPI and AT45DBX.
Definition at line 200 of file main.c.
References AT45DBX_ENABLE_NPCS_PIN, AT45DBX_MEM_CNT, AT45DBX_SPI_BITS, AT45DBX_SPI_FIRST_NPCS, AT45DBX_SPI_MASTER_SPEED, and CP_PBA_SPEED.
Referenced by main().
00201 { 00202 static const gpio_map_t AT45DBX_SPI_GPIO_MAP = 00203 { 00204 {AT45DBX_SPI_SCK_PIN, AT45DBX_SPI_SCK_FUNCTION }, // SPI Clock. 00205 {AT45DBX_SPI_MISO_PIN, AT45DBX_SPI_MISO_FUNCTION }, // MISO. 00206 {AT45DBX_SPI_MOSI_PIN, AT45DBX_SPI_MOSI_FUNCTION }, // MOSI. 00207 #define AT45DBX_ENABLE_NPCS_PIN(NPCS, unused) \ 00208 {AT45DBX_SPI_NPCS##NPCS##_PIN, AT45DBX_SPI_NPCS##NPCS##_FUNCTION}, // Chip Select NPCS. 00209 MREPEAT(AT45DBX_MEM_CNT, AT45DBX_ENABLE_NPCS_PIN, ~) 00210 #undef AT45DBX_ENABLE_NPCS_PIN 00211 }; 00212 00213 // SPI options. 00214 spi_options_t spiOptions = 00215 { 00216 .reg = AT45DBX_SPI_FIRST_NPCS, // Defined in conf_at45dbx.h. 00217 .baudrate = AT45DBX_SPI_MASTER_SPEED, // Defined in conf_at45dbx.h. 00218 .bits = AT45DBX_SPI_BITS, // Defined in conf_at45dbx.h. 00219 .spck_delay = 0, 00220 .trans_delay = 0, 00221 .stay_act = 1, 00222 .spi_mode = 0, 00223 .modfdis = 1 00224 }; 00225 00226 // Assign I/Os to SPI. 00227 gpio_enable_module(AT45DBX_SPI_GPIO_MAP, 00228 sizeof(AT45DBX_SPI_GPIO_MAP) / sizeof(AT45DBX_SPI_GPIO_MAP[0])); 00229 00230 // If the SPI used by the AT45DBX is not enabled. 00231 if (!spi_is_enabled(AT45DBX_SPI)) 00232 { 00233 // Initialize as master. 00234 spi_initMaster(AT45DBX_SPI, &spiOptions); 00235 00236 // Set selection mode: variable_ps, pcs_decode, delay. 00237 spi_selectionMode(AT45DBX_SPI, 0, 0, 0); 00238 00239 // Enable SPI. 00240 spi_enable(AT45DBX_SPI); 00241 } 00242 00243 // Initialize data flash with SPI clock Osc0. 00244 at45dbx_init(spiOptions, CP_PBA_SPEED); 00245 }
static void prv_clk_gen_start | ( | void | ) | [static] |
Start the generation of a 48-MHz clock for the USB
USB
MACB
Reduce speed Bus.
Definition at line 302 of file main.c.
Referenced by main().
00303 { 00304 volatile avr32_pm_t *pm = &AVR32_PM; 00305 00307 #ifdef USB_ENABLE 00308 // Set PLL1 @ 96 MHz from Osc0: 12MHz*(7+1)/1 = 96MHz 00309 // In order to work, we need to go above 80MHz, then divide. 00310 pm_pll_setup(pm, 1, // pll 00311 7, // mul 00312 1, // div 00313 0, // osc 00314 16); // lockcount 00315 00316 pm_pll_set_option( pm, 1, // pll1 00317 1, // Choose the range 80-180MHz. 00318 1, // div2 00319 0 ); // wbwdisable 00320 00321 // Enable PLL1 00322 pm_pll_enable(pm, 1); 00323 00324 // Wait for PLL1 locked 00325 pm_wait_for_pll1_locked(pm); 00326 00327 // Setup USB GCLK 00328 pm_gc_setup(pm, AVR32_PM_GCLK_USBB, // gc 00329 1, // osc_or_pll: use Osc (if 0) or PLL (if 1) 00330 1, // pll_osc: select Osc0/PLL0 or Osc1/PLL1 00331 0, // diven 00332 0); // div 00333 00334 // Enable USB GCLK 00335 pm_gc_enable(pm, AVR32_PM_GCLK_USBB); 00336 #endif 00337 00338 00340 #if CP_CPU_SPEED == 60000000 00341 00342 /* Setup PLL0 on OSC0, mul+1=10 ,divisor by 1, lockcount=16, ie. 12Mhzx10/1 = 120MHz output. 00343 Extra div by 2 => 60MHz */ 00344 pm_pll_setup(pm, // volatile avr32_pm_t* pm 00345 0, // unsigned int pll 00346 9, // unsigned int mul 00347 1, // unsigned int div: Sel Osc0/PLL0 or Osc1/Pll1 00348 0, // unsigned int osc 00349 16); // unsigned int lockcount 00350 00351 pm_pll_set_option( pm, 0, // pll0 00352 1, // Choose the range 80-180MHz. 00353 1, // div2 00354 0 ); // wbwdisable 00355 00356 /* Enable PLL0 */ 00357 pm_pll_enable(pm,0); 00358 00359 /* Wait for PLL0 locked. */ 00360 pm_wait_for_pll0_locked(pm) ; 00361 #endif 00362 00363 #if (CP_PBA_SPEED == 27000000) && (CP_CPU_SPEED == 54000000) 00364 00365 // Set divider to 4 for PBA bus (so that PBA_SPEED == 108/2pow(sel+1) == 27), 00366 // to 2 for PBB and HSB (so that HSB_SPEED == 108/2pow(sel+1) == 54. 00367 // Note that HSB_SPEED == CPU_SPEED always. 00368 pm_cksel(pm,1,1,1,0,1,0); 00369 #elif (CP_PBA_SPEED == 15000000) && (CP_CPU_SPEED == 60000000) 00370 00371 // Set divider to 4 for PBA bus (so that PBA_SPEED == 60/2pow(sel+1) == 15). 00372 // Note that HSB_SPEED == CPU_SPEED always. 00373 pm_cksel(pm,1,1,0,0,0,0); 00374 #endif 00375 00376 #if CP_CPU_SPEED > 33000000 00377 /* Add one wait state for flash management. */ 00378 flashc_set_wait_state(1); 00379 00380 /* switch to clock. */ 00381 pm_switch_to_clock(pm, AVR32_PM_MCCTRL_MCSEL_PLL0); 00382 #endif 00383 }
static void prv_sd_mmc_resources_init | ( | void | ) | [static] |
Initializes SD/MMC resources: GPIO, SPI and SD/MMC.
Definition at line 252 of file main.c.
References CP_PBA_SPEED, SD_MMC_SPI_BITS, and SD_MMC_SPI_MASTER_SPEED.
Referenced by main().
00253 { 00254 static const gpio_map_t SD_MMC_SPI_GPIO_MAP = 00255 { 00256 {SD_MMC_SPI_SCK_PIN, SD_MMC_SPI_SCK_FUNCTION }, // SPI Clock. 00257 {SD_MMC_SPI_MISO_PIN, SD_MMC_SPI_MISO_FUNCTION}, // MISO. 00258 {SD_MMC_SPI_MOSI_PIN, SD_MMC_SPI_MOSI_FUNCTION}, // MOSI. 00259 {SD_MMC_SPI_NPCS_PIN, SD_MMC_SPI_NPCS_FUNCTION} // Chip Select NPCS. 00260 }; 00261 00262 // SPI options. 00263 spi_options_t spiOptions = 00264 { 00265 .reg = SD_MMC_SPI_NPCS, 00266 .baudrate = SD_MMC_SPI_MASTER_SPEED, // Defined in conf_sd_mmc_spi.h. 00267 .bits = SD_MMC_SPI_BITS, // Defined in conf_sd_mmc_spi.h. 00268 .spck_delay = 0, 00269 .trans_delay = 0, 00270 .stay_act = 1, 00271 .spi_mode = 0, 00272 .modfdis = 1 00273 }; 00274 00275 // Assign I/Os to SPI. 00276 gpio_enable_module(SD_MMC_SPI_GPIO_MAP, 00277 sizeof(SD_MMC_SPI_GPIO_MAP) / sizeof(SD_MMC_SPI_GPIO_MAP[0])); 00278 00279 // If the SPI used by the SD/MMC is not enabled. 00280 if (!spi_is_enabled(SD_MMC_SPI)) 00281 { 00282 // Initialize as master. 00283 spi_initMaster(SD_MMC_SPI, &spiOptions); 00284 00285 // Set selection mode: variable_ps, pcs_decode, delay. 00286 spi_selectionMode(SD_MMC_SPI, 0, 0, 0); 00287 00288 // Enable SPI. 00289 spi_enable(SD_MMC_SPI); 00290 } 00291 00292 // Initialize SD/MMC with SPI clock Osc0. 00293 sd_mmc_spi_init(spiOptions, CP_PBA_SPEED); 00294 }
void vApplicationStackOverflowHook | ( | xTaskHandle * | pxTask, | |
signed portCHAR * | pcTaskName | |||
) |
const char* const pcCtrlPanelVersion = "GCC "__VERSION__" "__DATE__" "__TIME__" ATMEL_CONTROLPANEL_AVR32_UC3_10400"CRLF |
The Ctrl Panel sw version.
Definition at line 100 of file main.c.
Referenced by e_syscmds_version().