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00047 #ifndef _NF_H_
00048 #define _NF_H_
00049
00050
00051
00052 #include "conf_nf.h"
00053 #include "board.h"
00054 #include "gpio.h"
00055 #include "ecchrs.h"
00056 #include "nf.h"
00057
00058 #undef _GLOBEXT_
00059 #if (defined _NF_DRV_C_)
00060 # define _GLOBEXT_
00061 #else
00062 # define _GLOBEXT_ extern
00063 #endif
00064
00065
00066
00067
00068 #define AVR32_EBI_NAND_FLASH_ADDRESS AVR32_EBI_CS3_ADDRESS
00069
00072 #if __GNUC__
00073 __attribute__((__always_inline__))
00074 #endif
00075 static __inline__ U8 nf_rd_data( void )
00076 {
00077 volatile unsigned char *p_data = ((volatile unsigned char *)AVR32_EBI_NAND_FLASH_ADDRESS);
00078 return *p_data;
00079 }
00080
00083 #if __GNUC__
00084 __attribute__((__always_inline__))
00085 #endif
00086 static __inline__ void nf_wr_data( U8 data )
00087 {
00088 volatile unsigned char *p_data = ((volatile unsigned char *)AVR32_EBI_NAND_FLASH_ADDRESS);
00089 *p_data=data;
00090 }
00091
00094 #if __GNUC__
00095 __attribute__((__always_inline__))
00096 #endif
00097 static __inline__ void nf_send_nop( void )
00098 {
00099
00100 volatile unsigned char *p_nop = (volatile unsigned char *)AVR32_EBI_CS0_ADDRESS;
00101 *p_nop = 0;
00102 }
00103
00108 #if __GNUC__
00109 __attribute__((__always_inline__))
00110 #endif
00111 static __inline__ void nf_wr_addr(U8 addr)
00112 {
00113 volatile int A;
00114 volatile unsigned char *p_ale = ((volatile unsigned char *)AVR32_EBI_NAND_FLASH_ADDRESS + 0x00400000);
00115 A=0;
00116 *p_ale = addr;
00117 A=0;
00118 nf_send_nop();
00119 }
00120
00125 #if __GNUC__
00126 __attribute__((__always_inline__))
00127 #endif
00128 static __inline__ void nf_wr_cmd(U8 cmd)
00129 {
00130 volatile int A;
00131 volatile unsigned char *p_cle = ((volatile unsigned char *)AVR32_EBI_NAND_FLASH_ADDRESS + 0x00200000);
00132 A=0;
00133 *p_cle = cmd;
00134 A=0;
00135 nf_send_nop();
00136 }
00137
00142 #if __GNUC__
00143 __attribute__((__always_inline__))
00144 #endif
00145 static __inline__ void nf_select(U8 dev)
00146 {
00147 if( dev==0 )
00148 {
00149 #if (NF_N_DEVICES==2) || (NF_N_DEVICES==4)
00150
00151 gpio_set_gpio_pin(NF_DEV_1_CS_PIN);
00152 # if (NF_N_DEVICES==4)
00153 gpio_set_gpio_pin(NF_DEV_2_CS_PIN);
00154 gpio_set_gpio_pin(NF_DEV_3_CS_PIN);
00155 # endif
00156 #endif
00157
00158 gpio_clr_gpio_pin(NF_DEV_0_CS_PIN);
00159 }
00160 #if (NF_N_DEVICES==2) || (NF_N_DEVICES==4)
00161 else if( dev==1 )
00162 {
00163
00164 gpio_set_gpio_pin(NF_DEV_0_CS_PIN);
00165 # if (NF_N_DEVICES==4)
00166 gpio_set_gpio_pin(NF_DEV_2_CS_PIN);
00167 gpio_set_gpio_pin(NF_DEV_3_CS_PIN);
00168 # endif
00169
00170 gpio_clr_gpio_pin(NF_DEV_1_CS_PIN);
00171 }
00172 # if (NF_N_DEVICES==4)
00173 else if( dev==2 )
00174 {
00175
00176 gpio_set_gpio_pin(NF_DEV_0_CS_PIN);
00177 gpio_set_gpio_pin(NF_DEV_1_CS_PIN);
00178 gpio_set_gpio_pin(NF_DEV_3_CS_PIN);
00179
00180
00181 gpio_clr_gpio_pin(NF_DEV_2_CS_PIN);
00182 }
00183 else if( dev==3 )
00184 {
00185
00186 gpio_set_gpio_pin(NF_DEV_0_CS_PIN);
00187 gpio_set_gpio_pin(NF_DEV_1_CS_PIN);
00188 gpio_set_gpio_pin(NF_DEV_2_CS_PIN);
00189
00190
00191 gpio_clr_gpio_pin(NF_DEV_3_CS_PIN);
00192 }
00193 # endif
00194 #endif
00195 }
00196
00197 #warning Update for full NF support.
00198 #define nf_force_CE()
00199 #define nf_unforce_CE()
00200
00201
00202
00204
00205
00206
00207
00208
00209
00210
00211
00212
00213
00214
00215
00216
00217
00218
00219
00220
00221
00222
00224 #define M_ID_MICRON 0x2C
00225 #define M_ID_HYNIX 0xAD
00226 #define M_ID_SANDISK 0x98
00227 #define M_ID_ST 0x20
00228 #define M_ID_TOSHIBA 0x98
00229 #define M_ID_TOSHIBA96 0x96
00230 #define M_ID_SAMSUNG 0xEC
00231 #define M_ID_INFINEON 0xC1
00232
00233
00234
00235
00236 typedef struct {
00237 U8 manuf;
00238 U8 dev;
00239 U8 conf;
00240 } St_nf_id;
00241
00242
00243 typedef struct {
00244 U8 dev_id;
00245 U8 nb_zones;
00246 }St_nf_link_id_block;
00247
00248
00249 typedef struct {
00250 U8 copy_back_cont :4;
00251 U8 copy_back_discont:4;
00252 U8 cache_program :1;
00253 U8 ce_low :1;
00254 U8 timing_read :1;
00255 U8 dfc_nfc_clock :5;
00256 } St_nf_conf;
00257
00258
00259
00260
00261 #define NF_BAD_CONFIG FALSE
00262 #define NF_GENERIC_DRIVER FALSE // TRUE configuration is not possible
00263 #define NF_SHIFT_SECTOR_BYTE 9 // (1<<n) size of sector, unit in bytes (other value not supported)
00264
00265 #if (!defined NF_AUTO_DETECT_2KB)
00266 # define NF_AUTO_DETECT_2KB FALSE
00267 #endif
00268 #if (!defined NF_AUTO_DETECT_512B)
00269 # define NF_AUTO_DETECT_512B FALSE
00270 #endif
00271 #if (NF_AUTO_DETECT_2KB==TRUE) && (NF_AUTO_DETECT_512B==TRUE)
00272 # undef NF_BAD_CONFIG
00273 # define NF_BAD_CONFIG (TRUE)
00274 # error NF_AUTO_DETECT_2KB and NF_AUTO_DETECT_512B can not be activated at the same time.
00275 #endif
00276
00277 #include "nf_512B.h"
00278 #include "nf_2KB.h"
00279
00280
00281
00282 #if (NF_AUTO_DETECT_2KB==TRUE) && (NF_TYPE_512B_KNOWN==TRUE)
00283 # undef NF_BAD_CONFIG
00284 # define NF_BAD_CONFIG (TRUE)
00285 # error NF_AUTO_DETECT_2KB and NF_TYPE_x 512B can not be activated at the same time.
00286 #endif
00287 #if (NF_AUTO_DETECT_512B==TRUE) && (NF_TYPE_2KB_KNOWN==TRUE)
00288 # undef NF_BAD_CONFIG
00289 # define NF_BAD_CONFIG (TRUE)
00290 # error NF_AUTO_DETECT_512B and NF_TYPE_x 2KB can not be activated at the same time.
00291 #endif
00292 #if (NF_AUTO_DETECT_2KB==FALSE) && (NF_AUTO_DETECT_512B==FALSE)
00293 # define NF_DETECTION_ID (DISABLE)
00294 # if (NF_TYPE_2KB_KNOWN ==FALSE) && (NF_TYPE_512B_KNOWN ==FALSE)
00295 # undef NF_BAD_CONFIG
00296 # define NF_BAD_CONFIG (TRUE)
00297 # error No NandFlash configuration found (NF_AUTO_DETECT_2KB, NF_AUTO_DETECT_512B, NF_TYPE_x)
00298 # endif
00299 #else
00300 # define NF_DETECTION_ID (ENABLE)
00301 #endif
00302
00303
00304
00305
00306
00307
00308 #if 0
00309
00314 #define Nfc_set_read_timing(x) (NFCON = (NFCON & ~MSK_NFCON_TRS) | ((x<<4)&MSK_NFCON_TRS))
00315
00316 #define Nfc_spzone_enable() (NFCON |= MSK_NFCON_SPZEN)
00317 #define Nfc_spzone_disable() (NFCON &= ~MSK_NFCON_SPZEN)
00318
00319 #define Nfc_ecc_enable() (NFCON |= MSK_NFCON_ECCEN)
00320 #define Nfc_ecc_disable() (NFCON &= ~MSK_NFCON_ECCEN)
00321
00322 #define Nfc_enable() (NFCON |= MSK_NFCON_EN)
00323 #define Nfc_disable() (NFCON &= ~MSK_NFCON_EN)
00324
00325
00326
00327 #define Nfc_get_err() (NFERR)
00328 #define SHERRID_OK 0
00329 #define SHERRID_CORRECTABLE 4
00330 #define SHERRID_UNCORRECTABLE 8
00331 #define SHERRID_BAD_CRC 0xC
00332 #define Nfc_sherr(x) ((x)&0x0C) // Second half group error id
00333 #define Nfc_shfb(x) (((x)>>3) &7) // Second half group fail bit
00334
00335 #define FHERRID_OK 0
00336 #define FHERRID_CORRECTABLE 1
00337 #define FHERRID_UNCORRECTABLE 2
00338 #define FHERRID_BAD_CRC 3
00339 #define Nfc_fherr(x) ((x)&0x03) // First half group error id
00340 #define Nfc_fhfb(x) ((x)&7 ) // First half group fail bit
00341
00345 #define NFC_ACT_NOP 0
00346 #define NFC_ACT_DEV_SELECT 1
00347 #define NFC_ACT_READ 2
00348 #define NFC_ACT_WRITE 3
00349 #define NFC_ACT_ASSERT_CE 4
00350 # define NFC_EXT_CELOW 1
00351 # define NFC_EXT_NOP 0
00352 #define NFC_ACT_STOP 5
00353 #define NFC_ACT_ADC_EXT 6
00354
00355
00357 #define Nfc_action(act, ext) \
00358 ( NFACT = \
00359 ((ext)<<3) & MSK_NFACT_EXT \
00360 | (act) & MSK_NFACT_ACT )
00361
00362
00363
00364
00365 #define Nfc_wr_data(data) (NFDAT = (data) )
00366 #define Nfc_rd_data() (NFDAT )
00367 #define Nfc_rd_data_fetch_next() (NFDATF )
00368 #define Nfc_rd_status() (NFADC )
00369
00370
00371
00372
00373
00374 #define Is_nfc_running() ( NFC_RUN )
00375 #define Is_nfc_smc_locked() ( NFC_SMLCK )
00376 #define Is_nfc_smc_detected() ( NFC_SMCD )
00377 #define Is_nfc_end_of_page() ( NFC_EOP )
00378
00379
00380
00381
00382 #define Nfc_get_ecc() (NFECC )
00383 #define Nfc_init_ecc() (NFECC=0)
00384 #define Nfc_get_n_ecc() ((NFSTA & MSK_NFSTA_NECC)>>1 )
00385 #define Nfc_get_bpos() (((U16)NFBPH<<8) | NFBPL)
00386
00387
00388
00389
00390
00391 #define Is_nfc_it_stop() (NFINT & MSK_NFINT_STOPI )
00392 #define Is_nfc_it_ecc_err() (NFINT & MSK_NFINT_ECCERRI)
00393 #define Is_nfc_it_ecc_rdy() (NFINT & MSK_NFINT_ECCRDYI)
00394 #define Is_nfc_it_illegal() (NFINT & MSK_NFINT_ILGLI )
00395 #define Is_nfc_it_smc_transtion() (NFINT & MSK_NFINT_SMCTI )
00396
00397
00398 #define Nfc_clear_it_all() (NFINT = 0 )
00399 #define Nfc_set_it_stop() (NFINT |= MSK_NFINT_STOPI )
00400 #define Nfc_clear_it_stop() (NFINT &= ~MSK_NFINT_STOPI )
00401 #define Nfc_clear_it_ecc_err() (NFINT &= ~MSK_NFINT_ECCERRI)
00402 #define Nfc_clear_it_ecc_rdy() (NFINT &= ~MSK_NFINT_ECCRDYI)
00403 #define Nfc_clear_it_illegal() (NFINT &= ~MSK_NFINT_ILGLI )
00404 #define Nfc_clear_it_smc_transtion() (NFINT &= ~MSK_NFINT_SMCTI )
00405
00406
00407 #define Nfc_enable_it_stop() (NFIEN |= MSK_NFIEN_STOPE )
00408 #define Nfc_enable_it_ecc_err() (NFIEN |= MSK_NFIEN_ECCERRE)
00409 #define Nfc_enable_it_ecc_rdy() (NFIEN |= MSK_NFIEN_ECCRDYE)
00410 #define Nfc_enable_it_illegal() (NFIEN |= MSK_NFIEN_ILGLE )
00411 #define Nfc_enable_it_smc_transtion() (NFIEN |= MSK_NFIEN_SMCTE )
00412
00413
00414 #define Nfc_disable_it_all() (NFIEN = 0 )
00415 #define Nfc_disable_it_stop() (NFIEN &= ~MSK_NFIEN_STOPE )
00416 #define Nfc_disable_it_ecc_err() (NFIEN &= ~MSK_NFIEN_ECCERRE)
00417 #define Nfc_disable_it_ecc_rdy() (NFIEN &= ~MSK_NFIEN_ECCRDYE)
00418 #define Nfc_disable_it_illegal() (NFIEN &= ~MSK_NFIEN_ILGLE )
00419 #define Nfc_disable_it_smc_transtion() (NFIEN &= ~MSK_NFIEN_SMCTE )
00420
00421
00422
00425 # define Nfc_mode_manual() ( Nfc_spzone_disable(), Nfc_ecc_disable(), Nfc_disable_it_ecc_rdy() )
00426
00429 # define Nfc_mode_auto() ( Nfc_spzone_enable() , Nfc_ecc_enable() , Nfc_disable_it_ecc_rdy() )
00430
00435 # define Nfc_mode_ecc_manual() ( Nfc_spzone_disable(), Nfc_ecc_enable() , Nfc_enable_it_ecc_rdy() )
00436
00437 #endif
00438
00439
00440
00450 #define Nf_open_page_read( page_addr, byte_addr) \
00451 if ( Is_nf_512() ) \
00452 { \
00453 if ( (byte_addr)<256 ) \
00454 { \
00455 nf_wr_cmd(NF_READ_A_AREA_CMD); \
00456 nf_wr_addr( LSB( byte_addr) ); \
00457 nf_wr_addr( LSB0(page_addr) ); \
00458 nf_force_CE(); \
00459 nf_wr_addr( LSB1(page_addr) ); \
00460 if ( 3==G_N_ROW_CYCLES ) \
00461 { \
00462 nf_wr_addr( MSB1(page_addr) ); \
00463 } \
00464 nf_wait_busy(); \
00465 if(G_CE_LOW) \
00466 { nf_unforce_CE();} \
00467 } \
00468 else if ( (byte_addr)<512 ) \
00469 { \
00470 nf_wr_cmd(NF_READ_B_AREA_CMD); \
00471 nf_wr_addr( LSB( byte_addr) ); \
00472 nf_wr_addr( LSB0(page_addr) ); \
00473 nf_force_CE(); \
00474 nf_wr_addr( LSB1(page_addr) ); \
00475 if ( 3==G_N_ROW_CYCLES ) \
00476 { \
00477 nf_wr_addr( MSB1(page_addr) ); \
00478 } \
00479 nf_wait_busy(); \
00480 if(G_CE_LOW) \
00481 { nf_unforce_CE();} \
00482 } \
00483 else \
00484 { \
00485 nf_wr_cmd(NF_READ_C_AREA_CMD); \
00486 nf_wr_addr( LSB( byte_addr) ); \
00487 nf_wr_addr( LSB0(page_addr) ); \
00488 nf_force_CE(); \
00489 nf_wr_addr( LSB1(page_addr) ); \
00490 if ( 3==G_N_ROW_CYCLES ) \
00491 { \
00492 nf_wr_addr( MSB1(page_addr) ); \
00493 } \
00494 nf_wait_busy(); \
00495 if(G_CE_LOW) \
00496 { nf_unforce_CE();} \
00497 } \
00498 } \
00499 if ( Is_nf_2k() ) \
00500 { \
00501 nf_wr_cmd(NF_READ_CMD); \
00502 nf_wr_addr( LSB( byte_addr) ); \
00503 nf_wr_addr( MSB( byte_addr) ); \
00504 nf_wr_addr( LSB0(page_addr) ); \
00505 nf_wr_addr( LSB1(page_addr) ); \
00506 if ( 3==G_N_ROW_CYCLES ) \
00507 { \
00508 nf_wr_addr( MSB1(page_addr) ); \
00509 } \
00510 nf_wr_cmd(NF_READ_CMD2); \
00511 nf_wait_busy(); \
00512 } \
00513 nf_wr_cmd(NF_READ_CMD);
00514
00515
00516
00526 #define Nf_open_page_write( page_addr, byte_addr) \
00527 Nf_wait_cache_busy(); \
00528 \
00529 if ( Is_nf_512() ) \
00530 { \
00531 if ( (byte_addr)<256 ) \
00532 { \
00533 nf_wr_cmd(NF_READ_A_AREA_CMD); \
00534 nf_wr_cmd(NF_SEQUENTIAL_DATA_INPUT_CMD); \
00535 nf_wr_addr( LSB( byte_addr) ); \
00536 nf_wr_addr( LSB0(page_addr) ); \
00537 nf_wr_addr( LSB1(page_addr) ); \
00538 if ( 3==G_N_ROW_CYCLES ) \
00539 { \
00540 nf_wr_addr( MSB1(page_addr) ); \
00541 } \
00542 } \
00543 else if ( (byte_addr)<512 ) \
00544 { \
00545 nf_wr_cmd(NF_READ_B_AREA_CMD); \
00546 nf_wr_cmd(NF_SEQUENTIAL_DATA_INPUT_CMD); \
00547 nf_wr_addr( LSB( byte_addr) ); \
00548 nf_wr_addr( LSB0(page_addr) ); \
00549 nf_wr_addr( LSB1(page_addr) ); \
00550 if ( 3==G_N_ROW_CYCLES ) \
00551 { \
00552 nf_wr_addr( MSB1(page_addr) ); \
00553 } \
00554 } \
00555 else \
00556 { \
00557 nf_wr_cmd(NF_READ_C_AREA_CMD); \
00558 nf_wr_cmd(NF_SEQUENTIAL_DATA_INPUT_CMD); \
00559 nf_wr_addr( LSB( byte_addr) ); \
00560 nf_wr_addr( LSB0(page_addr) ); \
00561 nf_wr_addr( LSB1(page_addr) ); \
00562 if ( 3==G_N_ROW_CYCLES ) \
00563 { \
00564 nf_wr_addr( MSB1(page_addr) ); \
00565 } \
00566 } \
00567 } \
00568 if ( Is_nf_2k() ) \
00569 { \
00570 nf_wr_cmd(NF_SEQUENTIAL_DATA_INPUT_CMD); \
00571 nf_wr_addr( LSB( byte_addr) ); \
00572 nf_wr_addr( MSB( byte_addr) ); \
00573 nf_wr_addr( LSB0(page_addr) ); \
00574 nf_wr_addr( LSB1(page_addr) ); \
00575 if ( 3==G_N_ROW_CYCLES ) \
00576 { \
00577 nf_wr_addr( MSB1(page_addr) ); \
00578 } \
00579 }
00580
00581
00582
00583
00584 #define NF_MAX_DEVICES 4
00585
00587
00588
00589
00590
00591
00592
00593
00597 #define NF_READ_A_AREA_CMD 0x00
00598 #define NF_READ_B_AREA_CMD 0x01
00599 #define NF_READ_C_AREA_CMD 0x50
00600
00601 #define NF_READ_CMD 0x00
00602 #define NF_READ_CMD2 0x30
00603 #define NF_RANDOM_READ_CMD_C1 0x05
00604 #define NF_RANDOM_READ_CMD_C2 0xE0
00605
00606 #define NF_READ_ID_CMD 0x90
00607 #define NF_READ_ID2_CMD 0x91
00608
00609 #define NF_RESET_CMD 0xff
00610
00611 #define NF_SEQUENTIAL_DATA_INPUT_CMD 0x80
00612 #define NF_PAGE_PROGRAM_CMD 0x10
00613
00614 #define NF_RANDOM_DATA_INPUT_CMD 0x85
00615 #define NF_COPY_BACK_CMD 0x35
00616 #define NF_CACHE_PROGRAM_CMD 0x15
00617
00618 #define NF_BLOCK_ERASE_CMD 0x60
00619 #define NF_BLOCK_ERASE_CONFIRM_CMD 0xD0
00620
00621 #define NF_READ_STATUS_CMD 0x70
00622
00623
00624
00625
00629 #define NF_MASK_STATUS_FAIL (1<<0)
00630 #define NF_MASK_STATUS_READY (1<<6)
00631 #define NF_MASK_STATUS_T_RDY_2KB (1<<5)
00632 #define NF_MASK_STATUS_T_RDY_512B (1<<6)
00633
00634
00635
00636
00639 #define Nf_wait_cache_busy() \
00640 { \
00641 ecchrs_freeze(&AVR32_ECCHRS); \
00642 nf_wr_cmd(NF_READ_STATUS_CMD); \
00643 while( (nf_rd_data() & NF_MASK_STATUS_READY)==0 ); \
00644 while( (nf_rd_data() & NF_MASK_STATUS_READY)==0 ); \
00645 ecchrs_unfreeze(&AVR32_ECCHRS); \
00646 }
00647
00648 #define SIZE_PAGE_BYTE ((U16)1<<G_SHIFT_PAGE_BYTE)
00649 #define SIZE_SECTOR_BYTE ((U16)1<<S_SHIFT_SECTOR_BYTE)
00650 #define SIZE_BLOCK_PAGE ((U8)1<<G_SHIFT_BLOCK_PAGE)
00651 #define SIZE_PAGE_SECTOR ((U8)1<<(G_SHIFT_PAGE_BYTE - S_SHIFT_SECTOR_BYTE))
00652
00653
00654
00655
00656
00657 #define NFC_SPARE_OFST_1_BLK_ID 1
00658 # define NFC_BLK_ID_SYSTEM 0x39 // System block (Font, screen, firmware, ...)
00659 # define NFC_BLK_ID_SUBLUT 0xE8 // sub-LUT block
00660 # define NFC_BLK_ID_RCV 0x72 // Recovery block
00661 # define NFC_BLK_ID_FBB 0xB4 // Free-blocks block
00662 # define NFC_BLK_ID_DATA 0xFF // Data block (mass storage). Also the default value after an erase
00663 # define NFC_BLK_ID_QUARANTINE 0x8D // Block which encountered an ECC error not recoverable. Not yet bad...
00664
00665 #define NFC_SPARE_OFST_2_BYTE_2 2
00666 #define NFC_SPARE_OFST_3_BYTE_3 3 // NFC_BLK_ID_DATA: used as 'data valid'
00667 # define NFC_OFST_3_DATA_SRC 0x00 // Identify a source block (recovery)
00668 # define NFC_OFST_3_DATA_DST 0xFF // Identify a recipient block (recovery)
00669
00670 #define NFC_SPARE_OFST_4_BYTE_4 4
00671 # define NFC_OFST_4_FBB_DRIVER_RELEASE 0x01 // Current NF release. When a new firmware implies that LUT and FBB must be rebuild, just increment this number.
00672 # define NFC_SPARE_DATA_VALID 0xFF
00673 # define NFC_SPARE_DATA_INVALID 0
00674 #define NFC_SPARE_OFST_EXPORT 11
00675
00676 #define NFC_SPARE_OFST_6_LBA 6 // and 7
00677 # define NFC_OFST_6_FBB_VALID 0xFF
00678 # define NFC_OFST_6_FBB_INVALID 0
00679
00680 #define NFC_SPARE_OFST_ECC2 8 // and 9, 10
00681 #define NFC_SPARE_OFST_ECC1 13 // and 14, 15
00682
00683 #if( NF_BAD_CONFIG==(FALSE) )
00684 # if (NF_GENERIC_DRIVER==TRUE) || (NF_AUTO_DETECT_2KB==TRUE) || (NF_AUTO_DETECT_512B==TRUE)
00685 _GLOBEXT_ _MEM_TYPE_SLOW_ U8 g_n_zones ;
00686 _GLOBEXT_ _MEM_TYPE_SLOW_ U16 g_n_blocks ;
00687 _GLOBEXT_ _MEM_TYPE_FAST_ U8 g_n_row_cycles ;
00688 _GLOBEXT_ _MEM_TYPE_SLOW_ U8 g_copy_back_cont ;
00689 _GLOBEXT_ _MEM_TYPE_SLOW_ U8 g_copy_back_discont;
00690 _GLOBEXT_ Bool g_cache_program ;
00691 _GLOBEXT_ Bool g_ce_low ;
00692 _GLOBEXT_ _MEM_TYPE_SLOW_ U8 g_clock_dfc_nfc ;
00693 _GLOBEXT_ _MEM_TYPE_SLOW_ U8 g_dev_maker ;
00694 _GLOBEXT_ _MEM_TYPE_SLOW_ U8 g_dev_id ;
00695 # define G_N_ZONES g_n_zones
00696 # define G_N_BLOCKS g_n_blocks
00697 # define G_N_ROW_CYCLES g_n_row_cycles
00698 # define G_COPY_BACK_CONT g_copy_back_cont
00699 # define G_COPY_BACK_DISCONT g_copy_back_discont
00700 # define G_CACHE_PROG g_cache_program
00701 # define G_CE_LOW g_ce_low
00702 # define G_CLK_DFC_NFC g_clock_dfc_nfc
00703 # define G_DEV_MAKER g_dev_maker
00704 # define G_DEV_ID g_dev_id
00705 # else
00706 # define G_N_ZONES (NF_N_ZONES)
00707 # define G_N_BLOCKS (NF_N_BLOCKS)
00708 # define G_N_ROW_CYCLES (NF_N_ROW_CYCLES)
00709 # define G_COPY_BACK_CONT (NF_COPYBACK_CONT)
00710 # define G_COPY_BACK_DISCONT (NF_COPYBACK_DISCONT)
00711 # define G_CACHE_PROG (NF_CACHE_PROGRAM)
00712 # define G_CE_LOW (NF_CE_LOW)
00713 # define G_CLK_DFC_NFC (CLK_DFC_NFC)
00714 # define G_DEV_MAKER (NF_DEV_MAKER)
00715 # define G_DEV_ID (NF_DEV_ID)
00716 # endif
00717
00718 # if (NF_GENERIC_DRIVER==TRUE)
00719 _GLOBEXT_ _MEM_TYPE_FAST_ U8 g_shift_page_byte ;
00720 _GLOBEXT_ _MEM_TYPE_FAST_ U8 g_shift_block_page ;
00721 _GLOBEXT_ _MEM_TYPE_SLOW_ U8 g_ofst_blk_status ;
00722 # define Is_nf_2k() (11==g_shift_page_byte )
00723 # define Is_not_nf_2k() (11!=g_shift_page_byte )
00724 # define Is_nf_512() ( 9==g_shift_page_byte )
00725 # define Is_not_nf_512() ( 9!=g_shift_page_byte )
00726 # define G_SHIFT_BLOCK_PAGE g_shift_block_page
00727 # define G_SHIFT_PAGE_BYTE g_shift_page_byte
00728 # define G_OFST_BLK_STATUS g_ofst_blk_status
00729 # define NF_SPARE_POS ( Is_nf_2k() ? 2048 : 512 )
00730 # define NF_N_GOOD_STATIC_BLOCK ( Is_nf_2k() ? 32 : 256 )
00731 #else
00732 # if (NF_SHIFT_PAGE_BYTE==11) // 2KB pages
00733 # define Is_nf_2k() ( TRUE )
00734 # define Is_not_nf_2k() ( FALSE )
00735 # define Is_nf_512() ( FALSE )
00736 # define Is_not_nf_512() ( TRUE )
00737 # define NF_SPARE_POS 2048 // Spare zone starts at this byte offset in the page
00738 # define NF_N_GOOD_STATIC_BLOCK 32 // Number of the *valid* blocks in the static area
00739 # define G_OFST_BLK_STATUS 0 // Offset of the Bad Block information in spare zone
00740 # endif
00741 # if (NF_SHIFT_PAGE_BYTE==9) // 512B pages
00742 # define Is_nf_2k() ( FALSE )
00743 # define Is_not_nf_2k() ( TRUE )
00744 # define Is_nf_512() ( TRUE )
00745 # define Is_not_nf_512() ( FALSE )
00746 # define NF_SPARE_POS 512 // Spare zone starts at this byte offset in the page
00747 # define NF_N_GOOD_STATIC_BLOCK 256 // Number of the *valid* blocks in the static area
00748 # define G_OFST_BLK_STATUS 5 // Offset of the Bad Block information in spare zone
00749 # endif
00750 # define G_SHIFT_BLOCK_PAGE (NF_SHIFT_BLOCK_PAGE)
00751 # define G_SHIFT_PAGE_BYTE (NF_SHIFT_PAGE_BYTE)
00752 # endif
00753
00754 #define G_PROTECT_DEV (NF_PROTECTED_DEVICES)
00755
00756
00757
00758 #endif // NF_BAD_CONFIG
00759
00760
00761
00762
00763
00764
00765
00766
00767 void nf_init( U32 hsb_f_hz );
00768 U8 nf_get_freq( void );
00769 Bool nf_check_status( void );
00770 U8 nf_check_type( U8 nb_dev );
00771 void nf_reset_nands( U8 nb_dev );
00772 void nf_open_page_read( U32 page_addr, U16 byte_addr);
00773 void nf_open_page_write( U32 page_addr, U16 byte_addr);
00774 void nf_mark_bad_block( U32 page_addr );
00775 void nf_erase_block( U32 page_addr, U8 force_erase );
00776 void nf_copy_back_init( U32 page_addr );
00777 void nf_copy_back_conf( U32 page_addr );
00778 U32 nf_read_id( U8 read_id_cmd, U8 nf_num );
00779 U8 nf_detect( void );
00780 void nf_wait_busy( void );
00781 void nf_unprotect( void );
00782 void nf_protect( void );
00783
00784
00785
00786
00787
00788 void nf_read_spare_byte(
00789 U8 _MEM_TYPE_SLOW_ * p_byte
00790 , U8 n_byte
00791 , U32 page_addr
00792 );
00793
00794 void nf_print_block( U16 block_addr, U8 dev_id);
00795
00796 #endif // _NF_H_