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00048 #include "aes.h"
00049
00050
00051
00052 #define AES_CKEY 0xE
00053
00054
00055
00056
00057 void aes_configure( volatile avr32_aes_t *aes, const aes_config_t *pAesConfig )
00058 {
00059 aes->mr = ((pAesConfig->ProcessingMode << AVR32_AES_MR_CIPHER_OFFSET) & AVR32_AES_MR_CIPHER_MASK) |
00060 ((pAesConfig->ProcessingDelay << AVR32_AES_MR_PROCDLY_OFFSET) & AVR32_AES_MR_PROCDLY_MASK) |
00061 ((pAesConfig->StartMode << AVR32_AES_MR_SMOD_OFFSET) & AVR32_AES_MR_SMOD_MASK) |
00062 ((pAesConfig->KeySize << AVR32_AES_MR_KEYSIZE_OFFSET) & AVR32_AES_MR_KEYSIZE_MASK) |
00063 ((pAesConfig->OpMode << AVR32_AES_MR_OPMOD_OFFSET) & AVR32_AES_MR_OPMOD_MASK) |
00064 ((pAesConfig->LodMode << AVR32_AES_MR_LOD_OFFSET) & AVR32_AES_MR_LOD_MASK) |
00065 ((pAesConfig->CFBSize << AVR32_AES_MR_CFBS_OFFSET) & AVR32_AES_MR_CFBS_MASK) |
00066 ((pAesConfig->CounterMeasureMask << AVR32_AES_MR_CTYPE_OFFSET) & AVR32_AES_MR_CTYPE_MASK) |
00067 ((AES_CKEY << AVR32_AES_MR_CKEY_OFFSET) & AVR32_AES_MR_CKEY_MASK);
00068 }
00069
00070
00071 void aes_isr_configure( volatile avr32_aes_t *aes, const aes_isrconfig_t *pAesIsrConfig )
00072 {
00073 Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00074
00075
00076
00077 aes->ier = pAesIsrConfig->datrdy << AVR32_AES_IER_DATRDY_OFFSET |
00078 pAesIsrConfig->urad << AVR32_AES_IER_URAD_OFFSET ;
00079
00080 if (global_interrupt_enabled) Disable_global_interrupt();
00081 aes->idr = (~(pAesIsrConfig->datrdy) & 1) << AVR32_AES_IDR_DATRDY_OFFSET |
00082 (~(pAesIsrConfig->urad) & 1) << AVR32_AES_IDR_URAD_OFFSET ;
00083
00084 if (global_interrupt_enabled) Enable_global_interrupt();
00085 }
00086
00087
00088 unsigned int aes_get_status( volatile avr32_aes_t *aes )
00089 {
00090 return(aes->isr);
00091 }
00092
00093
00094 void aes_set_key( volatile avr32_aes_t *aes, const unsigned int *pKey)
00095 {
00096 unsigned long int volatile *pTempo = &(aes->keyw1r);
00097 unsigned char keylen = 0;
00098
00099
00100 switch((aes->mr & AVR32_AES_MR_KEYSIZE_MASK) >> AVR32_AES_MR_KEYSIZE_OFFSET)
00101 {
00102 case 0:
00103 keylen = 4;
00104 break;
00105 case 1:
00106 keylen = 6;
00107 break;
00108 case 2:
00109 keylen = 8;
00110 break;
00111 default:
00112 break;
00113 }
00114 for( ; keylen > 0; keylen--)
00115 *pTempo++ = *pKey++;
00116 }
00117
00118
00119 void aes_set_initvector( volatile avr32_aes_t *aes, const unsigned int *pVector)
00120 {
00121 unsigned long int volatile *pTempo = &(aes->iv1r);
00122 int i;
00123
00124 for(i=0; i<4; i++)
00125 *pTempo++ = *pVector++;
00126 }
00127
00128
00129 void aes_write_inputdata( volatile avr32_aes_t *aes, const unsigned int *pIn)
00130 {
00131 unsigned long int volatile *pTempo = &(aes->idata1r);
00132 unsigned char inlen = 4;
00133
00134
00135 if(AES_CFB_MODE == ((aes->mr & AVR32_AES_MR_OPMOD_MASK) >> AVR32_AES_MR_OPMOD_OFFSET))
00136 {
00137 switch((aes->mr & AVR32_AES_MR_CFBS_MASK) >> AVR32_AES_MR_CFBS_OFFSET)
00138 {
00139 case 1:
00140 inlen = 2;
00141 break;
00142 case 2:
00143 case 3:
00144 case 4:
00145 inlen = 1;
00146 break;
00147 default:
00148 break;
00149 }
00150 }
00151 for(; inlen > 0; inlen--)
00152 *pTempo++ = *pIn++;
00153 }
00154
00155
00156 void aes_read_outputdata( volatile avr32_aes_t *aes, unsigned int *pOut)
00157 {
00158 unsigned long int const volatile *pTempo = &(aes->odata1r);
00159 unsigned char outlen = 4;
00160
00161
00162 if(AES_CFB_MODE == ((aes->mr & AVR32_AES_MR_OPMOD_MASK) >> AVR32_AES_MR_OPMOD_OFFSET))
00163 {
00164 switch((aes->mr & AVR32_AES_MR_CFBS_MASK) >> AVR32_AES_MR_CFBS_OFFSET)
00165 {
00166 case 1:
00167 outlen = 2;
00168 break;
00169 case 2:
00170 case 3:
00171 case 4:
00172 outlen = 1;
00173 break;
00174 default:
00175 break;
00176 }
00177 }
00178 for(; outlen > 0; outlen--)
00179 *pOut++ = *pTempo++;
00180 }