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00049 #include "compiler.h"
00050
00051
00052
00053
00054 #define _NF_C_
00055
00056 #include "conf_nf.h"
00057 #include "nf.h"
00058 #include "gpio.h"
00059 #include "smc.h"
00060
00061 #if( NF_BAD_CONFIG==(FALSE) )
00062
00063
00064
00065
00066
00067 #if (NF_AUTO_DETECT_2KB==FALSE) && (NF_AUTO_DETECT_512B==FALSE)
00078 U8 nf_check_type( U8 nb_dev )
00079 {
00080 U8 i_dev;
00081
00082
00083 #warning Update for full support.
00084 nf_reset_nands( nb_dev );
00085
00086
00087
00088 for( i_dev=0 ; i_dev<nb_dev ; i_dev++ )
00089 {
00090 nf_select( i_dev );
00091 nf_wait_busy();
00092 nf_force_CE();
00093 nf_wr_cmd(NF_READ_ID_CMD);
00094 nf_wr_addr( 0 );
00095 if(( nf_rd_data()!=G_DEV_MAKER )
00096 || ( nf_rd_data()!=G_DEV_ID ))
00097 {
00098 Assert( FALSE );
00099 return i_dev;
00100 }
00101 if( G_CE_LOW )
00102 {
00103
00104
00105 nf_force_CE();
00106 }
00107 }
00108 return nb_dev;
00109 }
00110 #endif
00111
00112
00117 void nf_reset_nands( U8 nb_dev )
00118 {
00119 U8 i_dev;
00120 for( i_dev=0 ; i_dev<nb_dev ; i_dev++ )
00121 {
00122 nf_select( i_dev );
00123
00124
00125 nf_wait_busy();
00126 nf_wr_cmd(NF_RESET_CMD);
00127 nf_wait_busy();
00128 }
00129 }
00130
00131
00132
00137 void nf_init( U32 hsb_f_hz )
00138 {
00139 static const gpio_map_t SMC_NF_EBI_GPIO_MAP =
00140 {
00141 {ATPASTE2(EBI_NANDOE,_PIN),ATPASTE2(EBI_NANDOE,_FUNCTION)},
00142 {ATPASTE2(EBI_NANDWE,_PIN),ATPASTE2(EBI_NANDWE,_FUNCTION)},
00143 };
00144
00145 gpio_enable_module(SMC_NF_EBI_GPIO_MAP, sizeof(SMC_NF_EBI_GPIO_MAP) / sizeof(SMC_NF_EBI_GPIO_MAP[0]));
00146 smc_init(hsb_f_hz);
00147
00148
00149 AVR32_HMATRIX.sfr[AVR32_EBI_HMATRIX_NR] |= (1 << AVR32_EBI_NAND_CS);
00150
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160 }
00161
00162
00163
00168 U8 nf_get_freq( void )
00169 {
00170 #warning Update for full support.
00171 return 0;
00172
00173 }
00174
00175
00176
00183 Bool nf_check_status( void )
00184 {
00185 U8 data;
00186 nf_wait_busy();
00187
00188 ecchrs_freeze(&AVR32_ECCHRS);
00189 data = nf_rd_data();
00190 ecchrs_unfreeze(&AVR32_ECCHRS);
00191 if ( (data&NF_MASK_STATUS_FAIL)==0 ) { return PASS; }
00192 else { return FAIL; }
00193 }
00194
00204 void nf_open_page_read( U32 page_addr, U16 byte_addr)
00205 {
00206 nf_wait_busy();
00207 Nf_open_page_read( page_addr, byte_addr);
00208 }
00209
00219 void nf_open_page_write( U32 page_addr, U16 byte_addr)
00220 {
00221 Nf_open_page_write( page_addr, byte_addr);
00222 }
00223
00232 void nf_mark_bad_block(U32 page_addr)
00233 {
00234 U8 n_bytes;
00235 U8 i_byte;
00236 U8 i_page;
00237
00238
00239 n_bytes= ( Is_nf_512() )
00240 ? 16
00241 : 64
00242 ;
00243
00244
00245 nf_erase_block( page_addr, TRUE );
00246 for ( i_page=(U8)1<<G_SHIFT_BLOCK_PAGE ; i_page!=0 ; i_page--, page_addr++ )
00247 {
00248 nf_open_page_write( page_addr, NF_SPARE_POS-8 );
00249 nf_wr_data('A'); nf_wr_data('t');
00250 nf_wr_data('m'); nf_wr_data('e');
00251 nf_wr_data('l'); nf_wr_data(' ');
00252 nf_wr_data(' '); nf_wr_data(' ');
00253 for ( i_byte=n_bytes ; i_byte!=0 ; i_byte-=4 )
00254 {
00255 nf_wr_data(0);
00256 nf_wr_data(0);
00257 nf_wr_data(0);
00258 nf_wr_data(0);
00259 }
00260 nf_wr_cmd(NF_PAGE_PROGRAM_CMD);
00261 }
00262 }
00263
00275 void nf_erase_block( U32 page_addr, U8 force_erase )
00276 {
00277 if( FALSE==force_erase )
00278 {
00279 nf_open_page_read( page_addr, NF_SPARE_POS + G_OFST_BLK_STATUS );
00280 if( (nf_rd_data()!=0xFF) ) return;
00281 }
00282 nf_wait_busy();
00283 nf_wr_cmd(NF_BLOCK_ERASE_CMD);
00284 nf_wr_addr( LSB0(page_addr) );
00285 nf_wr_addr( LSB1(page_addr) );
00286 if ( 3==G_N_ROW_CYCLES )
00287 {
00288 nf_wr_addr( MSB1(page_addr) );
00289 }
00290 nf_wr_cmd(NF_BLOCK_ERASE_CONFIRM_CMD);
00291 }
00292
00302 void nfc_read_spare_byte(
00303 U8 _MEM_TYPE_SLOW_ * p_byte
00304 , U8 n_byte
00305 , U32 page_addr)
00306 {
00307 U8 i;
00308
00309 nf_open_page_read( page_addr, NF_SPARE_POS);
00310
00311 for ( i=0 ; i!=n_byte ; i++ )
00312 p_byte[i] = nf_rd_data();
00313 }
00314
00319 void nf_wait_busy( void )
00320 {
00321 ecchrs_freeze(&AVR32_ECCHRS);
00322 nf_wr_cmd(NF_READ_STATUS_CMD);
00323 if( Is_nf_2k() )
00324 {
00325 if( G_CACHE_PROG )
00326 {
00327 while( (nf_rd_data() & NF_MASK_STATUS_T_RDY_2KB )==0 );
00328 while( (nf_rd_data() & NF_MASK_STATUS_T_RDY_2KB )==0 );
00329 }
00330 else
00331 {
00332 while( (nf_rd_data() & NF_MASK_STATUS_READY )==0 );
00333 while( (nf_rd_data() & NF_MASK_STATUS_READY )==0 );
00334 }
00335 }
00336 if( Is_nf_512() )
00337 {
00338 while( (nf_rd_data() & NF_MASK_STATUS_T_RDY_512B )==0 );
00339 while( (nf_rd_data() & NF_MASK_STATUS_T_RDY_512B )==0 );
00340 }
00341 ecchrs_unfreeze(&AVR32_ECCHRS);
00342 }
00343
00344
00345
00359 U32 nf_read_id( U8 read_id_cmd, U8 nf_num )
00360 {
00361 U32 ret;
00362
00363 nf_select( nf_num );
00364 nf_wait_busy();
00365
00366 nf_wr_cmd (read_id_cmd);
00367 nf_wr_addr( 0 );
00368
00369 MSB0(ret)= nf_rd_data();
00370 MSB1(ret)= nf_rd_data();
00371 MSB2(ret)= nf_rd_data();
00372 MSB3(ret)= nf_rd_data();
00373
00374
00375 return ret;
00376 }
00377
00378
00379 #if (NF_DETECTION_ID==ENABLE) || (NF_AUTO_DETECT_2KB==TRUE) || (NF_AUTO_DETECT_512B==TRUE)
00385 static Bool nfc_nf_is_ready( void )
00386 {
00387 U8 u8_timeout;
00388 U8 dummy;
00389 nf_wr_cmd( NF_READ_STATUS_CMD );
00390 dummy = Nfc_rd_status();
00391
00392 for (u8_timeout=NF_MAX_RB_TIMEOUT ; u8_timeout!=0 ; u8_timeout--)
00393 {
00394 if(( (Nfc_rd_status() & NF_MASK_STATUS_READY) !=0 )
00395 && ( (Nfc_rd_status() & NF_MASK_STATUS_READY) !=0 ) )
00396 {
00397 return TRUE;
00398 }
00399 }
00400 return FALSE;
00401 }
00402
00403
00410 U8 nfc_detect( void )
00411 {
00412 U32 u32_nf_ids;
00413 U8 u8_i, u8_conf;
00414
00415
00416 nf_init( NF_MAX_DEVICES, 0 );
00417 nf_reset_nands( NF_MAX_DEVICES );
00418
00419
00420 if ( FALSE == nfc_nf_is_ready() )
00421 return NO_NF_CONNECTED;
00422
00423
00424 u32_nf_ids = nf_read_id( NF_READ_ID_CMD, 0 );
00425
00426
00427 for( u8_i=0 ; u8_i < (sizeof(nf_list_id)/sizeof(St_nf_id)) ; u8_i++)
00428 {
00429 if((nf_list_id[u8_i].manuf == MSB0(u32_nf_ids))
00430 && (nf_list_id[u8_i].dev == MSB1(u32_nf_ids)))
00431 break;
00432 }
00433 if( u8_i == (sizeof(nf_list_id)/sizeof(St_nf_id)) )
00434 return NF_UNKNOW;
00435
00436
00437 #if (NF_GENERIC_DRIVER==TRUE)
00438 # error Test me...
00439 g_shift_page_byte =;
00440 g_shift_block_page =;
00441 #endif
00442
00443 #if (NF_GENERIC_DRIVER==TRUE) || (NF_AUTO_DETECT_2KB==TRUE) ||(NF_AUTO_DETECT_512B==TRUE)
00444
00445
00446 u8_conf = nf_list_id[u8_i].conf;
00447 g_dev_maker = MSB0(u32_nf_ids);
00448 g_dev_id = MSB1(u32_nf_ids);
00449
00450
00451 for( u8_i=0 ; u8_i < (sizeof(nf_list_link_id_block)/sizeof(St_nf_link_id_block)) ; u8_i++)
00452 {
00453 if( nf_list_link_id_block[u8_i].dev_id == g_dev_id )
00454 break;
00455 }
00456 if( u8_i == (sizeof(nf_list_link_id_block)/sizeof(St_nf_link_id_block)) )
00457 while(1);
00458
00459 g_n_zones = nf_list_link_id_block[u8_i].nb_zones;
00460 #if (NF_AUTO_DETECT_2KB==TRUE)
00461 if( 1 == g_n_zones )
00462 g_n_row_cycles = 2;
00463 else
00464 g_n_row_cycles = 3;
00465 #endif
00466 #if (NF_AUTO_DETECT_512B==TRUE)
00467 if( 2 >= g_n_zones )
00468 g_n_row_cycles = 2;
00469 else
00470 g_n_row_cycles = 3;
00471 #endif
00472 g_n_blocks = g_n_zones*1024L;
00473
00474 g_copy_back_cont = nf_list_conf[u8_conf].copy_back_cont ;
00475 g_copy_back_discont = nf_list_conf[u8_conf].copy_back_discont;
00476 g_cache_program = nf_list_conf[u8_conf].cache_program ;
00477 g_ce_low = nf_list_conf[u8_conf].ce_low;
00478 g_clock_dfc_nfc = (nf_list_conf[u8_conf].dfc_nfc_clock<<5) & MSK_DNFCKS;
00479
00480 Nfc_set_read_timing((U8)nf_list_conf[u8_conf].timing_read );
00481 if( g_ce_low )
00482 {
00483 nf_force_CE();
00484 }
00485 #endif
00486 return u8_i;
00487 }
00488
00489 #endif
00490
00497 void nf_copy_back_init( U32 page_addr )
00498 {
00499 nf_wait_busy();
00500 nf_wr_cmd(NF_READ_CMD);
00501 nf_wr_addr( 0 );
00502 nf_wr_addr( 0 );
00503 nf_wr_addr( LSB0(page_addr) );
00504 nf_wr_addr( LSB1(page_addr) );
00505 if ( 3==G_N_ROW_CYCLES )
00506 {
00507 nf_wr_addr( MSB1(page_addr) );
00508 }
00509 nf_wr_cmd(NF_COPY_BACK_CMD);
00510 nf_wait_busy();
00511 }
00512
00513 #if (0)
00520 void nfc_copy_back_conf( U32 page_addr )
00521 {
00522 nf_wait_busy();
00523 nf_wr_cmd(NF_RANDOM_DATA_INPUT_CMD);
00524 nf_wr_addr( 0 );
00525 nf_wr_addr( 0 );
00526 nf_wr_addr( LSB0(page_addr) );
00527 nf_wr_addr( LSB1(page_addr) );
00528 if ( 3==G_N_ROW_CYCLES )
00529 {
00530 nf_wr_addr( MSB1(page_addr) );
00531 }
00532 nf_wr_cmd(NF_PAGE_PROGRAM_CMD);
00533 }
00534 #endif
00535
00538 void nf_unprotect( void )
00539 {
00540 gpio_set_gpio_pin(NF_WP_PIN);
00541 }
00542
00545 void nf_protect( void )
00546 {
00547 U32 i_dev;
00548
00549
00550 for( i_dev=0 ; i_dev<NF_N_DEVICES ; i_dev++ )
00551 {
00552 nf_select( i_dev );
00553 nf_wait_busy();
00554 }
00555 gpio_clr_gpio_pin(NF_WP_PIN);
00556 }
00557
00565 #if 0
00566 void nfc_print_block(U16 block_addr, U8 dev_id)
00567 {
00568 _MEM_TYPE_SLOW_ U32 page_addr=(U32)block_addr*((U8)1<<G_SHIFT_BLOCK_PAGE);
00569 _MEM_TYPE_SLOW_ U16 n_bytes;
00570 _MEM_TYPE_SLOW_ U16 i_byte;
00571 _MEM_TYPE_SLOW_ U8 i_page;
00572
00573 trace("\n\rDisplay block 0x");
00574 trace_hex( MSB(block_addr) );
00575 trace_hex( LSB(block_addr) );
00576
00577 n_bytes= ( Is_nf_512() )
00578 ? 512
00579 : 2048
00580 ;
00581 nf_select( dev_id );
00582
00583 for( i_page=0 ; i_page<64 ; i_page++, page_addr++ )
00584 {
00585 trace("\n\rOpening page 0x");
00586 trace_hex( MSB0(page_addr) );
00587 trace_hex( MSB1(page_addr) );
00588 trace_hex( MSB2(page_addr) );
00589 trace_hex( MSB3(page_addr) );
00590 #if 0
00591 nf_open_page_read( page_addr, 0 );
00592 for( i_byte=0 ; i_byte<n_bytes ; )
00593 {
00594 if( !(i_byte%32) )
00595 {
00596 trace("\n\r0x");
00597 trace_hex( MSB(i_byte) );
00598 trace_hex( LSB(i_byte) );
00599 trace(" 0x");
00600 }
00601 else if( !(i_byte%16) ) trace(" ");
00602 else if( !(i_byte% 8) ) trace(" ");
00603 trace_hex( nf_rd_data() );
00604 trace_hex( nf_rd_data() );
00605 trace_hex( nf_rd_data() );
00606 trace_hex( nf_rd_data() );
00607 i_byte+=4;
00608 }
00609 #else
00610 nf_open_page_read( page_addr, n_bytes );
00611 #endif
00612 trace("\n\rSpare zone: 0x");
00613 for( i_byte=4*4 ; i_byte!=0 ; i_byte-- )
00614 {
00615 if( i_byte%4==0 ) trace_nl();
00616 trace_hex( nf_rd_data() );
00617 trace_hex( nf_rd_data() );
00618 trace_hex( nf_rd_data() );
00619 trace_hex( nf_rd_data() );
00620 }
00621 trace("\n\r");
00622 }
00623 trace("\n\rOther way to access spare zone: 0x");
00624 page_addr=(U32)block_addr*((U8)1<<G_SHIFT_BLOCK_PAGE);
00625 nf_open_page_read( page_addr, NF_SPARE_POS );
00626 i_byte=Nfc_rd_data_fetch_next();
00627 {
00628 for ( i_byte=4*4 ; i_byte!=0 ; i_byte-- )
00629 {
00630 trace_hex( Nfc_rd_data_fetch_next() );
00631 trace_hex( Nfc_rd_data_fetch_next() );
00632 trace_hex( Nfc_rd_data_fetch_next() );
00633 trace_hex( Nfc_rd_data_fetch_next() );
00634 }
00635 trace("\n\r");
00636 }
00637 }
00638
00639 #endif // NF_BAD_CONFIG
00640
00641 #endif // _NF_C_