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00048 #ifndef _PEVC_H_
00049 #define _PEVC_H_
00050
00051 #include <avr32/io.h>
00052 #include "compiler.h"
00053
00054 #include "uc3c_pevc_ids.h"
00055
00058
00059
00060 #define PEVC_NUMBER_OF_EVENT_GENERATORS AVR32_PEVC_EVIN_BITS
00062 #define PEVC_NUMBER_OF_EVENT_USERS AVR32_PEVC_TRIGOUT_BITS
00063
00065
00066
00069
00070 #define PEVC_CHANNEL_IDLE 0
00071 #define PEVC_CHANNEL_BUSY 1
00073
00074
00077
00078 #define PEVC_EVS_IGF_ON ON
00079 #define PEVC_EVS_IGF_OFF OFF
00080 #define PEVC_EVS_EVF_ON ON
00081 #define PEVC_EVS_EVF_OFF OFF
00082 #define PEVC_EVS_EVR_ON ON
00083 #define PEVC_EVS_EVR_OFF OFF
00085
00087 typedef struct
00088 {
00090 unsigned char igfdr;
00091
00095 unsigned int igf;
00096
00100 unsigned int evf;
00101
00105 unsigned int evr;
00106 } pevc_evs_opt_t;
00107
00108
00112
00114
00128 extern Bool pevc_channel_configure( volatile avr32_pevc_t *pevc, unsigned short int chan_id,
00129 unsigned short int gen_id, const pevc_evs_opt_t *pevs );
00130
00131
00140 extern void pevc_igfd_set( volatile avr32_pevc_t *pevc, unsigned char igfd );
00141
00142 #define PEVC_IGFD_SET(pevc, igfd) \
00143 (pevc)->igfdr = ((igfd)<<AVR32_PEVC_IGFDR_IGFDR_OFFSET) & AVR32_PEVC_IGFDR_IGFDR_MASK;
00145
00146
00147
00151
00153
00160 extern void pevc_channels_enable(volatile avr32_pevc_t *pevc, unsigned long long int chan_mask);
00161
00162 #define PEVC_CHANNELS_ENABLE(pevc, chan_mask) \
00163 if((chan_mask)<=0x80000000) (pevc)->cher0 = (chan_mask); \
00164 else (pevc)->cher1 = (chan_mask);
00165
00172 extern void pevc_channels_disable(volatile avr32_pevc_t *pevc, unsigned long long int chan_mask);
00173
00174 #define PEVC_CHANNELS_DISABLE(pevc, chan_mask) \
00175 if((chan_mask)<=0x80000000) (pevc)->chdr0 = (chan_mask); \
00176 else (pevc)->chdr1 = (chan_mask);
00177
00178
00186 extern Bool pevc_get_channel_status(volatile avr32_pevc_t *pevc, unsigned short int chan_id);
00188
00189
00193
00195
00205 extern Bool pevc_get_channel_state(volatile avr32_pevc_t *pevc, unsigned short int chan_id);
00207
00208
00209
00213
00215
00223 extern void pevc_channel_sev_enable( volatile avr32_pevc_t *pevc, unsigned short int chan_id );
00224
00225 #define PEVC_CHANNEL_SEV_ENABLE(pevc, chan_id) ((pevc)->CHMX[(chan_id)].smx = ENABLE)
00226
00235 extern void pevc_channels_trigger_sev(volatile avr32_pevc_t *pevc, unsigned long long int chan_mask);
00236
00237 #define PEVC_CHANNELS_TRIGGER_SEV(pevc, chan_mask) \
00238 if((chan_mask)<=0x80000000) (pevc)->sev0 = (chan_mask); \
00239 else (pevc)->sev1 = (chan_mask);
00240
00248 extern void pevc_channel_sev_disable( volatile avr32_pevc_t *pevc, unsigned short int chan_id );
00249
00250 #define PEVC_CHANNEL_SEV_DISABLE(pevc, chan_id) ((pevc)->CHMX[(chan_id)].smx = DISABLE)
00252
00253
00254
00258
00260
00271 extern void pevc_channels_enable_trigger_interrupt( volatile avr32_pevc_t *pevc, unsigned long long int chan_mask);
00272
00273 #define PEVC_CHANNELS_ENABLE_TRIGGER_INTERRUPT(pevc, chan_mask) \
00274 if((chan_mask)<=0x80000000) (pevc)->trier0 = (chan_mask); \
00275 else (pevc)->trier1 = (chan_mask);
00276
00284 extern void pevc_channels_disable_trigger_interrupt( volatile avr32_pevc_t *pevc, unsigned long long int chan_mask);
00285
00286 #define PEVC_CHANNELS_DISABLE_TRIGGER_INTERRUPT(pevc, chan_mask) \
00287 if((chan_mask)<=0x80000000) (pevc)->tridr0 = (chan_mask); \
00288 else (pevc)->tridr1 = (chan_mask);
00289
00298 extern Bool pevc_channel_is_trigger_interrupt_enabled( volatile avr32_pevc_t *pevc, unsigned short int chan_id);
00299
00308 extern Bool pevc_channel_is_trigger_interrupt_raised( volatile avr32_pevc_t *pevc, unsigned short int chan_id);
00309
00316 extern void pevc_channel_clear_trigger_interrupt( volatile avr32_pevc_t *pevc, unsigned short int chan_id);
00317
00319
00320
00324
00326
00338 extern void pevc_channels_enable_overrun_interrupt( volatile avr32_pevc_t *pevc, unsigned long long int chan_mask);
00339
00340 #define PEVC_CHANNELS_ENABLE_OVERRUN_INTERRUPT(pevc, chan_mask) \
00341 if((chan_mask)<=0x80000000) (pevc)->ovier0 = (chan_mask); \
00342 else (pevc)->ovier1 = (chan_mask);
00343
00351 extern void pevc_channels_disable_overrun_interrupt( volatile avr32_pevc_t *pevc, unsigned long long int chan_mask);
00352
00353 #define PEVC_CHANNELS_DISABLE_OVERRUN_INTERRUPT(pevc, chan_mask) \
00354 if((chan_mask)<=0x80000000) (pevc)->ovidr0 = (chan_mask); \
00355 else (pevc)->ovidr1 = (chan_mask);
00356
00365 extern Bool pevc_channel_is_overrun_interrupt_enabled( volatile avr32_pevc_t *pevc, unsigned short int chan_id);
00366
00375 extern Bool pevc_channel_is_overrun_interrupt_raised( volatile avr32_pevc_t *pevc, unsigned short int chan_id);
00376
00383 extern void pevc_channel_clear_overrun_interrupt( volatile avr32_pevc_t *pevc, unsigned short int chan_id);
00385
00386 #endif // _PEVC_H_