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00046 #include "compiler.h"
00047 #include "preprocessor.h"
00048 #include "gpio.h"
00049 #include "sdramc.h"
00050
00051
00056 static void sdramc_ck_delay(unsigned long ck)
00057 {
00058
00059 unsigned long delay_start_cycle = Get_system_register(AVR32_COUNT);
00060 unsigned long delay_end_cycle = delay_start_cycle + ck;
00061
00062
00063
00064 if (delay_start_cycle > delay_end_cycle)
00065 {
00066 while ((unsigned long)Get_system_register(AVR32_COUNT) > delay_end_cycle);
00067 }
00068 while ((unsigned long)Get_system_register(AVR32_COUNT) < delay_end_cycle);
00069 }
00070
00071
00077 #define sdramc_ns_delay(ns, hsb_mhz_up) sdramc_ck_delay(((ns) * (hsb_mhz_up) + 999) / 1000)
00078
00079
00085 #define sdramc_us_delay(us, hsb_mhz_up) sdramc_ck_delay((us) * (hsb_mhz_up))
00086
00087
00091 #if BOARD == EVK1100 || BOARD == EVK1104 || BOARD == EVK1105
00092 static void sdramc_enable_muxed_pins(void)
00093 {
00094 static const gpio_map_t SDRAMC_EBI_GPIO_MAP =
00095 {
00096
00097 #define SDRAMC_ENABLE_DATA_PIN(DATA_BIT, unused) \
00098 {AVR32_EBI_DATA_##DATA_BIT##_PIN, AVR32_EBI_DATA_##DATA_BIT##_FUNCTION},
00099 MREPEAT(SDRAM_DBW, SDRAMC_ENABLE_DATA_PIN, ~)
00100 #undef SDRAMC_ENABLE_DATA_PIN
00101
00102
00103 {AVR32_EBI_ADDR_2_PIN, AVR32_EBI_ADDR_2_FUNCTION },
00104 {AVR32_EBI_ADDR_3_PIN, AVR32_EBI_ADDR_3_FUNCTION },
00105 {AVR32_EBI_ADDR_4_PIN, AVR32_EBI_ADDR_4_FUNCTION },
00106 {AVR32_EBI_ADDR_5_PIN, AVR32_EBI_ADDR_5_FUNCTION },
00107 {AVR32_EBI_ADDR_6_PIN, AVR32_EBI_ADDR_6_FUNCTION },
00108 {AVR32_EBI_ADDR_7_PIN, AVR32_EBI_ADDR_7_FUNCTION },
00109 {AVR32_EBI_ADDR_8_PIN, AVR32_EBI_ADDR_8_FUNCTION },
00110 {AVR32_EBI_ADDR_9_PIN, AVR32_EBI_ADDR_9_FUNCTION },
00111 {AVR32_EBI_ADDR_10_PIN, AVR32_EBI_ADDR_10_FUNCTION },
00112 {AVR32_EBI_ADDR_11_PIN, AVR32_EBI_ADDR_11_FUNCTION },
00113 {AVR32_EBI_SDA10_0_PIN, AVR32_EBI_SDA10_0_FUNCTION },
00114 #if SDRAM_ROW_BITS >= 12
00115 {AVR32_EBI_ADDR_13_PIN, AVR32_EBI_ADDR_13_FUNCTION },
00116 #if SDRAM_ROW_BITS >= 13
00117 {AVR32_EBI_ADDR_14_PIN, AVR32_EBI_ADDR_14_FUNCTION },
00118 #endif
00119 #endif
00120
00121
00122 {AVR32_EBI_ADDR_16_PIN, AVR32_EBI_ADDR_16_FUNCTION },
00123 #if SDRAM_BANK_BITS >= 2
00124 {AVR32_EBI_ADDR_17_PIN, AVR32_EBI_ADDR_17_FUNCTION },
00125 #endif
00126
00127
00128 {AVR32_EBI_ADDR_0_PIN, AVR32_EBI_ADDR_0_FUNCTION },
00129 {AVR32_EBI_NWE1_0_PIN, AVR32_EBI_NWE1_0_FUNCTION },
00130 #if SDRAM_DBW >= 32
00131 {AVR32_EBI_ADDR_1_PIN, AVR32_EBI_ADDR_1_FUNCTION },
00132 {AVR32_EBI_NWE3_0_PIN, AVR32_EBI_NWE3_0_FUNCTION },
00133 #endif
00134
00135
00136 {AVR32_EBI_SDWE_0_PIN, AVR32_EBI_SDWE_0_FUNCTION },
00137 {AVR32_EBI_CAS_0_PIN, AVR32_EBI_CAS_0_FUNCTION },
00138 {AVR32_EBI_RAS_0_PIN, AVR32_EBI_RAS_0_FUNCTION },
00139 {AVR32_EBI_NCS_1_PIN, AVR32_EBI_NCS_1_FUNCTION },
00140
00141
00142 {AVR32_EBI_SDCK_0_PIN, AVR32_EBI_SDCK_0_FUNCTION },
00143 {AVR32_EBI_SDCKE_0_PIN, AVR32_EBI_SDCKE_0_FUNCTION }
00144 };
00145
00146 gpio_enable_module(SDRAMC_EBI_GPIO_MAP, sizeof(SDRAMC_EBI_GPIO_MAP) / sizeof(SDRAMC_EBI_GPIO_MAP[0]));
00147 }
00148 #elif BOARD == UC3C_EK
00149 static void sdramc_enable_muxed_pins(void)
00150 {
00151 static const gpio_map_t SDRAMC_EBI_GPIO_MAP =
00152 {
00153
00154 #define SDRAMC_ENABLE_DATA_PIN(DATA_BIT, unused) \
00155 {AVR32_EBI_DATA_##DATA_BIT##_PIN, AVR32_EBI_DATA_##DATA_BIT##_FUNCTION},
00156 MREPEAT(SDRAM_DBW, SDRAMC_ENABLE_DATA_PIN, ~)
00157 #undef SDRAMC_ENABLE_DATA_PIN
00158
00159
00160 {AVR32_EBI_ADDR_2_PIN, AVR32_EBI_ADDR_2_FUNCTION },
00161 {AVR32_EBI_ADDR_3_PIN, AVR32_EBI_ADDR_3_FUNCTION },
00162 {AVR32_EBI_ADDR_4_PIN, AVR32_EBI_ADDR_4_FUNCTION },
00163 {AVR32_EBI_ADDR_5_PIN, AVR32_EBI_ADDR_5_FUNCTION },
00164 {AVR32_EBI_ADDR_6_PIN, AVR32_EBI_ADDR_6_FUNCTION },
00165 {AVR32_EBI_ADDR_7_PIN, AVR32_EBI_ADDR_7_FUNCTION },
00166 {AVR32_EBI_ADDR_8_PIN, AVR32_EBI_ADDR_8_FUNCTION },
00167 {AVR32_EBI_ADDR_9_PIN, AVR32_EBI_ADDR_9_FUNCTION },
00168 {AVR32_EBI_ADDR_10_PIN, AVR32_EBI_ADDR_10_FUNCTION },
00169 {AVR32_EBI_ADDR_11_PIN, AVR32_EBI_ADDR_11_FUNCTION },
00170 {AVR32_EBI_SDA10_PIN, AVR32_EBI_SDA10_FUNCTION },
00171 #if SDRAM_ROW_BITS >= 12
00172 {AVR32_EBI_ADDR_13_PIN, AVR32_EBI_ADDR_13_FUNCTION },
00173 #if SDRAM_ROW_BITS >= 13
00174 {AVR32_EBI_ADDR_14_PIN, AVR32_EBI_ADDR_14_FUNCTION },
00175 #endif
00176 #endif
00177
00178
00179 {AVR32_EBI_ADDR_16_PIN, AVR32_EBI_ADDR_16_FUNCTION },
00180 #if SDRAM_BANK_BITS >= 2
00181 {AVR32_EBI_ADDR_17_PIN, AVR32_EBI_ADDR_17_FUNCTION },
00182 #endif
00183
00184
00185 {AVR32_EBI_ADDR_0_PIN, AVR32_EBI_ADDR_0_FUNCTION },
00186 {AVR32_EBI_NWE1_PIN, AVR32_EBI_NWE1_FUNCTION },
00187 #if SDRAM_DBW >= 32
00188 {AVR32_EBI_ADDR_1_PIN, AVR32_EBI_ADDR_1_FUNCTION },
00189 {AVR32_EBI_NWE3_PIN, AVR32_EBI_NWE3_FUNCTION },
00190 #endif
00191
00192
00193 {AVR32_EBI_SDWE_PIN, AVR32_EBI_SDWE_FUNCTION },
00194 {AVR32_EBI_CAS_PIN, AVR32_EBI_CAS_FUNCTION },
00195 {AVR32_EBI_RAS_PIN, AVR32_EBI_RAS_FUNCTION },
00196 {AVR32_EBI_NCS_1_PIN, AVR32_EBI_NCS_1_FUNCTION },
00197
00198
00199 {AVR32_EBI_SDCK_PIN, AVR32_EBI_SDCK_FUNCTION },
00200 {AVR32_EBI_SDCKE_PIN, AVR32_EBI_SDCKE_FUNCTION }
00201 };
00202
00203 gpio_enable_module(SDRAMC_EBI_GPIO_MAP, sizeof(SDRAMC_EBI_GPIO_MAP) / sizeof(SDRAMC_EBI_GPIO_MAP[0]));
00204 }
00205 #elif BOARD == STK1000
00206 static void sdramc_enable_muxed_pins(void)
00207 {
00208 volatile avr32_hmatrix_t *hmatrix = &AVR32_HMATRIX;
00209
00210
00211 hmatrix->sfr[4] |= 0x0002;
00212 hmatrix->sfr[4] |= 0x0100;
00213
00214 static const gpio_map_t SDRAMC_EBI_GPIO_MAP =
00215 {
00216
00217 {AVR32_EBI_DATA_16_PIN, AVR32_EBI_DATA_16_FUNCTION },
00218 {AVR32_EBI_DATA_17_PIN, AVR32_EBI_DATA_17_FUNCTION },
00219 {AVR32_EBI_DATA_18_PIN, AVR32_EBI_DATA_18_FUNCTION },
00220 {AVR32_EBI_DATA_19_PIN, AVR32_EBI_DATA_19_FUNCTION },
00221 {AVR32_EBI_DATA_20_PIN, AVR32_EBI_DATA_20_FUNCTION },
00222 {AVR32_EBI_DATA_21_PIN, AVR32_EBI_DATA_21_FUNCTION },
00223 {AVR32_EBI_DATA_22_PIN, AVR32_EBI_DATA_22_FUNCTION },
00224 {AVR32_EBI_DATA_23_PIN, AVR32_EBI_DATA_23_FUNCTION },
00225 {AVR32_EBI_DATA_24_PIN, AVR32_EBI_DATA_24_FUNCTION },
00226 {AVR32_EBI_DATA_25_PIN, AVR32_EBI_DATA_25_FUNCTION },
00227 {AVR32_EBI_DATA_26_PIN, AVR32_EBI_DATA_26_FUNCTION },
00228 {AVR32_EBI_DATA_27_PIN, AVR32_EBI_DATA_27_FUNCTION },
00229 {AVR32_EBI_DATA_28_PIN, AVR32_EBI_DATA_28_FUNCTION },
00230 {AVR32_EBI_DATA_29_PIN, AVR32_EBI_DATA_29_FUNCTION },
00231 {AVR32_EBI_DATA_30_PIN, AVR32_EBI_DATA_30_FUNCTION },
00232 {AVR32_EBI_DATA_31_PIN, AVR32_EBI_DATA_31_FUNCTION }
00233 };
00234
00235 gpio_enable_module(SDRAMC_EBI_GPIO_MAP, sizeof(SDRAMC_EBI_GPIO_MAP) / sizeof(SDRAMC_EBI_GPIO_MAP[0]));
00236
00237
00238 }
00239
00240 #endif
00241
00242 void sdramc_init(unsigned long hsb_hz)
00243 {
00244 unsigned long hsb_mhz_dn = hsb_hz / 1000000;
00245 unsigned long hsb_mhz_up = (hsb_hz + 999999) / 1000000;
00246 volatile ATPASTE2(U, SDRAM_DBW) *sdram = SDRAM;
00247 unsigned int i;
00248
00249
00250 sdramc_enable_muxed_pins();
00251
00252
00253 AVR32_HMATRIX.sfr[AVR32_EBI_HMATRIX_NR] |= 1 << AVR32_EBI_SDRAM_CS;
00254 AVR32_HMATRIX.sfr[AVR32_EBI_HMATRIX_NR];
00255
00256
00257
00258 AVR32_SDRAMC.cr =
00259 ((( SDRAM_COL_BITS - 8) << AVR32_SDRAMC_CR_NC_OFFSET ) & AVR32_SDRAMC_CR_NC_MASK ) |
00260 ((( SDRAM_ROW_BITS - 11) << AVR32_SDRAMC_CR_NR_OFFSET ) & AVR32_SDRAMC_CR_NR_MASK ) |
00261 ((( SDRAM_BANK_BITS - 1) << AVR32_SDRAMC_CR_NB_OFFSET ) & AVR32_SDRAMC_CR_NB_MASK ) |
00262 (( SDRAM_CAS << AVR32_SDRAMC_CR_CAS_OFFSET ) & AVR32_SDRAMC_CR_CAS_MASK ) |
00263 ((( SDRAM_DBW >> 4) << AVR32_SDRAMC_CR_DBW_OFFSET ) & AVR32_SDRAMC_CR_DBW_MASK ) |
00264 ((((SDRAM_TWR * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TWR_OFFSET ) & AVR32_SDRAMC_CR_TWR_MASK ) |
00265 ((((SDRAM_TRC * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRC_OFFSET ) & AVR32_SDRAMC_CR_TRC_MASK ) |
00266 ((((SDRAM_TRP * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRP_OFFSET ) & AVR32_SDRAMC_CR_TRP_MASK ) |
00267 ((((SDRAM_TRCD * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRCD_OFFSET) & AVR32_SDRAMC_CR_TRCD_MASK) |
00268 ((((SDRAM_TRAS * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRAS_OFFSET) & AVR32_SDRAMC_CR_TRAS_MASK) |
00269 ((((SDRAM_TXSR * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TXSR_OFFSET) & AVR32_SDRAMC_CR_TXSR_MASK);
00270 AVR32_SDRAMC.cr;
00271
00272
00273 AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_NOP;
00274 AVR32_SDRAMC.mr;
00275 sdram[0];
00276
00277
00278 sdramc_us_delay(SDRAM_STABLE_CLOCK_INIT_DELAY, hsb_mhz_up);
00279
00280
00281 AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_BANKS_PRECHARGE;
00282 AVR32_SDRAMC.mr;
00283 sdram[0];
00284 sdramc_ns_delay(SDRAM_TRP, hsb_mhz_up);
00285
00286
00287 AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_AUTO_REFRESH;
00288 AVR32_SDRAMC.mr;
00289 for (i = 0; i < SDRAM_INIT_AUTO_REFRESH_COUNT; i++)
00290 {
00291 sdram[0];
00292 sdramc_ns_delay(SDRAM_TRFC, hsb_mhz_up);
00293 }
00294
00295
00296
00297
00298
00299
00300
00301
00302
00303 AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_LOAD_MODE;
00304 AVR32_SDRAMC.mr;
00305 sdram[0];
00306 sdramc_ns_delay(SDRAM_TMRD, hsb_mhz_up);
00307
00308
00309 AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_NORMAL;
00310 AVR32_SDRAMC.mr;
00311 sdram[0];
00312
00313
00314
00315 AVR32_SDRAMC.tr = (SDRAM_TR * hsb_mhz_dn) / 1000;
00316 AVR32_SDRAMC.tr;
00317 }