power_clocks_lib.h File Reference


Detailed Description

High-level library abstracting features such as oscillators/pll/dfll configuration, clock configuration, System-sensible parameters configuration, buses clocks configuration, sleep mode, reset.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file power_clocks_lib.h.

#include <avr32/io.h>
#include "compiler.h"
#include "pm.h"

Go to the source code of this file.

Clocks Management

#define pcl_disable_module(module)   pm_disable_module(&AVR32_PM, module)
 Disable the clock of a module.
#define pcl_enable_module(module)   pm_enable_module(&AVR32_PM, module)
 Enable the clock of a module.
#define pcl_freq_param_t   pm_freq_param_t
 Input and output parameters to configure clocks with pcl_configure_clocks().
#define PCL_NOT_SUPPORTED   (-10000)
 Define "not supported" for the lib.
enum  pcl_dfll_t { PCL_DFLL0 = 0, PCL_DFLL1 = 1 }
 The different DFLLs. More...
enum  pcl_mainclk_t {
  PCL_MC_RCSYS, PCL_MC_OSC0, PCL_MC_OSC1, PCL_MC_OSC0_PLL0,
  PCL_MC_OSC1_PLL0, PCL_MC_OSC0_PLL1, PCL_MC_OSC1_PLL1, PCL_MC_DFLL0,
  PCL_MC_DFLL1, PCL_MC_RC120M, PCL_MC_RC8M, PCL_MC_CRIPOSC
}
 Possible Main Clock Sources. More...
enum  pcl_osc_t { PCL_OSC0 = 0, PCL_OSC1 = 1 }
 The different oscillators. More...
long int pcl_configure_clocks (pcl_freq_param_t *param)
 Automatically configure the CPU, PBA, PBB, and HSB clocks.
long int pcl_configure_clocks_dfll0 (pcl_freq_param_t *param)
 Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock.
long int pcl_configure_clocks_osc0 (pcl_freq_param_t *param)
 Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock.
long int pcl_configure_clocks_rc120m (pcl_freq_param_t *param)
 Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock.
long int pcl_configure_clocks_rcsys (pcl_freq_param_t *param)
 Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock.
long int pcl_configure_usb_clock (void)
 Configure the USB Clock.
long int pcl_switch_to_osc (pcl_osc_t osc, unsigned int fcrystal, unsigned int startup)
 Switch the main clock source to Osc0 configured in crystal mode.

Functions

Power Management
unsigned long pcl_read_gplp (unsigned long gplp)
 Read the content of the GPLP registers.
void pcl_write_gplp (unsigned long gplp, unsigned long value)
 Write into the GPLP registers.


Define Documentation

#define pcl_disable_module ( module   )     pm_disable_module(&AVR32_PM, module)

Disable the clock of a module.

Parameters:
module The module to shut down (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks" or look in the module section).
Returns:
Status.
Return values:
0 Success.
<0 An error occured.

Definition at line 335 of file power_clocks_lib.h.

#define pcl_enable_module ( module   )     pm_enable_module(&AVR32_PM, module)

Enable the clock of a module.

Parameters:
module The module to clock (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks" or look in the module section).
Returns:
Status.
Return values:
0 Success.
<0 An error occured.

Definition at line 316 of file power_clocks_lib.h.

#define pcl_freq_param_t   pm_freq_param_t

Input and output parameters to configure clocks with pcl_configure_clocks().

Definition at line 114 of file power_clocks_lib.h.

#define PCL_NOT_SUPPORTED   (-10000)

Define "not supported" for the lib.

Definition at line 151 of file power_clocks_lib.h.

Referenced by pcl_configure_usb_clock(), and pcl_switch_to_osc().


Enumeration Type Documentation

enum pcl_dfll_t

The different DFLLs.

Enumerator:
PCL_DFLL0 
PCL_DFLL1 

Definition at line 87 of file power_clocks_lib.h.

00088 {
00089   PCL_DFLL0  = 0,
00090   PCL_DFLL1  = 1
00091 } pcl_dfll_t;

Possible Main Clock Sources.

Enumerator:
PCL_MC_RCSYS 
PCL_MC_OSC0 
PCL_MC_OSC1 
PCL_MC_OSC0_PLL0 
PCL_MC_OSC1_PLL0 
PCL_MC_OSC0_PLL1 
PCL_MC_OSC1_PLL1 
PCL_MC_DFLL0 
PCL_MC_DFLL1 
PCL_MC_RC120M 
PCL_MC_RC8M 
PCL_MC_CRIPOSC 

Definition at line 94 of file power_clocks_lib.h.

00095 {
00096   PCL_MC_RCSYS,      // Default main clock source, supported by all (aka Slow Clock)
00097   PCL_MC_OSC0,       // Supported by all
00098   PCL_MC_OSC1,       // Supported by UC3C only
00099   PCL_MC_OSC0_PLL0,  // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC0 as reference)
00100   PCL_MC_OSC1_PLL0,  // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC1 as reference)
00101   PCL_MC_OSC0_PLL1,  // Supported by UC3C  (the main clock source is PLL1 with OSC0 as reference)
00102   PCL_MC_OSC1_PLL1,  // Supported by UC3C  (the main clock source is PLL1 with OSC1 as reference)
00103   PCL_MC_DFLL0,      // Supported by UC3L
00104   PCL_MC_DFLL1,      // Not supported yet
00105   PCL_MC_RC120M,     // Supported by UC3L, UC3C
00106   PCL_MC_RC8M,       // Supported by UC3C
00107   PCL_MC_CRIPOSC     // Supported by UC3C
00108 } pcl_mainclk_t;

enum pcl_osc_t

The different oscillators.

Enumerator:
PCL_OSC0 
PCL_OSC1 

Definition at line 80 of file power_clocks_lib.h.

00081 {
00082   PCL_OSC0  = 0,
00083   PCL_OSC1  = 1
00084 } pcl_osc_t;


Function Documentation

long int pcl_configure_clocks ( pcl_freq_param_t *  param  ) 

Automatically configure the CPU, PBA, PBB, and HSB clocks.

This function needs some parameters stored in a pcl_freq_param_t structure:

  • main_clk_src is the id of the main clock source to use,
  • cpu_f and pba_f and pbb_f are the wanted frequencies,
  • osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),
  • osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).
  • dfll_f is the target DFLL frequency to set-up if main_clk_src is the dfll.

The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.

Note:
: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks() and modify it to use preprocessor computation from pre-defined target frequencies.
Parameters:
param pointer on the configuration structure.
Return values:
0 Success.
<0 The configuration cannot be performed.

Definition at line 60 of file power_clocks_lib.c.

References pm_configure_clocks().

00061 {
00062 #ifndef AVR32_PM_VERSION_RESETVALUE
00063   // Implementation for UC3A, UC3A3, UC3B parts.
00064   return(pm_configure_clocks(param));
00065 #else
00066   #ifdef AVR32_PM_410_H_INCLUDED
00067     // Implementation for UC3C parts.
00068     return(pcl_configure_clocks_uc3c(param));
00069   #else
00070     // Implementation for UC3L parts.
00071     return(pcl_configure_clocks_uc3l(param));
00072   #endif
00073 #endif
00074 }

long int pcl_configure_clocks_dfll0 ( pcl_freq_param_t *  param  ) 

Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock.

This function needs some parameters stored in a pcl_freq_param_t structure:

  • cpu_f and pba_f and pbb_f are the wanted frequencies,
  • dfll_f is the target DFLL frequency to set-up

Note:
: when the DFLL0 is to be used as main source clock for the synchronous clocks, the target frequency of the DFLL should be chosen to be as high as possible within the specification range (for stability reasons); the target cpu and pbx frequencies will then be reached by appropriate division ratio.
Supported main clock sources: PCL_MC_DFLL0

Supported synchronous clocks frequencies: (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example) 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.

Note:
: by default, this implementation doesn't perform thorough checks on the input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.

: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_dfll0() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:
param pointer on the configuration structure.
Return values:
0 Success.
<0 The configuration cannot be performed.

long int pcl_configure_clocks_osc0 ( pcl_freq_param_t *  param  ) 

Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock.

This function needs some parameters stored in a pcl_freq_param_t structure:

  • cpu_f and pba_f and pbb_f are the wanted frequencies,
  • osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),
  • osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).

Supported main clock sources: PCL_MC_OSC0

Supported synchronous clocks frequencies: (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example) 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.

Note:
: by default, this implementation doesn't perform thorough checks on the input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.

: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_osc0() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:
param pointer on the configuration structure.
Return values:
0 Success.
<0 The configuration cannot be performed.

long int pcl_configure_clocks_rc120m ( pcl_freq_param_t *  param  ) 

Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock.

This function needs some parameters stored in a pcl_freq_param_t structure:

  • cpu_f and pba_f and pbb_f are the wanted frequencies

Supported main clock sources: PCL_MC_RC120M

Supported synchronous clocks frequencies: 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.

Note:
: by default, this implementation doesn't perform thorough checks on the input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.

: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_rc120m() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:
param pointer on the configuration structure.
Return values:
0 Success.
<0 The configuration cannot be performed.

long int pcl_configure_clocks_rcsys ( pcl_freq_param_t *  param  ) 

Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock.

This function needs some parameters stored in a pcl_freq_param_t structure:

  • cpu_f and pba_f and pbb_f are the wanted frequencies

Supported main clock sources: PCL_MC_RCSYS

Supported synchronous clocks frequencies: 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.

Note:
: by default, this implementation doesn't perform thorough checks on the input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.

: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_rcsys() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:
param pointer on the configuration structure.
Return values:
0 Success.
<0 The configuration cannot be performed.

long int pcl_configure_usb_clock ( void   ) 

Configure the USB Clock.

Returns:
Status.
Return values:
0 Success.
<0 An error occured.

Definition at line 500 of file power_clocks_lib.c.

References PCL_NOT_SUPPORTED, and pm_configure_usb_clock().

00501 {
00502 #ifndef AVR32_PM_VERSION_RESETVALUE
00503 // Implementation for UC3A, UC3A3, UC3B parts.
00504   pm_configure_usb_clock();
00505   return PASS;
00506 #else
00507   #ifdef AVR32_PM_410_H_INCLUDED
00508     const scif_pll_opt_t opt = {
00509               .osc = SCIF_OSC0,     // Sel Osc0 or Osc1
00510               .lockcount = 16,      // lockcount in main clock for the PLL wait lock
00511               .div = 1,             // DIV=1 in the formula
00512               .mul = 5,             // MUL=7 in the formula
00513               .pll_div2 = 1,        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
00514               .pll_wbwdisable = 0,  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
00515               .pll_freq = 1,        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
00516     };
00517 
00518     /* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */
00519     scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock
00520 
00521     /* Enable PLL1 */
00522     scif_pll_enable(SCIF_PLL1);
00523 
00524     /* Wait for PLL1 locked */
00525     scif_wait_for_pll_locked(SCIF_PLL1) ;
00526 
00527   // Implementation for UC3C parts.
00528     // Setup the generic clock for USB
00529     scif_gc_setup(AVR32_SCIF_GCLK_USB,
00530                   SCIF_GCCTRL_PLL1,
00531                   AVR32_SCIF_GC_NO_DIV_CLOCK,
00532                   0);
00533     // Now enable the generic clock
00534     scif_gc_enable(AVR32_SCIF_GCLK_USB);
00535     return PASS;
00536   #else
00537       return PCL_NOT_SUPPORTED;
00538   #endif
00539 #endif
00540 }

unsigned long pcl_read_gplp ( unsigned long  gplp  ) 

Read the content of the GPLP registers.

Parameters:
gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
Returns:
The content of the chosen GPLP register.

Definition at line 555 of file power_clocks_lib.c.

References pm_read_gplp().

00556 {
00557 #ifndef AVR32_PM_VERSION_RESETVALUE
00558 // Implementation for UC3A, UC3A3, UC3B parts.
00559   return pm_read_gplp(&AVR32_PM,gplp);
00560 #else
00561   return scif_read_gplp(gplp);
00562 #endif
00563 }

long int pcl_switch_to_osc ( pcl_osc_t  osc,
unsigned int  fcrystal,
unsigned int  startup 
)

Switch the main clock source to Osc0 configured in crystal mode.

Parameters:
osc The oscillator to enable and switch to.
fcrystal Oscillator external crystal frequency (Hz)
startup Oscillator startup time.
Returns:
Status.
Return values:
0 Success.
<0 An error occured.
Switch the main clock source to Osc0 configured in crystal mode.

UC3C Device-specific implementation

Definition at line 457 of file power_clocks_lib.c.

References PCL_NOT_SUPPORTED, PCL_OSC0, PM_CLK_SRC_OSC0, pm_set_mclk_source(), and pm_switch_to_osc0().

00458 {
00459 #ifndef AVR32_PM_VERSION_RESETVALUE
00460 // Implementation for UC3A, UC3A3, UC3B parts.
00461   if(PCL_OSC0 == osc)
00462   {
00463     // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency,
00464     // enable the OSC0, set the main clock source as being OSC0.
00465     pm_switch_to_osc0(&AVR32_PM, fcrystal, startup);
00466   }
00467   else
00468   {
00469     return PCL_NOT_SUPPORTED;
00470   }
00471 #else
00472 // Implementation for UC3C, UC3L parts.
00473   #if AVR32_PM_VERSION_RESETVALUE < 0x400
00474     return PCL_NOT_SUPPORTED;
00475   #else
00476   if(PCL_OSC0 == osc)
00477   {
00478     // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
00479     scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal);
00480     // Enable the OSC0
00481     scif_enable_osc(SCIF_OSC0, startup, true);
00482     // Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
00483 #if UC3L
00484     flashcdw_set_flash_waitstate_and_readmode(fcrystal);
00485 #elif UC3C
00486     flashc_set_flash_waitstate_and_readmode(fcrystal);
00487 #endif
00488     // Set the main clock source as being OSC0.
00489     pm_set_mclk_source(PM_CLK_SRC_OSC0);
00490   }
00491   else
00492   {
00493     return PCL_NOT_SUPPORTED;
00494   }
00495   #endif
00496 #endif
00497   return PASS;
00498 }

void pcl_write_gplp ( unsigned long  gplp,
unsigned long  value 
)

Write into the GPLP registers.

Parameters:
gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
value Value to write

Definition at line 545 of file power_clocks_lib.c.

References pm_write_gplp().

00546 {
00547 #ifndef AVR32_PM_VERSION_RESETVALUE
00548 // Implementation for UC3A, UC3A3, UC3B parts.
00549   pm_write_gplp(&AVR32_PM,gplp,value);
00550 #else
00551   scif_write_gplp(gplp,value);
00552 #endif
00553 }


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