Definition in file isp.c.
#include "preprocessor.h"
#include "compiler.h"
#include "board.h"
#include "pm.h"
#include "rtc.h"
#include "cycle_counter.h"
#include "flashc.h"
#include "conf_usb.h"
#include "usb_drv.h"
#include "usb_task.h"
#include "usb_dfu.h"
#include "conf_isp.h"
#include "isp.h"
#include "autobaud.h"
Go to the source code of this file.
Defines | |
#define | MAX_OSC_FREQ 16000000 |
#define | PM (&AVR32_PM) |
#define | TC (&AVR32_TC) |
#define | TC_32KHZ_CHANNEL 0 |
Functions | |
int | main (void) |
static void | osc_isp_counter_reset (void) |
static int | osc_isp_counter_value (void) |
static void | osc_rtc_counter_reset (void) |
static int | osc_rtc_counter_value (void) |
void | sys_clk_gen_start (void) |
void | sys_clk_gen_stop (void) |
void | wait_10_ms (void) |
#define MAX_OSC_FREQ 16000000 |
Referenced by sys_clk_gen_start().
#define PM (&AVR32_PM) |
int main | ( | void | ) |
Definition at line 269 of file isp.c.
References usb_dfu_init(), and wait_10_ms().
00270 { 00271 wait_10_ms(); 00272 00273 Usb_force_full_speed_mode(); 00274 usb_task_init(); 00275 #if USB_DEVICE_FEATURE == ENABLED 00276 usb_dfu_init(); 00277 #endif 00278 00279 while (TRUE) 00280 { 00281 usb_task(); 00282 } 00283 }
static void osc_isp_counter_reset | ( | void | ) | [static] |
static int osc_isp_counter_value | ( | void | ) | [static] |
static void osc_rtc_counter_reset | ( | void | ) | [static] |
static int osc_rtc_counter_value | ( | void | ) | [static] |
void sys_clk_gen_start | ( | void | ) |
Start the generation of system clocks with USB autobaud
Definition at line 132 of file isp.c.
References ISP_OSC, MAX_OSC_FREQ, osc_isp_counter_reset(), osc_isp_counter_value(), osc_rtc_counter_reset(), osc_rtc_counter_value(), and PM.
00133 { 00134 int cpu_freq_hz, mul; 00135 const int freq_hz[] = { 8000000, 12000000, 16000000 }; 00136 const struct autobaud_cfg_osc_cmp_t autobaud_cfg = { 00137 .osc_ref_freq_hz = 115000, 00138 .osc_ref_counter_reset = osc_rtc_counter_reset, 00139 .osc_ref_counter_value = osc_rtc_counter_value, 00140 .osc_target_counter_reset = osc_isp_counter_reset, 00141 .osc_target_counter_value = osc_isp_counter_value, 00142 .convergence_rate = 10000 00143 }; 00144 const struct autobaud_matching_freq_t match_freq = { 00145 .freq_hz = freq_hz, 00146 .nb_entries = sizeof(freq_hz)/sizeof(freq_hz[0]) 00147 }; 00148 Bool sav_glob_int_en; 00149 00150 #define MAX_OSC_FREQ 16000000 00151 00152 00153 // Switch to OSC ISP 00154 // Set max startup time to make sure any crystal will be supported 00155 // We cannot use a TC to measure this OSC frequency because the master clock must be faster than the clock selected by the TC 00156 pm_switch_to_osc0(&AVR32_PM, MAX_OSC_FREQ, ATPASTE3(AVR32_PM_OSCCTRL, ISP_OSC, _STARTUP_16384_RCOSC)); 00157 // Intialize the RTC with the internal RC oscillator 00158 // RTC will count at the frequency of 115KHz/2 00159 rtc_init(&AVR32_RTC, RTC_OSC_RC, 0); 00160 rtc_enable(&AVR32_RTC); 00161 00162 // Calculate the frequency 00163 if (!(cpu_freq_hz = autobaud_detect_osc_cmp(&autobaud_cfg))) 00164 cpu_freq_hz = 12000000; 00165 cpu_freq_hz = autobaud_match_frequency(cpu_freq_hz, &match_freq); 00166 00167 switch (cpu_freq_hz) 00168 { 00169 case 8000000: 00170 mul = 5; 00171 break; 00172 case 12000000: 00173 mul = 3; 00174 break; 00175 case 16000000: 00176 mul = 2; 00177 break; 00178 default: 00179 mul = 3; 00180 } 00181 00182 Usb_freeze_clock(); 00183 00184 // Set PLL0 VCO @ 96 MHz 00185 pm_pll_setup(PM, 0, // pll 00186 mul, // mul 00187 0, // div 00188 ISP_OSC, // osc 00189 63); // lockcount 00190 00191 if ((sav_glob_int_en = Is_global_interrupt_enabled())) Disable_global_interrupt(); 00192 00193 // Set PLL0 @ 48 MHz 00194 pm_pll_set_option(PM, 0, // pll 00195 1, // pll_freq 00196 1, // pll_div2 00197 0); // pll_wbwdisable 00198 00199 // Enable PLL0 00200 pm_pll_enable(PM, 0); 00201 00202 // Wait for PLL0 locked with a 10-ms time-out 00203 pm_wait_for_pll0_locked(PM); 00204 00205 // Setup USB GCLK 00206 pm_gc_setup(PM, AVR32_PM_GCLK_USBB, // gc 00207 1, // osc_or_pll: use Osc (if 0) or PLL (if 1) 00208 0, // pll_osc: select Osc0/PLL0 or Osc1/PLL1 00209 #if UC3A3 00210 1, // diven 00211 1); // div 00212 #else 00213 0, // diven 00214 0); // div 00215 #endif 00216 00217 // Enable USB GCLK 00218 pm_gc_enable(PM, AVR32_PM_GCLK_USBB); 00219 00220 Usb_unfreeze_clock(); 00221 00222 // Use 1 flash wait state 00223 flashc_set_wait_state(1); 00224 00225 // Switch the main clock to PLL0 00226 pm_switch_to_clock(PM, AVR32_PM_MCCTRL_MCSEL_PLL0); 00227 00228 // fPBA: 12 MHz 00229 // fPBB: 12 MHz 00230 // fHSB: 12 MHz 00231 pm_cksel(PM, 1, // pbadiv 00232 1, // pbasel 00233 1, // pbbdiv 00234 1, // pbbsel 00235 1, // hsbdiv 00236 1); // hsbsel 00237 00238 // Use 0 flash wait state 00239 flashc_set_wait_state(0); 00240 00241 Usb_ack_sof(); 00242 00243 if (sav_glob_int_en) Enable_global_interrupt(); 00244 }
void sys_clk_gen_stop | ( | void | ) |
Stop the generation of system clocks and switch to RCOsc
Definition at line 250 of file isp.c.
References ISP_OSC, pm_disable_clk, pm_enable_clk_no_wait, and pm_enable_osc_ext_clock.
Referenced by usb_dfu_dnload().
00251 { 00252 volatile avr32_pm_t *const pm = &AVR32_PM; 00253 00254 pm_gc_disable(pm, AVR32_PM_GCLK_USBB); 00255 pm_gc_setup(pm, AVR32_PM_GCLK_USBB, 0, 0, 0, 0); 00256 flashc_set_wait_state(1); 00257 pm_cksel(pm, 0, 0, 0, 0, 0, 0); 00258 pm_switch_to_clock(pm, AVR32_PM_MCCTRL_MCSEL_SLOW); 00259 flashc_set_wait_state(0); 00260 pm_pll_disable(pm, 0); 00261 pm_pll_set_option(pm, 0, 0, 0, 0); 00262 pm_pll_setup(pm, 0, 0, 0, 0, 0); 00263 pm_enable_clk_no_wait(pm, ATPASTE3(AVR32_PM_OSCCTRL, ISP_OSC, _STARTUP_0_RCOSC)); 00264 pm_disable_clk(pm); 00265 pm_enable_osc_ext_clock(pm); 00266 }
void wait_10_ms | ( | void | ) |
Definition at line 103 of file isp.c.
Referenced by main(), and usb_dfu_dnload().
00104 { 00105 Set_system_register(AVR32_COUNT, 0); 00106 while ((U32)Get_system_register(AVR32_COUNT) < (FRCOSC * 10 + 999) / 1000); 00107 }