Definition in file pm_example3.c.
#include "board.h"
#include "gpio.h"
Go to the source code of this file.
Defines | |
Generic Clock Configuration | |
#define | EXAMPLE_CPUCLK_HZ (30000000UL) |
#define | EXAMPLE_GCLK_FUNCTION AVR32_SCIF_GCLK_1_0_FUNCTION |
#define | EXAMPLE_GCLK_ID AVR32_SCIF_GCLK_DFLL0_SSG |
#define | EXAMPLE_GCLK_PIN AVR32_SCIF_GCLK_1_0_PIN |
Functions | |
static void | local_set_main_clock_to_rc120m (void) |
static void | local_start_gc (void) |
int | main (void) |
static void | software_delay (void) |
#define EXAMPLE_CPUCLK_HZ (30000000UL) |
#define EXAMPLE_GCLK_FUNCTION AVR32_SCIF_GCLK_1_0_FUNCTION |
#define EXAMPLE_GCLK_ID AVR32_SCIF_GCLK_DFLL0_SSG |
#define EXAMPLE_GCLK_PIN AVR32_SCIF_GCLK_1_0_PIN |
static void local_set_main_clock_to_rc120m | ( | void | ) | [static] |
Definition at line 123 of file pm_example3.c.
References EXAMPLE_CPUCLK_HZ, PM_CKSEL_DIVRATIO_4, PM_CLK_SRC_RC120M, pm_set_clk_domain_div(), and pm_set_mclk_source().
Referenced by main().
00124 { 00125 // Start the 120MHz internal RCosc (RC120M) clock 00126 scif_start_rc120M(); 00127 00128 // Since our target is to set the CPU&HSB frequency domains to 30MHz, set the 00129 // appropriate wait-state and speed read mode on the flash controller. 00130 flashcdw_set_flash_waitstate_and_readmode(EXAMPLE_CPUCLK_HZ); 00131 00132 // Set the CPU clock domain to 30MHz (by applying a division ratio = 4). 00133 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_4); 00134 00135 // Set the PBA clock domain to 30MHz (by applying a division ratio = 4). 00136 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_4); 00137 00138 // Set the PBB clock domain to 30MHz (by applying a division ratio = 4). 00139 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_4); 00140 00141 // Set the main clock source to be the RC120M. 00142 pm_set_mclk_source(PM_CLK_SRC_RC120M); 00143 }
static void local_start_gc | ( | void | ) | [static] |
Definition at line 149 of file pm_example3.c.
References EXAMPLE_GCLK_FUNCTION, EXAMPLE_GCLK_ID, and EXAMPLE_GCLK_PIN.
Referenced by main().
00150 { 00151 // Note: for UC3L devices, the generic clock configurations are handled by the 00152 // SCIF module. 00153 // Setup gc to use RC120M as source clock, divisor enabled, apply a division factor. 00154 // Since the RC120M frequency is 120MHz, set the division factor to 4 to have a 00155 // gclk frequency of 30MHz. 00156 scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_RC120M, AVR32_GC_DIV_CLOCK, 4); 00157 00158 // Now enable the generic clock 00159 scif_gc_enable(EXAMPLE_GCLK_ID); 00160 00161 // Set the GCLOCK function to the GPIO pin 00162 gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION); 00163 }
int main | ( | void | ) |
Definition at line 182 of file pm_example3.c.
References local_set_main_clock_to_rc120m(), local_start_gc(), and software_delay().
00183 { 00184 // Start RC120M, switch main clock to RC120M/4. 00185 local_set_main_clock_to_rc120m(); 00186 00187 /* Set-up a generic clock from a high frequency clock and output it to a gpio pin. */ 00188 local_start_gc(); 00189 00190 /* Now toggle LED0 using a GPIO */ 00191 while(1) 00192 { 00193 gpio_tgl_gpio_pin(LED0_GPIO); 00194 software_delay(); 00195 } 00196 }
static void software_delay | ( | void | ) | [static] |