00001
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047 #include "preprocessor.h"
00048
00049 #if !defined(FORCE_ALL_GENERICS) && \
00050 !defined(FORCE_GENERIC_VECT16_REALDIV) && \
00051 defined(TARGET_SPECIFIC_VECT16_REALDIV)
00052
00053 #if __GNUC__
00054 # define DSP16_REALDIV_END_KERNEL_X_FCT(x_num, data) __attribute__((__naked__)) DSP16_REALDIV_END_KERNEL_X_FCT__(x_num, data)
00055 #elif __ICCAVR32__
00056 # define DSP16_REALDIV_END_KERNEL_X_FCT(x_num, data) DSP16_REALDIV_END_KERNEL_X_FCT__(x_num, data)
00057 #endif
00058
00059
00060 #if __GNUC__
00061 # define ASM_INSTRUCT_COMPACKED(str) str
00062 # define ASM_INSTRUCT_EXTENDED(str) str
00063 #elif __ICCAVR32__
00064 # define ASM_INSTRUCT_COMPACKED(str) str":C"
00065 # define ASM_INSTRUCT_EXTENDED(str) str":E"
00066 #endif
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081 #define DSP16_REALDIVISION_0(r_vect1, r_vect2, real)
00082
00083 #define DSP16_REALDIVISION_1(r_vect1, r_vect2, real) \
00084 "ld.sh r2, "ASTRINGZ(r_vect2)"[0x0]\n\t" \
00085 "lsl r2, "ASTRINGZ(DSP16_QB)"\n\t" \
00086 \
00087 "divs r0, r2, "ASTRINGZ(real)"\n\t" \
00088 "st.h "ASTRINGZ(r_vect1)"[0x0], r0\n\t"
00089
00090 #define DSP16_REALDIVISION_2(r_vect1, r_vect2, real) \
00091 "ld.sh r0, "ASTRINGZ(r_vect2)"[0x0]\n\t" \
00092 "lsl r0, "ASTRINGZ(DSP16_QB)"\n\t" \
00093 "divs r2, r0, "ASTRINGZ(real)"\n\t" \
00094 \
00095 "ld.sh r0, "ASTRINGZ(r_vect2)"[0x2]\n\t" \
00096 "lsl r0, "ASTRINGZ(DSP16_QB)"\n\t" \
00097 "divs r4, r0, "ASTRINGZ(real)"\n\t" \
00098 \
00099 "sthh.w r12[0x0], r2:b, r4:b\n\t"
00100
00101 #define DSP16_REALDIVISION_3(r_vect1, r_vect2, real) \
00102 "ld.sh r0, "ASTRINGZ(r_vect2)"[0x0]\n\t" \
00103 "lsl r0, "ASTRINGZ(DSP16_QB)"\n\t" \
00104 "divs r2, r0, "ASTRINGZ(real)"\n\t" \
00105 \
00106 "ld.sh r0, "ASTRINGZ(r_vect2)"[0x2]\n\t" \
00107 "lsl r0, "ASTRINGZ(DSP16_QB)"\n\t" \
00108 "divs r4, r0, "ASTRINGZ(real)"\n\t" \
00109 \
00110 "sthh.w r12[0x0], r2:b, r4:b\n\t" \
00111 \
00112 "ld.sh r2, "ASTRINGZ(r_vect2)"[0x4]\n\t" \
00113 "lsl r2, "ASTRINGZ(DSP16_QB)"\n\t" \
00114 \
00115 "divs r0, r2, "ASTRINGZ(real)"\n\t" \
00116 "st.h "ASTRINGZ(r_vect1)"[0x4], r0\n\t"
00117
00118
00119
00120
00121
00122
00123 #define DSP16_REALDIV_END_KERNEL_X_FCT__(x_num, data) \
00124 static void TPASTE2(dsp16_vect_realdiv_end_kernel_x, x_num)(dsp16_t *vect1, dsp16_t *vect2, dsp16_t real) \
00125 { \
00126 __asm__ __volatile__ ( \
00127 "pushm r0-r3, lr\n\t" \
00128 TPASTE2(DSP16_REALDIVISION_, x_num)(r12, r11, r10) \
00129 "popm r0-r3, pc\n\t" \
00130 ); \
00131 }
00132
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142
00143
00144
00145
00147 #if __GNUC__
00148 __attribute__((__naked__))
00149 __attribute__((__noinline__))
00150 #elif __ICCAVR32__
00151 # pragma shadow_registers=full
00152 # pragma optimize=none no_inline
00153 #endif
00154 static int dsp16_vect_realdiv_kernel_ext(dsp16_t *vect1, dsp16_t *vect2, int size, dsp16_t real)
00155 {
00156 __asm__ __volatile__ ( \
00157 "pushm r0-r7, lr\n\t" \
00158 \
00159 "mov lr, 0\n\t" \
00160 "sub r10, 3\n\t" \
00161 \
00162 "cp.h lr, r10\n\t" \
00163 ASM_INSTRUCT_COMPACKED("brge __dsp16_realdiv_ext_end_loop")"\n" \
00164 \
00165 "__dsp16_realdiv_ext_loop:\n\t" \
00166 \
00167 "ld.sh r0, r11[0x0]\n\t" \
00168 "lsl r0, "ASTRINGZ(DSP16_QB)"\n\t" \
00169 "divs r2, r0, r9\n\t" \
00170 \
00171 "ld.sh r0, r11[0x2]\n\t" \
00172 "lsl r0, "ASTRINGZ(DSP16_QB)"\n\t" \
00173 "divs r4, r0, r9\n\t" \
00174 \
00175 "sthh.w r12[lr << 1], r2:b, r4:b\n\t" \
00176 "sub lr, -2\n\t" \
00177 \
00178 "ld.sh r0, r11[0x4]\n\t" \
00179 "lsl r0, "ASTRINGZ(DSP16_QB)"\n\t" \
00180 "divs r2, r0, r9\n\t" \
00181 \
00182 "ld.sh r0, r11[0x6]\n\t" \
00183 "lsl r0, "ASTRINGZ(DSP16_QB)"\n\t" \
00184 "divs r4, r0, r9\n\t" \
00185 \
00186 "sub r11, -8\n\t" \
00187 \
00188 "sthh.w r12[lr << 1], r2:b, r4:b\n\t" \
00189 "sub lr, -2\n\t" \
00190 \
00191 "cp.h lr, r10\n\t" \
00192 ASM_INSTRUCT_COMPACKED("brlt __dsp16_realdiv_ext_loop")"\n" \
00193 \
00194 "__dsp16_realdiv_ext_end_loop:\n\t" \
00195 \
00196 "mov r12, lr\n\t" \
00197 "popm r0-r7, pc\n\t" \
00198 ); \
00199
00200 return 0;
00201 }
00202
00203
00204 DSP16_REALDIV_END_KERNEL_X_FCT(0, "")
00205 DSP16_REALDIV_END_KERNEL_X_FCT(1, "")
00206 DSP16_REALDIV_END_KERNEL_X_FCT(2, "")
00207 DSP16_REALDIV_END_KERNEL_X_FCT(3, "")
00208
00209 void dsp16_vect_realdiv(dsp16_t *vect1, dsp16_t *vect2, int size, dsp16_t real)
00210 {
00211 typedef void (*realdiv_end_kernel_opti_t)(dsp16_t *, dsp16_t *, dsp16_t);
00212 static const realdiv_end_kernel_opti_t realdiv_end_kernel_opti[4] = {
00213 dsp16_vect_realdiv_end_kernel_x0,
00214 dsp16_vect_realdiv_end_kernel_x1,
00215 dsp16_vect_realdiv_end_kernel_x2,
00216 dsp16_vect_realdiv_end_kernel_x3
00217 };
00218 int n;
00219
00220 n = dsp16_vect_realdiv_kernel_ext(vect1, vect2, size, real);
00221
00222
00223 realdiv_end_kernel_opti[size&0x3](&vect1[n], &vect2[n], real);
00224 }
00225
00226 #endif