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00050 #include "compiler.h"
00051 #include "ssc_i2s.h"
00052
00053
00070 static int set_clock_divider(volatile avr32_ssc_t *ssc,
00071 unsigned int bit_rate,
00072 unsigned int pba_hz)
00073 {
00076 ssc->cmr = ((pba_hz + bit_rate) / (2 * bit_rate)) << AVR32_SSC_CMR_DIV_OFFSET;
00077
00078 return SSC_I2S_OK;
00079 }
00080
00081
00082 void ssc_i2s_reset(volatile avr32_ssc_t *ssc)
00083 {
00084
00085 ssc->cr = AVR32_SSC_CR_SWRST_MASK;
00086 }
00087
00088
00089 int ssc_i2s_init(volatile avr32_ssc_t *ssc,
00090 unsigned int sample_frequency,
00091 unsigned int data_bit_res,
00092 unsigned int frame_bit_res,
00093 unsigned char mode,
00094 unsigned int pba_hz)
00095 {
00098
00099 ssc_i2s_reset(ssc);
00100
00101 if (mode == SSC_I2S_MODE_SLAVE_STEREO_OUT)
00102 {
00103 ssc->cmr = AVR32_SSC_CMR_DIV_NOT_ACTIVE << AVR32_SSC_CMR_DIV_OFFSET;
00104
00105 ssc->tcmr = AVR32_SSC_TCMR_CKS_TK_PIN << AVR32_SSC_TCMR_CKS_OFFSET |
00106 AVR32_SSC_TCMR_CKO_INPUT_ONLY << AVR32_SSC_TCMR_CKO_OFFSET |
00107 0 << AVR32_SSC_TCMR_CKI_OFFSET |
00108 AVR32_SSC_TCMR_CKG_NONE << AVR32_SSC_TCMR_CKG_OFFSET |
00109 AVR32_SSC_TCMR_START_DETECT_ANY_EDGE_TF << AVR32_SSC_TCMR_START_OFFSET |
00110 1 << AVR32_SSC_TCMR_STTDLY_OFFSET |
00111 0 << AVR32_SSC_TCMR_PERIOD_OFFSET;
00112 #ifdef AVR32_SSC_220_H_INCLUDED
00113 ssc->tfmr = (data_bit_res - 1) << AVR32_SSC_TFMR_DATLEN_OFFSET |
00114 0 << AVR32_SSC_TFMR_DATDEF_OFFSET |
00115 1 << AVR32_SSC_TFMR_MSBF_OFFSET |
00116 (1 - 1) << AVR32_SSC_TFMR_DATNB_OFFSET |
00117 0 << AVR32_SSC_TFMR_FSLEN_OFFSET |
00118 AVR32_SSC_TFMR_FSOS_INPUT_ONLY << AVR32_SSC_TFMR_FSOS_OFFSET |
00119 0 << AVR32_SSC_TFMR_FSDEN_OFFSET |
00120 0 << AVR32_SSC_TFMR_FSEDGE_OFFSET;
00121 #else
00122 ssc->tfmr = (data_bit_res - 1) << AVR32_SSC_TFMR_DATLEN_OFFSET |
00123 0 << AVR32_SSC_TFMR_DATDEF_OFFSET |
00124 1 << AVR32_SSC_TFMR_MSBF_OFFSET |
00125 (1 - 1) << AVR32_SSC_TFMR_DATNB_OFFSET |
00126 0 << AVR32_SSC_TFMR_FSLEN_OFFSET |
00127 AVR32_SSC_TFMR_FSOS_INPUT_ONLY << AVR32_SSC_TFMR_FSOS_OFFSET |
00128 0 << AVR32_SSC_TFMR_FSDEN_OFFSET |
00129 0 << AVR32_SSC_TFMR_FSEDGE_OFFSET |
00130 0 << AVR32_SSC_TFMR_FSLENHI_OFFSET;
00131 #endif
00132 ssc->cr = AVR32_SSC_CR_TXEN_MASK;
00133 }
00134 else if (mode == SSC_I2S_MODE_SLAVE_STEREO_IN)
00135 {
00136 ssc->cmr = AVR32_SSC_CMR_DIV_NOT_ACTIVE << AVR32_SSC_CMR_DIV_OFFSET;
00137 ssc->tcmr = 0;
00138 ssc->tfmr = 0;
00139 ssc->rcmr = (AVR32_SSC_RCMR_CKS_RK_PIN << AVR32_SSC_RCMR_CKS_OFFSET) |
00140 (1 << AVR32_SSC_RCMR_CKI_OFFSET)|
00141 (AVR32_SSC_RCMR_CKO_INPUT_ONLY << AVR32_SSC_RCMR_CKO_OFFSET) |
00142 (1 << AVR32_SSC_RCMR_STTDLY_OFFSET ) |
00143 (AVR32_SSC_RCMR_START_DETECT_FALLING_RF << AVR32_SSC_RCMR_START_OFFSET)
00144 ;
00145
00146 #ifdef AVR32_SSC_220_H_INCLUDED
00147 ssc->rfmr = (data_bit_res - 1) << AVR32_SSC_RFMR_DATLEN_OFFSET |
00148 1 << AVR32_SSC_RFMR_MSBF_OFFSET |
00149 (1 - 1) << AVR32_SSC_RFMR_DATNB_OFFSET |
00150 (((frame_bit_res - 1) << AVR32_SSC_RFMR_FSLEN_OFFSET) & AVR32_SSC_RFMR_FSLEN_MASK) |
00151 AVR32_SSC_RFMR_FSOS_INPUT_ONLY << AVR32_SSC_RFMR_FSOS_OFFSET |
00152 1 << AVR32_SSC_RFMR_FSEDGE_OFFSET;
00153 #else
00154 ssc->rfmr = (data_bit_res - 1) << AVR32_SSC_RFMR_DATLEN_OFFSET |
00155 1 << AVR32_SSC_RFMR_MSBF_OFFSET |
00156 (1 - 1) << AVR32_SSC_RFMR_DATNB_OFFSET |
00157 (((frame_bit_res - 1) << AVR32_SSC_RFMR_FSLEN_OFFSET) & AVR32_SSC_RFMR_FSLEN_MASK) |
00158 AVR32_SSC_RFMR_FSOS_INPUT_ONLY << AVR32_SSC_RFMR_FSOS_OFFSET |
00159 1 << AVR32_SSC_RFMR_FSEDGE_OFFSET |
00160 ((frame_bit_res - 1) >> AVR32_SSC_RFMR_FSLEN_SIZE) << AVR32_SSC_RFMR_FSLENHI_OFFSET;
00161 #endif
00162
00163 ssc->cr = AVR32_SSC_CR_RXEN_MASK;
00164
00165 }
00166 else
00167 {
00168
00169
00170
00171
00172
00173
00174
00175
00176 unsigned long txen_mask = 0x00000000,
00177 rxen_mask = 0x00000000;
00178
00179 if (mode != SSC_I2S_MODE_STEREO_OUT_EXT_CLK)
00180 {
00181
00182 set_clock_divider(ssc, 2 * sample_frequency * frame_bit_res, pba_hz);
00183 }
00184
00185
00186
00187
00188
00189
00190
00191
00192
00193
00194
00195
00196 if (mode != SSC_I2S_MODE_RIGHT_IN)
00197 {
00198
00199
00200
00201
00202
00203
00204
00205 if (mode != SSC_I2S_MODE_STEREO_OUT_EXT_CLK)
00206 {
00207
00208
00209
00210
00211
00212
00213
00214
00215
00216
00217
00218
00219
00220
00221
00222
00223
00224 ssc->tcmr = AVR32_SSC_TCMR_CKS_DIV_CLOCK << AVR32_SSC_TCMR_CKS_OFFSET |
00225 AVR32_SSC_TCMR_CKO_CONTINOUS_CLOCK_OUTPUT << AVR32_SSC_TCMR_CKO_OFFSET |
00226 0 << AVR32_SSC_TCMR_CKI_OFFSET |
00227 AVR32_SSC_TCMR_CKG_NONE << AVR32_SSC_TCMR_CKG_OFFSET |
00228 AVR32_SSC_TCMR_START_DETECT_ANY_EDGE_TF << AVR32_SSC_TCMR_START_OFFSET |
00229 1 << AVR32_SSC_TCMR_STTDLY_OFFSET |
00230 (frame_bit_res - 1) << AVR32_SSC_TCMR_PERIOD_OFFSET;
00231 }
00232 else
00233 {
00234
00235
00236
00237
00238
00239
00240
00241
00242
00243
00244
00245
00246
00247
00248 ssc->tcmr = AVR32_SSC_TCMR_CKS_RK_CLOCK << AVR32_SSC_TCMR_CKS_OFFSET |
00249 AVR32_SSC_TCMR_CKO_CONTINOUS_CLOCK_OUTPUT << AVR32_SSC_TCMR_CKO_OFFSET |
00250 0 << AVR32_SSC_TCMR_CKI_OFFSET |
00251 AVR32_SSC_TCMR_CKG_NONE << AVR32_SSC_TCMR_CKG_OFFSET |
00252 AVR32_SSC_TCMR_START_DETECT_ANY_EDGE_TF << AVR32_SSC_TCMR_START_OFFSET |
00253 1 << AVR32_SSC_TCMR_STTDLY_OFFSET |
00254 (frame_bit_res - 1) << AVR32_SSC_TCMR_PERIOD_OFFSET;
00255
00256
00257
00258 ssc->rcmr = (AVR32_SSC_RCMR_CKS_RK_PIN << AVR32_SSC_RCMR_CKS_OFFSET);
00259 }
00260
00261
00262
00263
00264
00265
00266
00267
00268
00269
00270
00271 #ifdef AVR32_SSC_220_H_INCLUDED
00272 ssc->tfmr = (data_bit_res - 1) << AVR32_SSC_TFMR_DATLEN_OFFSET |
00273 0 << AVR32_SSC_TFMR_DATDEF_OFFSET |
00274 1 << AVR32_SSC_TFMR_MSBF_OFFSET |
00275 (1 - 1) << AVR32_SSC_TFMR_DATNB_OFFSET |
00276 (((frame_bit_res - 1) << AVR32_SSC_TFMR_FSLEN_OFFSET) & AVR32_SSC_TFMR_FSLEN_MASK) |
00277 AVR32_SSC_TFMR_FSOS_NEG_PULSE << AVR32_SSC_TFMR_FSOS_OFFSET |
00278 0 << AVR32_SSC_TFMR_FSDEN_OFFSET |
00279 1 << AVR32_SSC_TFMR_FSEDGE_OFFSET;
00280 #else
00281 ssc->tfmr = (data_bit_res - 1) << AVR32_SSC_TFMR_DATLEN_OFFSET |
00282 0 << AVR32_SSC_TFMR_DATDEF_OFFSET |
00283 1 << AVR32_SSC_TFMR_MSBF_OFFSET |
00284 (1 - 1) << AVR32_SSC_TFMR_DATNB_OFFSET |
00285 (((frame_bit_res - 1) << AVR32_SSC_TFMR_FSLEN_OFFSET) & AVR32_SSC_TFMR_FSLEN_MASK) |
00286 AVR32_SSC_TFMR_FSOS_NEG_PULSE << AVR32_SSC_TFMR_FSOS_OFFSET |
00287 0 << AVR32_SSC_TFMR_FSDEN_OFFSET |
00288 1 << AVR32_SSC_TFMR_FSEDGE_OFFSET |
00289 ((frame_bit_res - 1) >> AVR32_SSC_TFMR_FSLEN_SIZE) << AVR32_SSC_TFMR_FSLENHI_OFFSET;
00290 #endif
00291 txen_mask = AVR32_SSC_CR_TXEN_MASK;
00292 }
00293
00294
00295 if ( (mode != SSC_I2S_MODE_STEREO_OUT) && (mode != SSC_I2S_MODE_STEREO_OUT_EXT_CLK) )
00296 {
00297
00298
00299
00300
00301
00302
00303 if ( (mode == SSC_I2S_MODE_STEREO_OUT_MONO_IN) || (mode == SSC_I2S_MODE_RIGHT_IN) )
00304 {
00305
00306
00307
00308
00309
00310
00311
00312
00313
00314
00315
00316 ssc->rcmr =
00317 (( mode == SSC_I2S_MODE_RIGHT_IN ? AVR32_SSC_RCMR_CKS_RK_PIN : AVR32_SSC_RCMR_CKS_TK_CLOCK )
00318 << AVR32_SSC_RCMR_CKS_OFFSET)|
00319 (AVR32_SSC_RCMR_CKO_INPUT_ONLY << AVR32_SSC_RCMR_CKO_OFFSET)|
00320 (1 << AVR32_SSC_RCMR_CKI_OFFSET)|
00321 (AVR32_SSC_RCMR_CKG_NONE << AVR32_SSC_RCMR_CKG_OFFSET)|
00322 (( mode == SSC_I2S_MODE_RIGHT_IN ? AVR32_SSC_RCMR_START_DETECT_RISING_RF : AVR32_SSC_RCMR_START_TRANSMIT_START )
00323 << AVR32_SSC_RCMR_START_OFFSET)|
00324 (1 << AVR32_SSC_RCMR_STTDLY_OFFSET)|
00325 (0 << AVR32_SSC_RCMR_PERIOD_OFFSET);
00326
00327
00328
00329
00330
00331
00332
00333
00334
00335
00336 ssc->rfmr =
00337 ((data_bit_res-1) << AVR32_SSC_RFMR_DATLEN_OFFSET)|
00338 (0 << AVR32_SSC_RFMR_LOOP_OFFSET)|
00339 (1 << AVR32_SSC_RFMR_MSBF_OFFSET)|
00340 (0 << AVR32_SSC_RFMR_DATNB_OFFSET)|
00341 (0 << AVR32_SSC_RFMR_FSLEN_OFFSET)|
00342 (AVR32_SSC_RFMR_FSOS_INPUT_ONLY << AVR32_SSC_RFMR_FSOS_OFFSET)|
00343 (0 << AVR32_SSC_RFMR_FSEDGE_OFFSET);
00344
00345 rxen_mask = AVR32_SSC_CR_RXEN_MASK;
00346 }
00347 else
00348 {
00349
00350
00351
00352
00353 ssc->rcmr = AVR32_SSC_RCMR_CKS_TK_CLOCK << AVR32_SSC_RCMR_CKS_OFFSET |
00354 AVR32_SSC_RCMR_CKO_CONTINOUS_CLOCK_OUTPUT << AVR32_SSC_RCMR_CKO_OFFSET |
00355 0 << AVR32_SSC_RCMR_CKI_OFFSET |
00356 AVR32_SSC_RCMR_CKG_NONE << AVR32_SSC_RCMR_CKG_OFFSET |
00357 AVR32_SSC_RCMR_START_DETECT_ANY_EDGE_RF << AVR32_SSC_RCMR_START_OFFSET |
00358 1 << AVR32_SSC_RCMR_STTDLY_OFFSET |
00359 (frame_bit_res - 1) << AVR32_SSC_RCMR_PERIOD_OFFSET;
00360
00361 #ifdef AVR32_SSC_220_H_INCLUDED
00362 ssc->rfmr = (data_bit_res - 1) << AVR32_SSC_RFMR_DATLEN_OFFSET |
00363 1 << AVR32_SSC_RFMR_MSBF_OFFSET |
00364 (1 - 1) << AVR32_SSC_RFMR_DATNB_OFFSET |
00365 (((frame_bit_res - 1) << AVR32_SSC_RFMR_FSLEN_OFFSET) & AVR32_SSC_TFMR_FSLEN_MASK) |
00366 AVR32_SSC_RFMR_FSOS_NEG_PULSE << AVR32_SSC_RFMR_FSOS_OFFSET |
00367 1 << AVR32_SSC_RFMR_FSEDGE_OFFSET;
00368 #else
00369 ssc->rfmr = (data_bit_res - 1) << AVR32_SSC_RFMR_DATLEN_OFFSET |
00370 1 << AVR32_SSC_RFMR_MSBF_OFFSET |
00371 (1 - 1) << AVR32_SSC_RFMR_DATNB_OFFSET |
00372 (((frame_bit_res - 1) << AVR32_SSC_RFMR_FSLEN_OFFSET) & AVR32_SSC_TFMR_FSLEN_MASK) |
00373 AVR32_SSC_RFMR_FSOS_NEG_PULSE << AVR32_SSC_RFMR_FSOS_OFFSET |
00374 1 << AVR32_SSC_RFMR_FSEDGE_OFFSET |
00375 ((frame_bit_res - 1) >> AVR32_SSC_RFMR_FSLEN_SIZE) << AVR32_SSC_RFMR_FSLENHI_OFFSET;
00376 #endif
00377 rxen_mask = AVR32_SSC_CR_RXEN_MASK;
00378 }
00379
00380 }
00381
00382 ssc->cr = txen_mask | rxen_mask;
00383 }
00384
00385 return SSC_I2S_OK;
00386 }
00387
00388
00389 int ssc_i2s_transfer(volatile avr32_ssc_t *ssc, unsigned int data)
00390 {
00391 unsigned int timeout = SSC_I2S_TIMEOUT_VALUE;
00392
00393 while( ( ssc->sr & (1<<AVR32_SSC_SR_TXRDY_OFFSET) ) == 0 &&
00394 timeout > 0 ) {
00395 timeout--;
00396 }
00397
00398 if( timeout <= 0 ) {
00399 return SSC_I2S_TIMEOUT;
00400 }
00401
00402 ssc->thr = data;
00403
00404 return SSC_I2S_OK;
00405 }
00406
00407
00408 void ssc_i2s_disable_interrupts(volatile avr32_ssc_t *ssc, unsigned long int_mask)
00409 {
00410 Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00411
00412 if (global_interrupt_enabled) Disable_global_interrupt();
00413 ssc->idr = int_mask;
00414 ssc->sr;
00415 if (global_interrupt_enabled) Enable_global_interrupt();
00416 }
00417
00418
00419 void ssc_i2s_enable_interrupts(volatile avr32_ssc_t *ssc, unsigned long int_mask)
00420 {
00421 ssc->ier = int_mask;
00422 }
00423
00424
00425 unsigned long ssc_i2s_get_status(volatile avr32_ssc_t *ssc)
00426 {
00427 return ssc->sr;
00428 }