platform_spi.h File Reference

#include <inttypes.h>
#include "spb.h"

Go to the source code of this file.

Defines

#define MAX_BLOCK_LEN   512

Enumerations

enum  { IRQ_OP_ENABLE, IRQ_OP_DISABLE }
enum  { SPI_FLAG_POLL = (1 << 0) }
enum  { SPI_IRQ_RX = (1 << 0) }

Functions

void platform_init (uint8_t *flags)
void platform_reset (void)
void platform_spi_cs (uint8_t enable)
void platform_spi_irq (uint8_t op)
void platform_txrx (const uint8_t *in, uint8_t *out, uint16_t len)
void spi_irq_handler (uint8_t status)


Define Documentation

#define MAX_BLOCK_LEN   512

Definition at line 33 of file platform_spi.h.


Enumeration Type Documentation

anonymous enum

Enumerator:
IRQ_OP_ENABLE 
IRQ_OP_DISABLE 

Definition at line 35 of file platform_spi.h.

00035      {
00036         IRQ_OP_ENABLE,
00037         IRQ_OP_DISABLE
00038 };

anonymous enum

Enumerator:
SPI_FLAG_POLL 

Definition at line 40 of file platform_spi.h.

00040      {
00041         SPI_FLAG_POLL = (1 << 0),
00042 };

anonymous enum

Enumerator:
SPI_IRQ_RX 

Definition at line 45 of file platform_spi.h.

00045      {
00046     SPI_IRQ_RX = (1 << 0),
00047 };


Function Documentation

void platform_init ( uint8_t *  flags  ) 

void platform_reset ( void   ) 

Definition at line 164 of file avr32_spi.c.

00165 {
00166         volatile avr32_spi_t *spi = &AVR32_SPI;
00167 #if SPI_CS == 1
00168         volatile avr32_spi_csr1_t* CSR = &spi->CSR1;
00169 #elif SPI_CS == 2
00170         volatile avr32_spi_csr2_t* CSR = &spi->CSR2;
00171 #endif
00172         
00173         /* Disable SPI controller during configuration */
00174         spi->CR.spidis = 1;
00175 
00176         /* SPI master mode */
00177         spi->MR.mstr = 1;
00178 
00179         /* fixed peripheral select */
00180         spi->MR.ps = 0;
00181 #if SPI_CS == 2
00182         spi->MR.pcs = 0x3; /* cs2 */
00183 #elif SPI_CS == 1
00184         spi->MR.pcs = 0x1; /* cs1 */
00185 #endif
00186 
00187         CSR->scbr = 2;
00188 
00189         /* Use max width of TDR register, 16 bit transfers */
00190     CSR->bits = 0x8; 
00191 
00192         /* Make sure that we can hold CS low until transfer is completed, e.g
00193          * LASTXFER is set in TDR.
00194          */
00195         CSR->csaat = 1;
00196 
00197         /* NRG component requires clock polarity high */
00198         CSR->cpol = 1;
00199 
00200         /* Enable SPI controller */
00201         spi->CR.spien = 1;
00202 }

void platform_spi_cs ( uint8_t  enable  ) 

void platform_spi_irq ( uint8_t  op  ) 

void platform_txrx ( const uint8_t *  in,
uint8_t *  out,
uint16_t  len 
)

void spi_irq_handler ( uint8_t  status  ) 

Referenced by avr32_irq_handler().


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