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00049 #include "compiler.h"
00050 #include "pwm4.h"
00051
00052 int pwm_write_protect_hw_lock(int group)
00053 {
00054 volatile avr32_pwm_t *pwm = &AVR32_PWM;
00055 switch(group)
00056 {
00057 case 0:
00058 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00059 AVR32_PWM_WPCR_WPRG0_MASK |
00060 (AVR32_PWM_WPCR_WPCMD_HWENA << AVR32_PWM_WPCR_WPCMD);
00061 if (pwm->wpsr != (AVR32_PWM_WPSR_WPHWS0_YES << AVR32_PWM_WPSR_WPHWS0)) return PWM_FAILURE;
00062 break;
00063 case 1:
00064 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00065 AVR32_PWM_WPCR_WPRG1_MASK |
00066 (AVR32_PWM_WPCR_WPCMD_HWENA << AVR32_PWM_WPCR_WPCMD);
00067 if (pwm->wpsr != (AVR32_PWM_WPSR_WPHWS1_YES << AVR32_PWM_WPSR_WPHWS1)) return PWM_FAILURE;
00068 break;
00069 case 2:
00070 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00071 AVR32_PWM_WPCR_WPRG2_MASK |
00072 (AVR32_PWM_WPCR_WPCMD_HWENA << AVR32_PWM_WPCR_WPCMD);
00073 if (pwm->wpsr != (AVR32_PWM_WPSR_WPHWS2_YES << AVR32_PWM_WPSR_WPHWS2)) return PWM_FAILURE;
00074 break;
00075 case 3:
00076 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00077 AVR32_PWM_WPCR_WPRG3_MASK |
00078 (AVR32_PWM_WPCR_WPCMD_HWENA << AVR32_PWM_WPCR_WPCMD);
00079 if (pwm->wpsr != (AVR32_PWM_WPSR_WPHWS3_YES << AVR32_PWM_WPSR_WPHWS3)) return PWM_FAILURE;
00080 break;
00081 case 4:
00082 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00083 AVR32_PWM_WPCR_WPRG4_MASK |
00084 (AVR32_PWM_WPCR_WPCMD_HWENA << AVR32_PWM_WPCR_WPCMD);
00085 if (pwm->wpsr != (AVR32_PWM_WPSR_WPHWS4_YES << AVR32_PWM_WPSR_WPHWS4)) return PWM_FAILURE;
00086 break;
00087 case 5:
00088 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00089 AVR32_PWM_WPCR_WPRG5_MASK |
00090 (AVR32_PWM_WPCR_WPCMD_HWENA << AVR32_PWM_WPCR_WPCMD);
00091 if (pwm->wpsr != (AVR32_PWM_WPSR_WPHWS5_YES << AVR32_PWM_WPSR_WPHWS5)) return PWM_FAILURE;
00092 break;
00093 }
00094 return PWM_SUCCESS;
00095 }
00096
00097 int pwm_write_protect_sw_lock(int group)
00098 {
00099 volatile avr32_pwm_t *pwm = &AVR32_PWM;
00100 switch(group)
00101 {
00102 case 0:
00103 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00104 AVR32_PWM_WPCR_WPRG0_MASK |
00105 (AVR32_PWM_WPCR_WPCMD_SWENA << AVR32_PWM_WPCR_WPCMD);
00106 if (pwm->wpsr != (AVR32_PWM_WPSR_WPSWS0_YES << AVR32_PWM_WPSR_WPSWS0)) return PWM_FAILURE;
00107 break;
00108 case 1:
00109 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00110 AVR32_PWM_WPCR_WPRG1_MASK |
00111 (AVR32_PWM_WPCR_WPCMD_SWENA << AVR32_PWM_WPCR_WPCMD);
00112 if (pwm->wpsr != (AVR32_PWM_WPSR_WPSWS1_YES << AVR32_PWM_WPSR_WPSWS1)) return PWM_FAILURE;
00113 break;
00114 case 2:
00115 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00116 AVR32_PWM_WPCR_WPRG2_MASK |
00117 (AVR32_PWM_WPCR_WPCMD_SWENA << AVR32_PWM_WPCR_WPCMD);
00118 if (pwm->wpsr != (AVR32_PWM_WPSR_WPSWS2_YES << AVR32_PWM_WPSR_WPSWS2)) return PWM_FAILURE;
00119 break;
00120 case 3:
00121 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00122 AVR32_PWM_WPCR_WPRG3_MASK |
00123 (AVR32_PWM_WPCR_WPCMD_SWENA << AVR32_PWM_WPCR_WPCMD);
00124 if (pwm->wpsr != (AVR32_PWM_WPSR_WPSWS3_YES << AVR32_PWM_WPSR_WPSWS3)) return PWM_FAILURE;
00125 break;
00126 case 4:
00127 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00128 AVR32_PWM_WPCR_WPRG4_MASK |
00129 (AVR32_PWM_WPCR_WPCMD_SWENA << AVR32_PWM_WPCR_WPCMD);
00130 if (pwm->wpsr != (AVR32_PWM_WPSR_WPSWS4_YES << AVR32_PWM_WPSR_WPSWS4)) return PWM_FAILURE;
00131 break;
00132 case 5:
00133 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00134 AVR32_PWM_WPCR_WPRG5_MASK |
00135 (AVR32_PWM_WPCR_WPCMD_SWENA << AVR32_PWM_WPCR_WPCMD);
00136 if (pwm->wpsr != (AVR32_PWM_WPSR_WPSWS5_YES << AVR32_PWM_WPSR_WPSWS5)) return PWM_FAILURE;
00137 break;
00138 }
00139 return PWM_SUCCESS;
00140 }
00141
00142 int pwm_write_protect_sw_unlock(int group)
00143 {
00144 volatile avr32_pwm_t *pwm = &AVR32_PWM;
00145 switch(group)
00146 {
00147 case 0:
00148 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00149 AVR32_PWM_WPCR_WPRG0_MASK |
00150 (AVR32_PWM_WPCR_WPCMD_SWDIS << AVR32_PWM_WPCR_WPCMD);
00151 if (pwm->wpsr != 0) return PWM_FAILURE;
00152 break;
00153 case 1:
00154 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00155 AVR32_PWM_WPCR_WPRG1_MASK |
00156 (AVR32_PWM_WPCR_WPCMD_SWDIS << AVR32_PWM_WPCR_WPCMD);
00157 if (pwm->wpsr != 0) return PWM_FAILURE;
00158 break;
00159 case 2:
00160 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00161 AVR32_PWM_WPCR_WPRG2_MASK |
00162 (AVR32_PWM_WPCR_WPCMD_SWDIS << AVR32_PWM_WPCR_WPCMD);
00163 if (pwm->wpsr != 0) return PWM_FAILURE;
00164 break;
00165 case 3:
00166 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00167 AVR32_PWM_WPCR_WPRG3_MASK |
00168 (AVR32_PWM_WPCR_WPCMD_SWDIS << AVR32_PWM_WPCR_WPCMD);
00169 if (pwm->wpsr != 0) return PWM_FAILURE;
00170 break;
00171 case 4:
00172 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00173 AVR32_PWM_WPCR_WPRG4_MASK |
00174 (AVR32_PWM_WPCR_WPCMD_SWDIS << AVR32_PWM_WPCR_WPCMD);
00175 if (pwm->wpsr != 0) return PWM_FAILURE;
00176 break;
00177 case 5:
00178 pwm->wpcr = (AVR32_PWM_WPCR_WPKEY_KEY << AVR32_PWM_WPCR_WPKEY) |
00179 AVR32_PWM_WPCR_WPRG5_MASK |
00180 (AVR32_PWM_WPCR_WPCMD_SWDIS << AVR32_PWM_WPCR_WPCMD);
00181 if (pwm->wpsr != 0) return PWM_FAILURE;
00182 break;
00183 }
00184 return PWM_SUCCESS;
00185 }
00186
00187 U32 pwm_write_protect_status()
00188 {
00189 volatile avr32_pwm_t *pwm = &AVR32_PWM;
00190 U32 status;
00191 status = pwm->wpsr;
00192 if (status&AVR32_PWM_WPSR_WPVS_MASK)
00193 return ((status&AVR32_PWM_WPSR_WPVSRC_MASK)>>AVR32_PWM_WPSR_WPVSRC_OFFSET);
00194 else
00195 return PWM_NO_WRITE_PROTECT_VIOLATION;
00196 }
00197
00198 int pwm_init(pwm_opt_t *opt)
00199 {
00200 volatile avr32_pwm_t *pwm = &AVR32_PWM;
00201 Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00202
00203 if (opt == 0 )
00204 return PWM_INVALID_INPUT;
00205
00206
00207 pwm_write_protect_sw_unlock(0);
00208 pwm_write_protect_sw_unlock(1);
00209 pwm_write_protect_sw_unlock(2);
00210 pwm_write_protect_sw_unlock(3);
00211
00212
00213 if (global_interrupt_enabled) Disable_global_interrupt();
00214 pwm->idr1 = ((1 << (AVR32_PWM_LINES_MSB + 1)) - 1) << AVR32_PWM_IDR1_CHID0_OFFSET;
00215 if (opt->fault_detection_activated)
00216 pwm->idr1 |= ((1 << (AVR32_PWM_LINES_MSB + 1)) - 1) << AVR32_PWM_IDR1_FCHID0_OFFSET;
00217 pwm->isr1;
00218
00219 if (opt->sync_channel_activated)
00220 {
00221 pwm->idr2 = (1 << AVR32_PWM_IDR2_UNRE_OFFSET) | (1 << AVR32_PWM_IDR2_WRDY_OFFSET);
00222 if (opt->sync_update_channel_mode==PWM_SYNC_UPDATE_AUTO_WRITE_AUTO_UPDATE)
00223 pwm->idr2 |= (1 << AVR32_PWM_IDR2_ENDTX_OFFSET) | (1 << AVR32_PWM_IDR2_TXBUFE_OFFSET);
00224 pwm->isr2;
00225 }
00226 if (global_interrupt_enabled) Enable_global_interrupt();
00227
00228
00229 pwm->clk =
00230 ((opt->diva)<<AVR32_PWM_DIVA_OFFSET) |
00231 ((opt->divb)<<AVR32_PWM_DIVB_OFFSET) |
00232 ((opt->prea)<<AVR32_PWM_PREA_OFFSET) |
00233 ((opt->preb)<<AVR32_PWM_PREB_OFFSET) |
00234 ((opt->cksel)<<AVR32_PWM_CLKSEL_OFFSET)
00235 ;
00236
00237
00238 pwm->SCM.updm = opt->sync_update_channel_mode;
00239 int i;
00240 for (i=0;i<PWM_OOV_LINES;i++)
00241 {
00242 pwm->scm |= ((opt->sync_channel_select[i])<<(AVR32_PWM_SCM_SYNC0_OFFSET+i));
00243 }
00244
00245 return PWM_SUCCESS;
00246 }
00247
00248 int pwm_channel_init( unsigned int channel_id, const avr32_pwm_channel_t *pwm_channel)
00249 {
00250 volatile avr32_pwm_t *pwm = &AVR32_PWM;
00251
00252 if (pwm_channel == 0)
00253 return PWM_INVALID_ARGUMENT;
00254 if (channel_id > AVR32_PWM_LINES_MSB)
00255 return PWM_INVALID_INPUT;
00256
00257 pwm->channel[channel_id].cmr= pwm_channel->cmr;
00258 pwm->channel[channel_id].cdty= pwm_channel->cdty;
00259 pwm->channel[channel_id].cprd= pwm_channel->cprd;
00260
00261 return PWM_SUCCESS;
00262 }
00263
00264 int pwm_start_channels(unsigned long channels_bitmask)
00265 {
00266 volatile avr32_pwm_t *pwm = &AVR32_PWM;
00267 if (channels_bitmask & ~((1 << (AVR32_PWM_LINES_MSB + 1)) - 1))
00268 return PWM_INVALID_INPUT;
00269
00270
00271 pwm->ena = channels_bitmask;
00272
00273 return PWM_SUCCESS;
00274 }
00275
00276 int pwm_stop_channels(unsigned long channels_bitmask)
00277 {
00278 if (channels_bitmask & ~((1 << (AVR32_PWM_LINES_MSB + 1)) - 1))
00279 return PWM_INVALID_INPUT;
00280
00281 AVR32_PWM.dis = channels_bitmask;
00282
00283 return PWM_SUCCESS;
00284 }
00285
00286 int pwm_update_channel(unsigned int channel_id, const avr32_pwm_channel_t *pwm_channel)
00287 {
00288 volatile avr32_pwm_t *pwm = &AVR32_PWM;
00289
00290 if (channel_id > AVR32_PWM_LINES_MSB)
00291 return PWM_INVALID_INPUT;
00292
00293 AVR32_PWM.isr1;
00294 while (!(AVR32_PWM.isr1 & (1 << channel_id)));
00295 pwm->channel[channel_id].cdtyupd= pwm_channel->cdtyupd;
00296 pwm->channel[channel_id].cprdupd= pwm_channel->cprdupd;
00297 pwm->channel[channel_id].dtupd= pwm_channel->dtupd;
00298
00299 return PWM_SUCCESS;
00300 }
00301
00302 int pwm_interrupt_update_channel(unsigned int channel_id, const avr32_pwm_channel_t *pwm_channel)
00303 {
00304 volatile avr32_pwm_t *pwm = &AVR32_PWM;
00305
00306 if (channel_id > AVR32_PWM_LINES_MSB)
00307 return PWM_INVALID_INPUT;
00308
00309 pwm->channel[channel_id].cdtyupd= pwm_channel->cdtyupd;
00310 pwm->channel[channel_id].cprdupd= pwm_channel->cprdupd;
00311 pwm->channel[channel_id].dtupd= pwm_channel->dtupd;
00312
00313 return PWM_SUCCESS;
00314 }
00315
00316 int pwm_output_override_setup(pwm_output_override_opt_t *opt)
00317 {
00318 if (opt == 0 )
00319 return PWM_INVALID_INPUT;
00320
00321 AVR32_PWM.oov = 0;
00322 int i;
00323 for (i=0;i<PWM_OOV_LINES;i++)
00324 {
00325 AVR32_PWM.oov = ((opt->oov[0][i]<<(AVR32_PWM_OOVH0_OFFSET+i))|(opt->oov[1][i]<<(AVR32_PWM_OOVL0_OFFSET+i)));
00326 }
00327
00328 return PWM_SUCCESS;
00329 }
00330
00331 int pwm_output_override_write(pwm_output_override_opt_t *opt)
00332 {
00333 if (opt == 0 )
00334 return PWM_INVALID_INPUT;
00335
00336 U32 tmp=0;
00337 int i;
00338 for (i=0;i<PWM_OOV_LINES;i++)
00339 {
00340 if (opt->os[0][i])
00341 tmp |= (1<<(AVR32_PWM_OSH0_OFFSET+i));
00342 else
00343 tmp &= ~(1<<(AVR32_PWM_OSH0_OFFSET+i));
00344 if (opt->os[1][i])
00345 tmp |= (1<<(AVR32_PWM_OSL0_OFFSET+i));
00346 else
00347 tmp &= ~(1<<(AVR32_PWM_OSL0_OFFSET+i));
00348 }
00349 AVR32_PWM.os = tmp;
00350 return PWM_SUCCESS;
00351 }
00352
00353 int pwm_update_period_value(unsigned int value)
00354 {
00355 AVR32_PWM.scup = value;
00356 return PWM_SUCCESS;
00357 }
00358
00359 int pwm_synchronous_prepare_update(unsigned int channel_id, const avr32_pwm_channel_t *pwm_channel)
00360 {
00361 volatile avr32_pwm_t *pwm = &AVR32_PWM;
00362
00363 if (channel_id > AVR32_PWM_LINES_MSB)
00364 return PWM_INVALID_INPUT;
00365
00366 AVR32_PWM.isr1;
00367 while (!(AVR32_PWM.isr1 & (1 << channel_id)));
00368 pwm->channel[channel_id].cdtyupd= pwm_channel->cdtyupd;
00369 pwm->channel[channel_id].cprdupd= pwm_channel->cprdupd;
00370 return PWM_SUCCESS;
00371 }
00372
00373 int pwm_update_manual_write_manual_update()
00374 {
00375 AVR32_PWM.scuc = (1<<AVR32_PWM_SCUC_UPDULOCK_OFFSET);
00376 return PWM_SUCCESS;
00377 }
00378
00379 int pwm_update_manual_write_auto_update()
00380 {
00381 while(!AVR32_PWM.ISR2.wrdy);
00382 return PWM_SUCCESS;
00383 }
00384
00385 int pwm_update_auto_write_auto_update_check_ready()
00386 {
00387 while(!AVR32_PWM.ISR2.wrdy);
00388 return PWM_SUCCESS;
00389 }
00390
00391 int pwm_update_auto_write_auto_update_check_eot()
00392 {
00393 while(!AVR32_PWM.ISR2.endtx);
00394 return PWM_SUCCESS;
00395 }
00396
00397 int pwm_fault_lines_polarity_setup(U8 line,
00398 U8 polarity,
00399 U8 mode,
00400 U8 filter)
00401 {
00402 if ((line > 8 ) ||
00403 (polarity > 1 ) ||
00404 (mode > 1 )||
00405 (filter > 1 ))
00406 return PWM_INVALID_INPUT;
00407
00408 if (polarity)
00409 AVR32_PWM.fmr |= (polarity<<(AVR32_PWM_FPOL0_OFFSET+line));
00410 else
00411 AVR32_PWM.fmr &= ~(polarity<<(AVR32_PWM_FPOL0_OFFSET+line));
00412
00413 if (mode)
00414 AVR32_PWM.fmr |= (mode<<(AVR32_PWM_FMOD0_OFFSET+line));
00415 else
00416 AVR32_PWM.fmr &= ~(mode<<(AVR32_PWM_FMOD0_OFFSET+line));
00417
00418 if (filter)
00419 AVR32_PWM.fmr |= (filter<<(AVR32_PWM_FFIL0_OFFSET+line));
00420 else
00421 AVR32_PWM.fmr &= ~(filter<<(AVR32_PWM_FFIL0_OFFSET+line));
00422
00423 return PWM_SUCCESS;
00424 }
00425
00426 int pwm_fault_lines_level_setup(U8 line,
00427 U8 channel_high,
00428 U8 channel_low)
00429 {
00430 if ((line > 8 ) ||
00431 (channel_high > 1 ) ||
00432 (channel_low > 1 ))
00433 return PWM_INVALID_INPUT;
00434
00435 if (channel_high)
00436 AVR32_PWM.fpv |= (channel_high<<(AVR32_PWM_FPVH0_OFFSET+line));
00437 else
00438 AVR32_PWM.fpv &= ~(channel_high<<(AVR32_PWM_FPVH0_OFFSET+line));
00439
00440 if (channel_low)
00441 AVR32_PWM.fpv |= (channel_low<<(AVR32_PWM_FPVL0_OFFSET+line));
00442 else
00443 AVR32_PWM.fpv &= ~(channel_low<<(AVR32_PWM_FPVL0_OFFSET+line));
00444
00445 return PWM_SUCCESS;
00446 }
00447
00448 int pwm_fault_lines_enable(U8 line,
00449 U8 channel)
00450 {
00451 if (channel > 4 )
00452 return PWM_INVALID_INPUT;
00453
00454 if (channel)
00455 AVR32_PWM.fpe1 |= (line<<(AVR32_PWM_FPE1_OFFSET+8*channel));
00456 else
00457 AVR32_PWM.fpe1 &= ~(line<<(AVR32_PWM_FPE1_OFFSET+8*channel));
00458
00459 return PWM_SUCCESS;
00460 }
00461
00462 int pwm_get_fault_status()
00463 {
00464 return AVR32_PWM.fsr;
00465 }
00466
00467 void pwm_clr_fault_status()
00468 {
00469 AVR32_PWM.fcr = 0xffff;
00470 }
00471
00472
00473 int pwm_compare_match_setup(int line,pwm_compare_opt_t *pwm_compare_t)
00474 {
00475 if (line > AVR32_PWM_CMP_NUM)
00476 return PWM_INVALID_INPUT;
00477
00478
00479 AVR32_PWM.comp[line].CMP0V.cv =
00480 ((pwm_compare_t->compare_pwm_counter_value<<AVR32_PWM_CMP0V_CV_OFFSET) |
00481 (pwm_compare_t->compare_mode<<AVR32_PWM_CMP0V_CVM_OFFSET));
00482
00483
00484 AVR32_PWM.comp[line].cmp0m =
00485 (((pwm_compare_t->compare_pwm_period_counter_value)<< AVR32_PWM_CMP0M_CTR_OFFSET) |
00486 ((pwm_compare_t->compare_period_counter_value) << AVR32_PWM_CMP0M_CPR_OFFSET) |
00487 ((pwm_compare_t->compare_pwm_update_period) << AVR32_PWM_CMP0M_CUPR_OFFSET) |
00488 ((pwm_compare_t->compare_status) << AVR32_PWM_CMP0M_CEN_OFFSET));
00489
00490
00491 return PWM_SUCCESS;
00492 }
00493
00494
00495 int pwm_compare_match_reload_setup(int line,pwm_compare_opt_t *pwm_compare_t)
00496 {
00497 if (line > AVR32_PWM_CMP_NUM)
00498 return PWM_INVALID_INPUT;
00499
00500
00501 AVR32_PWM.comp[line].CMP0VUPD.cvupd =
00502 ((pwm_compare_t->compare_pwm_counter_value<<AVR32_PWM_CMP0VUPD_CVUPD_OFFSET) |
00503 (pwm_compare_t->compare_mode<<AVR32_PWM_CMP0VUPD_CVMUPD_OFFSET));
00504
00505
00506 AVR32_PWM.comp[line].cmp0mupd =
00507 (((pwm_compare_t->compare_pwm_period_counter_value)<< AVR32_PWM_CMP0MUPD_CTRUPD_OFFSET) |
00508 ((pwm_compare_t->compare_period_counter_value) << AVR32_PWM_CMP0MUPD_CPRUPD_OFFSET) |
00509 ((pwm_compare_t->compare_pwm_update_period) << AVR32_PWM_CMP0MUPD_CUPRUPD_OFFSET) |
00510 ((pwm_compare_t->compare_status) << AVR32_PWM_CMP0MUPD_CENUPD_OFFSET));
00511
00512 return PWM_SUCCESS;
00513 }
00514
00515 int pwm_compare_event_enable(int line, int event_line)
00516 {
00517 if (line > AVR32_PWM_CMP_NUM)
00518 return PWM_INVALID_INPUT;
00519
00520
00521 AVR32_PWM.elxmr[line] = event_line;
00522
00523 return PWM_SUCCESS;
00524 }
00525
00526 int pwm_compare_event_disable(int line, int event_line)
00527 {
00528 if (line > AVR32_PWM_CMP_NUM)
00529 return PWM_INVALID_INPUT;
00530
00531
00532 AVR32_PWM.elxmr[line] &= (~event_line);
00533
00534 return PWM_SUCCESS;
00535 }