This file defines a useful set of functions for the AES on AVR32 devices.
Definition in file aes.h.
#include <avr32/io.h>
#include "compiler.h"
Go to the source code of this file.
Data Structures | |
struct | aes_config_t |
AES Configuration structure. More... | |
struct | aes_isrconfig_t |
AES Interrupt configuration structure. More... | |
Defines | |
#define | AES_CBC_MODE 1 |
#define | AES_CFB_MODE 3 |
#define | AES_CTR_MODE 4 |
#define | AES_ECB_MODE 0 |
AES Operation cipher mode. | |
#define | AES_KEY_SIZE_128 0 |
AES Cryptographic key size. | |
#define | AES_KEY_SIZE_192 1 |
#define | AES_KEY_SIZE_256 2 |
#define | AES_OFB_MODE 2 |
#define | AES_PMODE_CIPHER 1 |
#define | AES_PMODE_DECIPHER 0 |
AES Processing mode. | |
#define | AES_START_MODE_AUTO 1 |
#define | AES_START_MODE_DMA 2 |
#define | AES_START_MODE_MANUAL 0 |
AES Start mode. | |
#define | AES_URAT_INPUTWRITE_DMA 0 |
AES URAD Type. | |
#define | AES_URAT_MRWRITE_PROCESS 2 |
#define | AES_URAT_MRWRITE_SUBKEY 4 |
#define | AES_URAT_OUTPUTREAD_PROCESS 1 |
#define | AES_URAT_OUTPUTREAD_SUBKEY 3 |
#define | AES_URAT_READ_WRITEONLY 5 |
Functions | |
void | aes_configure (volatile avr32_aes_t *aes, const aes_config_t *pAesConfig) |
Configure the AES. | |
unsigned int | aes_get_status (volatile avr32_aes_t *aes) |
Get the AES status. | |
void | aes_isr_configure (volatile avr32_aes_t *aes, const aes_isrconfig_t *pAesIsrConfig) |
Configure the AES interrupts. | |
__inline__ void | aes_load_newseed (volatile avr32_aes_t *aes) |
Trigger the load of a new seed in the AES internal random number generator (used for security counter measures). | |
void | aes_read_outputdata (volatile avr32_aes_t *aes, unsigned int *pOut) |
Read the 128/64/32/16/8bit input data. | |
void | aes_set_initvector (volatile avr32_aes_t *aes, const unsigned int *pVector) |
Set the 128bit initialization vector (for the CBC, CFB, OFB & CTR cipher modes). | |
void | aes_set_key (volatile avr32_aes_t *aes, const unsigned int *pKey) |
Set the 128/192/256bit cryptographic key. | |
__inline__ void | aes_start (volatile avr32_aes_t *aes) |
Start the cipher/decipher process [manual mode only]. | |
__inline__ void | aes_swreset (volatile avr32_aes_t *aes) |
Perform a software reset of the AES. | |
void | aes_write_inputdata (volatile avr32_aes_t *aes, const unsigned int *pIn) |
Write the 128/64/32/16/8bit input data. |
#define AES_CFB_MODE 3 |
Definition at line 74 of file aes.h.
Referenced by aes_read_outputdata(), and aes_write_inputdata().
#define AES_ECB_MODE 0 |
#define AES_KEY_SIZE_128 0 |
#define AES_PMODE_DECIPHER 0 |
#define AES_START_MODE_MANUAL 0 |
#define AES_URAT_READ_WRITEONLY 5 |
void aes_configure | ( | volatile avr32_aes_t * | aes, | |
const aes_config_t * | pAesConfig | |||
) |
Configure the AES.
*aes | Base address of the AES | |
*pAesConfig | Parameters for the AES configuration |
Definition at line 57 of file aes.c.
References AES_CKEY, aes_config_t::CFBSize, aes_config_t::CounterMeasureMask, aes_config_t::KeySize, aes_config_t::LodMode, aes_config_t::OpMode, aes_config_t::ProcessingDelay, aes_config_t::ProcessingMode, and aes_config_t::StartMode.
Referenced by main().
00058 { 00059 aes->mr = ((pAesConfig->ProcessingMode << AVR32_AES_MR_CIPHER_OFFSET) & AVR32_AES_MR_CIPHER_MASK) | 00060 ((pAesConfig->ProcessingDelay << AVR32_AES_MR_PROCDLY_OFFSET) & AVR32_AES_MR_PROCDLY_MASK) | 00061 ((pAesConfig->StartMode << AVR32_AES_MR_SMOD_OFFSET) & AVR32_AES_MR_SMOD_MASK) | 00062 ((pAesConfig->KeySize << AVR32_AES_MR_KEYSIZE_OFFSET) & AVR32_AES_MR_KEYSIZE_MASK) | 00063 ((pAesConfig->OpMode << AVR32_AES_MR_OPMOD_OFFSET) & AVR32_AES_MR_OPMOD_MASK) | 00064 ((pAesConfig->LodMode << AVR32_AES_MR_LOD_OFFSET) & AVR32_AES_MR_LOD_MASK) | 00065 ((pAesConfig->CFBSize << AVR32_AES_MR_CFBS_OFFSET) & AVR32_AES_MR_CFBS_MASK) | 00066 ((pAesConfig->CounterMeasureMask << AVR32_AES_MR_CTYPE_OFFSET) & AVR32_AES_MR_CTYPE_MASK) | 00067 ((AES_CKEY << AVR32_AES_MR_CKEY_OFFSET) & AVR32_AES_MR_CKEY_MASK); 00068 }
unsigned int aes_get_status | ( | volatile avr32_aes_t * | aes | ) |
Get the AES status.
*aes | Base address of the AES |
Definition at line 88 of file aes.c.
Referenced by aes_int_handler().
void aes_isr_configure | ( | volatile avr32_aes_t * | aes, | |
const aes_isrconfig_t * | pAesIsrConfig | |||
) |
Configure the AES interrupts.
*aes | Base address of the AES | |
*pAesIsrConfig | Parameters for the AES interrupts configuration |
Definition at line 71 of file aes.c.
References aes_isrconfig_t::datrdy, and aes_isrconfig_t::urad.
Referenced by main().
00072 { 00073 Bool global_interrupt_enabled = Is_global_interrupt_enabled(); 00074 00075 00076 // Enable the appropriate interrupts. 00077 aes->ier = pAesIsrConfig->datrdy << AVR32_AES_IER_DATRDY_OFFSET | 00078 pAesIsrConfig->urad << AVR32_AES_IER_URAD_OFFSET ; 00079 // Disable the appropriate interrupts. 00080 if (global_interrupt_enabled) Disable_global_interrupt(); 00081 aes->idr = (~(pAesIsrConfig->datrdy) & 1) << AVR32_AES_IDR_DATRDY_OFFSET | 00082 (~(pAesIsrConfig->urad) & 1) << AVR32_AES_IDR_URAD_OFFSET ; 00083 00084 if (global_interrupt_enabled) Enable_global_interrupt(); 00085 }
__inline__ void aes_load_newseed | ( | volatile avr32_aes_t * | aes | ) |
void aes_read_outputdata | ( | volatile avr32_aes_t * | aes, | |
unsigned int * | pOut | |||
) |
Read the 128/64/32/16/8bit input data.
*aes | Base address of the AES | |
*pOut | Pointer on 4/2/1 pre-allocated contiguous 32bit words. |
Definition at line 156 of file aes.c.
References AES_CFB_MODE.
Referenced by aes_int_handler().
00157 { 00158 unsigned long int const volatile *pTempo = &(aes->odata1r); 00159 unsigned char outlen = 4; 00160 00161 00162 if(AES_CFB_MODE == ((aes->mr & AVR32_AES_MR_OPMOD_MASK) >> AVR32_AES_MR_OPMOD_OFFSET)) 00163 { 00164 switch((aes->mr & AVR32_AES_MR_CFBS_MASK) >> AVR32_AES_MR_CFBS_OFFSET) 00165 { 00166 case 1: // 64bit CFB data size 00167 outlen = 2; 00168 break; 00169 case 2: // 32bit CFB data size 00170 case 3: // 16bit CFB data size 00171 case 4: // 8bit CFB data size 00172 outlen = 1; 00173 break; 00174 default: 00175 break; 00176 } 00177 } 00178 for(; outlen > 0; outlen--) 00179 *pOut++ = *pTempo++; 00180 }
void aes_set_initvector | ( | volatile avr32_aes_t * | aes, | |
const unsigned int * | pVector | |||
) |
Set the 128bit initialization vector (for the CBC, CFB, OFB & CTR cipher modes).
*aes | Base address of the AES | |
*pVector | Pointer on 4 contiguous 32bit words. |
Definition at line 119 of file aes.c.
Referenced by main().
00120 { 00121 unsigned long int volatile *pTempo = &(aes->iv1r); 00122 int i; 00123 00124 for(i=0; i<4; i++) 00125 *pTempo++ = *pVector++; 00126 }
void aes_set_key | ( | volatile avr32_aes_t * | aes, | |
const unsigned int * | pKey | |||
) |
Set the 128/192/256bit cryptographic key.
*aes | Base address of the AES | |
*pKey | Pointer on 4/6/8 contiguous 32bit words. |
Definition at line 94 of file aes.c.
Referenced by main().
00095 { 00096 unsigned long int volatile *pTempo = &(aes->keyw1r); 00097 unsigned char keylen = 0; 00098 00099 00100 switch((aes->mr & AVR32_AES_MR_KEYSIZE_MASK) >> AVR32_AES_MR_KEYSIZE_OFFSET) 00101 { 00102 case 0: // 128bit cryptographic key 00103 keylen = 4; 00104 break; 00105 case 1: // 192bit cryptographic key 00106 keylen = 6; 00107 break; 00108 case 2: // 256bit cryptographic key 00109 keylen = 8; 00110 break; 00111 default: 00112 break; 00113 } 00114 for( ; keylen > 0; keylen--) 00115 *pTempo++ = *pKey++; 00116 }
__inline__ void aes_start | ( | volatile avr32_aes_t * | aes | ) |
__inline__ void aes_swreset | ( | volatile avr32_aes_t * | aes | ) |
Perform a software reset of the AES.
*aes | Base address of the AES |
Definition at line 163 of file aes.h.
Referenced by aes_int_handler().
void aes_write_inputdata | ( | volatile avr32_aes_t * | aes, | |
const unsigned int * | pIn | |||
) |
Write the 128/64/32/16/8bit input data.
*aes | Base address of the AES | |
*pIn | Pointer on 4/2/1 contiguous 32bit words. |
Definition at line 129 of file aes.c.
References AES_CFB_MODE.
Referenced by main().
00130 { 00131 unsigned long int volatile *pTempo = &(aes->idata1r); 00132 unsigned char inlen = 4; 00133 00134 00135 if(AES_CFB_MODE == ((aes->mr & AVR32_AES_MR_OPMOD_MASK) >> AVR32_AES_MR_OPMOD_OFFSET)) 00136 { 00137 switch((aes->mr & AVR32_AES_MR_CFBS_MASK) >> AVR32_AES_MR_CFBS_OFFSET) 00138 { 00139 case 1: // 64bit CFB data size 00140 inlen = 2; 00141 break; 00142 case 2: // 32bit CFB data size 00143 case 3: // 16bit CFB data size 00144 case 4: // 8bit CFB data size 00145 inlen = 1; 00146 break; 00147 default: 00148 break; 00149 } 00150 } 00151 for(; inlen > 0; inlen--) 00152 *pTempo++ = *pIn++; 00153 }