Definition in file pdca_example.c.
#include <avr32/io.h>
#include "intc.h"
#include "pdca.h"
#include "usart.h"
#include "gpio.h"
#include "board.h"
#include "power_clocks_lib.h"
#include "ascii_anim1.h"
#include "ascii_anim2.h"
Go to the source code of this file.
Defines | |
#define | AVR32_PDCA_PID_USART_TX AVR32_PDCA_PID_USART3_TX |
#define | EXAMPLE_TARGET_DFLL_FREQ_HZ 96000000 |
#define | EXAMPLE_TARGET_MCUCLK_FREQ_HZ 12000000 |
#define | EXAMPLE_TARGET_PBACLK_FREQ_HZ 12000000 |
#define | EXAMPLE_USART (&AVR32_USART3) |
#define | EXAMPLE_USART_RX_FUNCTION AVR32_USART3_RXD_0_0_FUNCTION |
#define | EXAMPLE_USART_RX_PIN AVR32_USART3_RXD_0_0_PIN |
#define | EXAMPLE_USART_TX_FUNCTION AVR32_USART3_TXD_0_0_FUNCTION |
#define | EXAMPLE_USART_TX_PIN AVR32_USART3_TXD_0_0_PIN |
#define | PDCA_CHANNEL_USART_EXAMPLE 0 |
The channel instance for the USART example, here PDCA channel 0 (highest priority). | |
Functions | |
int | main (void) |
The given example is a transfer of an ASCII animation stored in internal flash to the USART_0 output (57600 bps/8 data bits/no parity bit/1 stop bit/no flow control). | |
static void | pdca_int_handler (void) |
The PDCA interrupt handler. | |
void | pdca_set_irq (void) |
Init interrupt controller and register pdca_int_handler interrupt. | |
int | usart_check_tx_status (volatile avr32_usart_t *usart) |
USART test if transmit buffer is ready before launching a PDCA transfer. | |
Variables | |
const char | ascii_anim1 [] |
String for ASCII animation: this is the first part of the ASCII animation. | |
const char | ascii_anim2 [] |
String for ASCII animation: this is the second and final part of the ASCII animation. | |
volatile int | bool_anim |
Counter for interrupt test. | |
Parameters to pcl_configure_clocks(). | |
static scif_gclk_opt_t | gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, OFF } |
static pcl_freq_param_t | pcl_dfll_freq_param |
#define AVR32_PDCA_PID_USART_TX AVR32_PDCA_PID_USART3_TX |
#define EXAMPLE_TARGET_DFLL_FREQ_HZ 96000000 |
Definition at line 163 of file pdca_example.c.
#define EXAMPLE_TARGET_MCUCLK_FREQ_HZ 12000000 |
Definition at line 164 of file pdca_example.c.
#define EXAMPLE_TARGET_PBACLK_FREQ_HZ 12000000 |
#define EXAMPLE_USART (&AVR32_USART3) |
#define EXAMPLE_USART_RX_FUNCTION AVR32_USART3_RXD_0_0_FUNCTION |
#define EXAMPLE_USART_RX_PIN AVR32_USART3_RXD_0_0_PIN |
#define EXAMPLE_USART_TX_FUNCTION AVR32_USART3_TXD_0_0_FUNCTION |
#define EXAMPLE_USART_TX_PIN AVR32_USART3_TXD_0_0_PIN |
#define PDCA_CHANNEL_USART_EXAMPLE 0 |
The channel instance for the USART example, here PDCA channel 0 (highest priority).
Definition at line 193 of file pdca_example.c.
Referenced by main(), and pdca_int_handler().
int main | ( | void | ) |
The given example is a transfer of an ASCII animation stored in internal flash to the USART_0 output (57600 bps/8 data bits/no parity bit/1 stop bit/no flow control).
This example uses the USART, GPIO, INTC and PDCA modules.
Definition at line 284 of file pdca_example.c.
References ascii_anim1, AVR32_PDCA_PID_USART_TX, bool_anim, EXAMPLE_TARGET_PBACLK_FREQ_HZ, EXAMPLE_USART, EXAMPLE_USART_RX_FUNCTION, EXAMPLE_USART_RX_PIN, EXAMPLE_USART_TX_FUNCTION, EXAMPLE_USART_TX_PIN, pcl_dfll_freq_param, PDCA_CHANNEL_USART_EXAMPLE, pdca_enable(), pdca_enable_interrupt_reload_counter_zero(), pdca_init_channel(), pdca_set_irq(), and PDCA_TRANSFER_SIZE_BYTE.
00285 { 00286 #if BOARD == UC3L_EK 00287 // Note: on the AT32UC3L-EK board, there is no crystal/external clock connected 00288 // to the OSC0 pinout XIN0/XOUT0. We shall then program the DFLL and switch the 00289 // main clock source to the DFLL. 00290 pcl_configure_clocks(&pcl_dfll_freq_param); 00291 // Note: since it is dynamically computing the appropriate field values of the 00292 // configuration registers from the parameters structure, this function is not 00293 // optimal in terms of code size. For a code size optimal solution, it is better 00294 // to create a new function from pcl_configure_clocks_dfll0() and modify it 00295 // to use preprocessor computation from pre-defined target frequencies. 00296 #else 00297 // Configure Osc0 in crystal mode (i.e. use of an external crystal source, with 00298 // frequency FOSC0) with an appropriate startup time then switch the main clock 00299 // source to Osc0. 00300 pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP); 00301 #endif 00302 00303 // As this program and the ASCII animation are loaded in internal Flash, 00304 // both the CPU instruction master and the PDCA master interface will access the flash at the same time. 00305 // 00306 // In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix 00307 // provides specific logic in order to re-arbitrate before the end of the INCR transfer. 00308 // 00309 // HSB Bus Matrix: By default the HSB bus matrix mode is in Undefined length burst type (INCR). 00310 // Here we have to put in single access (the undefined length burst is treated as a succession of single 00311 // accesses, allowing re-arbitration at each beat of the INCR burst. 00312 // Refer to the HSB bus matrix section of the datasheet for more details. 00313 // 00314 // HSB Bus matrix register MCFG1 is associated with the CPU instruction master interface. 00315 AVR32_HMATRIX.mcfg[AVR32_HMATRIX_MASTER_CPU_INSN] = 0x1; 00316 00317 // Init counter for PDCA interrupt. 00318 bool_anim=1; 00319 00320 static const gpio_map_t USART_GPIO_MAP = 00321 { 00322 {EXAMPLE_USART_RX_PIN, EXAMPLE_USART_RX_FUNCTION}, 00323 {EXAMPLE_USART_TX_PIN, EXAMPLE_USART_TX_FUNCTION} 00324 }; 00325 00326 // USART options. 00327 static const usart_options_t USART_OPTIONS = 00328 { 00329 .baudrate = 57600, 00330 .charlength = 8, 00331 .paritytype = USART_NO_PARITY, 00332 .stopbits = USART_1_STOPBIT, 00333 .channelmode = USART_NORMAL_CHMODE, 00334 }; 00335 00336 // Assign GPIO pins to USART_0. 00337 gpio_enable_module(USART_GPIO_MAP, 00338 sizeof(USART_GPIO_MAP) / sizeof(USART_GPIO_MAP[0])); 00339 00340 // Initialize the USART in RS232 mode. 00341 usart_init_rs232(EXAMPLE_USART, &USART_OPTIONS, EXAMPLE_TARGET_PBACLK_FREQ_HZ); 00342 00343 usart_write_line(EXAMPLE_USART, "PDCA Example.\n"); 00344 00345 // PDCA channel options 00346 static const pdca_channel_options_t PDCA_OPTIONS = 00347 { 00348 .addr = (void *)ascii_anim1, // memory address 00349 .pid = AVR32_PDCA_PID_USART_TX, // select peripheral - data are transmit on USART TX line. 00350 .size = sizeof(ascii_anim1), // transfer counter 00351 .r_addr = NULL, // next memory address 00352 .r_size = 0, // next transfer counter 00353 .transfer_size = PDCA_TRANSFER_SIZE_BYTE // select size of the transfer 00354 }; 00355 00356 // Init PDCA channel with the pdca_options. 00357 pdca_init_channel(PDCA_CHANNEL_USART_EXAMPLE, &PDCA_OPTIONS); // init PDCA channel with options. 00358 00359 // Register PDCA IRQ interrupt. 00360 pdca_set_irq(); 00361 00362 // Enable pdca interrupt each time the reload counter reaches zero, i.e. each time 00363 // half of the ASCII animation (either anim1 or anim2) is transferred. 00364 pdca_enable_interrupt_reload_counter_zero(PDCA_CHANNEL_USART_EXAMPLE); 00365 00366 // Enable now the transfer. 00367 pdca_enable(PDCA_CHANNEL_USART_EXAMPLE); 00368 00369 // While the PDCA is active transfering data from memory to USART, we may switch 00370 // the device into IDLE sleep mode. 00371 // -- 00372 // Modules communicating with external circuits should normally be disabled 00373 // before entering a sleep mode that will stop the module operation: this is not 00374 // the case for the IDLE sleep mode. 00375 // -- 00376 00377 while(1) 00378 { 00379 // If there is a chance that any PB write operations are incomplete, the CPU 00380 // should perform a read operation from any register on the PB bus before 00381 // executing the sleep instruction. 00382 AVR32_INTC.ipr[0]; // Dummy read 00383 00384 // Go to IDLE sleep mode. 00385 SLEEP(AVR32_PM_SMODE_IDLE); 00386 // When the device wakes up due to an interrupt, once the interrupt is serviced, 00387 // go back into IDLE sleep mode. 00388 } 00389 }
static void pdca_int_handler | ( | void | ) | [static] |
The PDCA interrupt handler.
The handler reload the PDCA settings with the correct ASCII animation address and size using the reload register. The interrupt will happen each time half of the animation is played. Let's use interrupt level 0 in the example.
Definition at line 228 of file pdca_example.c.
References ascii_anim1, ascii_anim2, bool_anim, PDCA_CHANNEL_USART_EXAMPLE, and pdca_reload_channel().
Referenced by pdca_set_irq().
00229 { 00230 00231 if (bool_anim == 1) 00232 { 00233 // Set PDCA channel reload values with address where data to load are stored, and size of the data block to load. 00234 pdca_reload_channel(PDCA_CHANNEL_USART_EXAMPLE, (void *)ascii_anim2, sizeof( ascii_anim2 )); 00235 bool_anim = 2; 00236 } 00237 else if (bool_anim == 2) 00238 { 00239 pdca_reload_channel(PDCA_CHANNEL_USART_EXAMPLE, (void *)ascii_anim1, sizeof( ascii_anim1 )); 00240 bool_anim = 1; 00241 } 00242 }
void pdca_set_irq | ( | void | ) |
Init interrupt controller and register pdca_int_handler interrupt.
Definition at line 247 of file pdca_example.c.
References pdca_int_handler().
Referenced by main().
00248 { 00249 #if __GNUC__ 00250 // Disable all interrupt/exception. 00251 Disable_global_interrupt(); 00252 00253 INTC_init_interrupts(); 00254 00255 // Register the compare interrupt handler to the interrupt controller 00256 // and enable the compare interrupt. 00257 // (__int_handler) &pdca_int_handler The handler function to register. 00258 // AVR32_PDCA_IRQ_0 The interrupt line to register to. 00259 // AVR32_INTC_INT0 The priority level to set for this interrupt line. 00260 // INTC_register_interrupt(__int_handler handler, int line, int priority); 00261 INTC_register_interrupt( (__int_handler) &pdca_int_handler, AVR32_PDCA_IRQ_0, AVR32_INTC_INT0); 00262 #endif 00263 00264 // Enable all interrupt/exception. 00265 Enable_global_interrupt(); 00266 }
int usart_check_tx_status | ( | volatile avr32_usart_t * | usart | ) |
USART test if transmit buffer is ready before launching a PDCA transfer.
usart | Pointer to a avr32_usart_t |
Definition at line 273 of file pdca_example.c.
00274 { 00275 if (usart->csr & (1<<AVR32_USART_CSR_TXEMPTY_OFFSET)) return USART_SUCCESS; 00276 else return USART_TX_BUSY; 00277 }
const char ascii_anim1[] |
Initial value:
# 200 "/cygdrive/d/TEMP/1.7.0-AT32UC3/DRIVERS/PDCA/EXAMPLE/pdca_example.c" 2
Definition at line 199 of file pdca_example.c.
Referenced by main(), and pdca_int_handler().
const char ascii_anim2[] |
Initial value:
# 205 "/cygdrive/d/TEMP/1.7.0-AT32UC3/DRIVERS/PDCA/EXAMPLE/pdca_example.c" 2
Definition at line 204 of file pdca_example.c.
Referenced by pdca_int_handler().
volatile int bool_anim |
Counter for interrupt test.
Definition at line 196 of file pdca_example.c.
Referenced by main(), and pdca_int_handler().
scif_gclk_opt_t gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, OFF } [static] |
Definition at line 169 of file pdca_example.c.
pcl_freq_param_t pcl_dfll_freq_param [static] |
Initial value:
{ .main_clk_src = PCL_MC_DFLL0, .cpu_f = EXAMPLE_TARGET_MCUCLK_FREQ_HZ, .pba_f = EXAMPLE_TARGET_PBACLK_FREQ_HZ, .pbb_f = EXAMPLE_TARGET_PBACLK_FREQ_HZ, .dfll_f = EXAMPLE_TARGET_DFLL_FREQ_HZ, .pextra_params = &gc_dfllif_ref_opt }
Definition at line 170 of file pdca_example.c.
Referenced by main().