00001
00104 #include <avr32/io.h>
00105 #if __GNUC__
00106 # include "intc.h"
00107 #endif
00108 #include "compiler.h"
00109 #include "board.h"
00110 #include "power_clocks_lib.h"
00111 #include "gpio.h"
00112 #include "tc.h"
00113
00114
00117
00118 # define EXAMPLE_TC (&AVR32_TC0)
00119 # define EXAMPLE_TC_CHANNEL 1
00120 # define EXAMPLE_TC_IRQ_GROUP AVR32_TC0_IRQ_GROUP
00121 # define EXAMPLE_TC_IRQ AVR32_TC0_IRQ1 // Because we use channel 1.
00122 # define EXAMPLE_EVENT_PIN AVR32_PIN_PA11
00123
00124
00125
00126
00127 #if BOARD == UC3L_EK
00128 # define EXAMPLE_TARGET_DFLL_FREQ_HZ 96000000 // DFLL target frequency, in Hz
00129 # define EXAMPLE_TARGET_MCUCLK_FREQ_HZ 12000000 // MCU clock target frequency, in Hz
00130 # define EXAMPLE_TARGET_PBACLK_FREQ_HZ 12000000 // PBA clock target frequency, in Hz
00131
00133
00134 static scif_gclk_opt_t gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, OFF };
00135 static pcl_freq_param_t pcl_dfll_freq_param =
00136 {
00137 .main_clk_src = PCL_MC_DFLL0,
00138 .cpu_f = EXAMPLE_TARGET_MCUCLK_FREQ_HZ,
00139 .pba_f = EXAMPLE_TARGET_PBACLK_FREQ_HZ,
00140 .pbb_f = EXAMPLE_TARGET_PBACLK_FREQ_HZ,
00141 .dfll_f = EXAMPLE_TARGET_DFLL_FREQ_HZ,
00142 .pextra_params = &gc_dfllif_ref_opt
00143 };
00145 #endif
00146
00147 #if !defined(EXAMPLE_TC) || \
00148 !defined(EXAMPLE_TC_CHANNEL) || \
00149 !defined(EXAMPLE_TC_IRQ_GROUP) || \
00150 !defined(EXAMPLE_TC_IRQ) || \
00151 !defined(EXAMPLE_EVENT_PIN)
00152 # error The preprocessor configuration to use in this example is missing.
00153 #endif
00155
00156
00157 static volatile int chan_status = 0;
00158
00161 #if defined(__GNUC__)
00162 __attribute__((__interrupt__))
00163 #elif defined(__ICCAVR32__)
00164 #pragma handler = EXAMPLE_TC_IRQ_GROUP, 3
00165 __interrupt
00166 #endif
00167 static void tc_irq_handler(void)
00168 {
00169
00170 chan_status = tc_read_sr(EXAMPLE_TC, EXAMPLE_TC_CHANNEL);
00171
00172
00173 gpio_tgl_gpio_pin(LED0_GPIO);
00174 }
00175
00176
00179 static void init_tc_input(volatile avr32_tc_t *tc, unsigned int channel)
00180 {
00181
00182 tc_capture_opt_t capture_opt =
00183 {
00184 .channel = channel,
00185
00186 .ldrb = TC_SEL_NO_EDGE,
00187 .ldra = TC_SEL_RISING_EDGE,
00188
00189 .cpctrg = TC_NO_TRIGGER_COMPARE_RC,
00190 .abetrg = TC_EXT_TRIG_SEL_TIOA,
00191 .etrgedg = TC_SEL_RISING_EDGE,
00192
00193 .ldbdis = FALSE,
00194 .ldbstop = FALSE,
00195
00196 .burst = TC_BURST_NOT_GATED,
00197 .clki = TC_CLOCK_RISING_EDGE,
00198 .tcclks = TC_CLOCK_SOURCE_TC4
00199 };
00200
00201
00202 tc_init_capture(tc, &capture_opt);
00203 }
00204
00205
00209 int main(void)
00210 {
00211 static const tc_interrupt_t TC_INTERRUPT =
00212 {
00213 .etrgs = 0,
00214 .ldrbs = 0,
00215 .ldras = 1,
00216 .cpcs = 0,
00217 .cpbs = 0,
00218 .cpas = 0,
00219 .lovrs = 0,
00220 .covfs = 0
00221 };
00222
00223
00224 volatile avr32_tc_t *tc = EXAMPLE_TC;
00225
00226
00227 gpio_set_gpio_pin(LED0_GPIO);
00228
00229
00230 #if BOARD == UC3L_EK
00231
00232
00233
00234 pcl_configure_clocks(&pcl_dfll_freq_param);
00235
00236
00237
00238
00239
00240 #else
00241
00242
00243
00244 pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP);
00245 #endif
00246
00247
00248
00249
00250
00251
00252
00253
00254
00255 gpio_configure_pin_periph_event_mode(EXAMPLE_EVENT_PIN, GPIO_FALLING_EDGE, TRUE);
00256
00257
00258 gpio_enable_pin_pull_up(EXAMPLE_EVENT_PIN);
00259
00260 gpio_enable_pin_periph_event(EXAMPLE_EVENT_PIN);
00261
00262 Disable_global_interrupt();
00263
00264
00265 #ifdef __GNUC__
00266
00267 INTC_init_interrupts();
00268
00269
00270 INTC_register_interrupt(&tc_irq_handler, EXAMPLE_TC_IRQ, AVR32_INTC_INT3);
00271 #endif
00272
00273 Enable_global_interrupt();
00274
00275
00276 init_tc_input(tc, EXAMPLE_TC_CHANNEL);
00277
00278
00279 tc_configure_interrupts(tc, EXAMPLE_TC_CHANNEL, &TC_INTERRUPT);
00280
00281
00282 tc_start(tc, EXAMPLE_TC_CHANNEL);
00283
00284 while(1);
00285 }