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00046 #ifndef _SCIF_UC3L_H_
00047 #define _SCIF_UC3L_H_
00048
00049 #ifdef __cplusplus
00050 extern "C" {
00051 #endif
00052
00053 #include "compiler.h"
00054
00055
00056 #if defined(AVR32_SCIF_100_H_INCLUDED) || defined(AVR32_SCIF_102_H_INCLUDED)
00057
00058 #define AVR32_SCIF_GC_NO_DIV_CLOCK AVR32_GC_NO_DIV_CLOCK
00059 #endif
00060
00061 #define AVR32_SCIF_OSCCTRL0_OSCEN_ENABLE 0x00000001
00062 #define AVR32_SCIF_OSCCTRL0_OSCEN_DISABLE 0x00000000
00063 #define AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE 0x00000001
00064 #define AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE 0x00000000
00065
00066
00068
00070 #define SCIF_EXT_CRYSTAL_MIN_FREQ_HZ 4000000
00072 #define SCIF_EXT_CRYSTAL_MAX_FREQ_HZ 20000000
00073
00075 typedef enum
00076 {
00077 SCIF_GCCTRL_SLOWCLOCK = AVR32_SCIF_GC_USES_CLK_SLOW,
00078 SCIF_GCCTRL_OSC32K = AVR32_SCIF_GC_USES_CLK_32,
00079 SCIF_GCCTRL_DFLL0 = AVR32_SCIF_GC_USES_DFLL0,
00080 SCIF_GCCTRL_OSC0 = AVR32_SCIF_GC_USES_OSC0,
00081 SCIF_GCCTRL_RC120M = AVR32_SCIF_GC_USES_RC120M,
00082 SCIF_GCCTRL_CPUCLOCK = AVR32_SCIF_GC_USES_CLK_CPU,
00083 SCIF_GCCTRL_HSBCLOCK = AVR32_SCIF_GC_USES_CLK_HSB,
00084 SCIF_GCCTRL_PBACLOCK = AVR32_SCIF_GC_USES_CLK_PBA,
00085 SCIF_GCCTRL_PBBCLOCK = AVR32_SCIF_GC_USES_CLK_PBB,
00086 SCIF_GCCTRL_RC32K = AVR32_SCIF_GC_USES_RC32K,
00087 SCIF_GCCTRL_CRIPOSC = AVR32_SCIF_GC_USES_CRIPOSC,
00088 SCIF_GCCTRL_CLK1K = AVR32_SCIF_GC_USES_CLK_1K,
00089 SCIF_GCCTRL_OSCSEL_INVALID
00090 } scif_gcctrl_oscsel_t;
00091
00093 #define SCIF_DFLL_MINFREQ_KHZ 20000
00094 #define SCIF_DFLL_MINFREQ_HZ 20000000L
00095
00097 #define SCIF_DFLL_MAXFREQ_KHZ 150000
00098 #define SCIF_DFLL_MAXFREQ_HZ 150000000L
00099
00101 #define SCIF_SLOWCLOCK_FREQ_HZ AVR32_SCIF_RCOSC_FREQUENCY
00102 #define SCIF_SLOWCLOCK_FREQ_KHZ (SCIF_SLOWCLOCK_FREQ_HZ/100)
00103
00105 #define SCIF_RC32K_FREQ_HZ 32768
00106 #define SCIF_RC32K_FREQ_KHZ (SCIF_RC32K_FREQ_HZ/100)
00107
00109 #define SCIF_RC120M_FREQ_HZ 120000000L
00110 #define SCIF_RC120M_FREQ_KHZ 120000
00111
00113 #define SCIF_OSC32_FREQ_HZ 32768
00114
00116 #define SCIF_POLL_TIMEOUT 100000
00117
00119 #define SCIF_NOT_SUPPORTED (-10000)
00120
00121
00123 typedef enum
00124 {
00125 SCIF_OSC0 = 0,
00126 SCIF_OSC1 = 1
00127 } scif_osc_t;
00128
00130 typedef enum
00131 {
00132 SCIF_OSC_MODE_EXT_CLK = 0,
00133 SCIF_OSC_MODE_2PIN_CRYSTAL = 1,
00134 SCIF_OSC_MODE_NOT_SUPPORTED_1 = 2,
00135 SCIF_OSC_MODE_NOT_SUPPORTED_2 = 3,
00136 SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR = 4,
00137 SCIF_OSC_MODE_NOT_SUPPORTED_3 = 5,
00138 SCIF_OSC_MODE_NOT_SUPPORTED_4 = 6,
00139 SCIF_OSC_MODE_NOT_SUPPORTED_5 = 7
00140 } scif_osc_mode_t;
00141
00143 typedef struct
00144 {
00146 unsigned long freq_hz;
00148 scif_osc_mode_t mode;
00150 unsigned char startup;
00152 unsigned char gain;
00153 } scif_osc_opt_t;
00154
00156 typedef struct
00157 {
00159 scif_osc_mode_t mode;
00161 unsigned char startup;
00163 bool pinsel;
00165 bool en1k;
00167 bool en32k;
00168 } scif_osc32_opt_t;
00169
00170
00172 typedef struct
00173 {
00175 scif_gcctrl_oscsel_t clock_source;
00177 unsigned int divider;
00179 unsigned int diven;
00181
00182 unsigned long extosc_f;
00183 } scif_gclk_opt_t;
00184
00185
00187 typedef struct
00188 {
00189 unsigned int fine;
00190 unsigned int coarse;
00191 } scif_dfll_openloop_conf_t;
00192
00194 typedef struct
00195 {
00197 unsigned int coarse;
00199 unsigned int fmul;
00200 #if (defined(__GNUC__) \
00201 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00202 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00203 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00204
00206 unsigned int finemaxstep;
00208 unsigned int coarsemaxstep;
00209 #else
00210
00212 unsigned int maxstep;
00213 #endif
00214 } scif_dfll_closedloop_conf_t;
00215
00217 typedef struct
00218 {
00220 unsigned int use_random;
00222 unsigned int amplitude;
00224 unsigned int step_size;
00225 } scif_dfll_ssg_conf_t;
00226
00227
00229 #define SCIF_UNLOCK(reg) (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg))
00230
00233
00234
00239 #ifdef __GNUC__
00240 __attribute__((__always_inline__))
00241 #endif
00242 extern __inline__ void scif_enable_interrupts(unsigned long mask)
00243 {
00244 AVR32_SCIF.ier = mask;
00245 }
00246
00251 #ifdef __GNUC__
00252 __attribute__((__always_inline__))
00253 #endif
00254 extern __inline__ void scif_disable_interrupts(unsigned long mask)
00255 {
00256 AVR32_SCIF.idr = mask;
00257 }
00258
00263 #ifdef __GNUC__
00264 __attribute__((__always_inline__))
00265 #endif
00266 extern __inline__ unsigned long scif_get_enabled_interrupts(void)
00267 {
00268 return(AVR32_SCIF.imr);
00269 }
00270
00275 #ifdef __GNUC__
00276 __attribute__((__always_inline__))
00277 #endif
00278 extern __inline__ unsigned long scif_get_interrupts_status(void)
00279 {
00280 return(AVR32_SCIF.isr);
00281 }
00282
00287 #ifdef __GNUC__
00288 __attribute__((__always_inline__))
00289 #endif
00290 extern __inline__ void scif_clear_interrupts_status(unsigned long mask)
00291 {
00292 AVR32_SCIF.icr = mask;
00293 }
00294
00296
00297
00300
00301
00306 #ifdef __GNUC__
00307 __attribute__((__always_inline__))
00308 #endif
00309 extern __inline__ unsigned long scif_get_pclk_status(void)
00310 {
00311 return(AVR32_SCIF.pclksr);
00312 }
00313
00315
00316
00319
00320
00334 extern long int scif_start_osc(scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready);
00335
00344 extern bool scif_is_osc_ready(scif_osc_t osc);
00345
00354 extern long int scif_stop_osc(scif_osc_t osc);
00355
00365 extern long int scif_configure_osc_crystalmode(scif_osc_t osc, unsigned int fcrystal);
00366
00377 extern long int scif_enable_osc(scif_osc_t osc, unsigned int startup, bool wait_for_ready);
00378
00380
00381
00384
00385
00398 extern long int scif_start_osc32(const scif_osc32_opt_t *opt, bool wait_for_ready);
00399
00406 #ifdef __GNUC__
00407 __attribute__((__always_inline__))
00408 #endif
00409 extern __inline__ bool scif_is_osc32_ready()
00410 {
00411 return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC32RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC32RDY_OFFSET);
00412 }
00413
00417 #ifdef __GNUC__
00418 __attribute__((__always_inline__))
00419 #endif
00420 extern __inline__ void scif_osc32_1kout_ena()
00421 {
00422 AVR32_SCIF.oscctrl32 |= AVR32_SCIF_EN1K_MASK;
00423 }
00424
00428 #ifdef __GNUC__
00429 __attribute__((__always_inline__))
00430 #endif
00431 extern __inline__ void scif_osc32_1kout_dis()
00432 {
00433 AVR32_SCIF.oscctrl32 &= ~AVR32_SCIF_EN1K_MASK;
00434 }
00435
00439 #ifdef __GNUC__
00440 __attribute__((__always_inline__))
00441 #endif
00442 extern __inline__ void scif_osc32_32kout_ena()
00443 {
00444 AVR32_SCIF.oscctrl32 |= AVR32_SCIF_EN32K_MASK;
00445 }
00446
00450 #ifdef __GNUC__
00451 __attribute__((__always_inline__))
00452 #endif
00453 extern __inline__ void scif_osc32_32kout_dis()
00454 {
00455 AVR32_SCIF.oscctrl32 &= ~AVR32_SCIF_EN32K_MASK;
00456 }
00457
00464 extern long int scif_stop_osc32();
00465
00467
00468
00471
00472
00481 extern long int scif_dfll0_openloop_start(const scif_dfll_openloop_conf_t *pdfllconfig);
00482
00491 extern long int scif_dfll0_openloop_start_auto(unsigned long TargetFreqkHz);
00492
00501 extern long int scif_dfll0_openloop_updatefreq(const scif_dfll_openloop_conf_t *pdfllconfig);
00502
00511 extern long int scif_dfll0_openloop_updatefreq_auto(unsigned long TargetFreq);
00512
00519 extern long int scif_dfll0_openloop_stop(void);
00520
00532 #define scif_dfll0_ssg_gc_enable(pgc_conf) scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_SSG, pgc_conf)
00533
00544 extern long int scif_dfll0_ssg_enable(scif_dfll_ssg_conf_t *pssg_conf);
00545
00554 #define scif_dfll0_closedloop_mainref_gc_enable(pgc_conf) scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_REF, pgc_conf)
00555
00566 extern long int scif_dfll0_closedloop_start(const scif_dfll_closedloop_conf_t *pdfllconfig);
00567
00585 extern long int scif_dfll0_closedloop_configure_and_start( const scif_gclk_opt_t *gc_dfllif_ref_opt,
00586 unsigned long long target_freq_hz,
00587 bool enable_ssg);
00588
00597 #define scif_dfll0_closedloop_dither_gc_enable(pgc_conf) scif_dfll0_ssg_gc_enable(pgc_conf)
00598
00599
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00608
00610
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00614
00615
00618 extern void scif_start_rc120M(void);
00619
00622 extern void scif_stop_rc120M(void);
00623
00625
00626
00629
00630
00633 extern void scif_start_rc32k(void);
00634
00637 extern void scif_stop_rc32k(void);
00638
00642 extern void scif_disable_rc32out(void);
00643
00645
00646
00649
00650
00660 extern long int scif_start_gclk(unsigned int gclk, const scif_gclk_opt_t *opt);
00661
00673 extern long int scif_stop_gclk(unsigned int gclk);
00674
00689 extern long int scif_gc_setup(unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor);
00690
00699 extern long int scif_gc_enable(unsigned int gclk);
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00708
00710
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00715
00724 long int scif_pclksr_statushigh_wait(unsigned long statusMask);
00725
00727
00728 #ifdef __cplusplus
00729 }
00730 #endif
00731
00732 #endif // _SCIF_UC3L_H_