This file defines a useful set of functions for ADC on AVR UC3 devices.
Definition in file adcifa.h.
#include <avr32/io.h>
#include "compiler.h"
Go to the source code of this file.
Data Structures | |
struct | adcifa_opt_t |
Parameters for the ADCIFA. More... | |
struct | adcifa_sequencer_conversion_opt_t |
Parameters for an conversion in the Sequencer. More... | |
struct | adcifa_sequencer_opt_t |
Parameters for the configuration of the Sequencer. More... | |
Defines | |
#define | ADCIFA_ADCREF 0x10 |
#define | ADCIFA_ADCREF0 0x2 |
#define | ADCIFA_ADCREF1 0x3 |
#define | ADCIFA_CONFIGURATION_ACCEPTED 0x1 |
This constant is used as return value for "adcifa_configure" and "adcifa_configure_sequencer" functions. | |
#define | ADCIFA_CONFIGURATION_REFUSED 0x0 |
Status. | |
#define | ADCIFA_configure_muxsel0n(m7, m6, m5, m4, m3, m2, m1, m0) |
#define | ADCIFA_configure_muxsel0p(m7, m6, m5, m4, m3, m2, m1, m0) |
#define | ADCIFA_configure_muxsel1n(m7, m6, m5, m4, m3, m2, m1, m0) |
#define | ADCIFA_configure_muxsel1p(m7, m6, m5, m4, m3, m2, m1, m0) |
#define | ADCIFA_configure_sequencer_0(cnvnb, sres, trgsel, socb, csws, hwla, sa) |
--------------------------- Sequencer 0 Functions Management ------------------------- | |
#define | ADCIFA_configure_sequencer_1(cnvnb, sres, trgsel, socb, csws, hwla, sa) |
--------------------------- Sequencer 1 Functions Management ------------------------- | |
#define | ADCIFA_configure_sh0gain(g7, g6, g5, g4, g3, g2, g1, g0) { AVR32_ADCIFA.shg0 = ((g7) << AVR32_ADCIFA_GCNV7_OFFSET) | ((g6) << AVR32_ADCIFA_GCNV6_OFFSET) | ((g5) << AVR32_ADCIFA_GCNV5_OFFSET) |((g4) << AVR32_ADCIFA_GCNV4_OFFSET) |((g3) << AVR32_ADCIFA_GCNV3_OFFSET) |((g2) << AVR32_ADCIFA_GCNV2_OFFSET) |((g1) << AVR32_ADCIFA_GCNV1_OFFSET) |((g0) << AVR32_ADCIFA_GCNV0_OFFSET); } |
#define | ADCIFA_configure_sh1gain(g7, g6, g5, g4, g3, g2, g1, g0) { AVR32_ADCIFA.shg1 = ((g7) << AVR32_ADCIFA_GCNV7_OFFSET) | ((g6) << AVR32_ADCIFA_GCNV6_OFFSET) | ((g5) << AVR32_ADCIFA_GCNV5_OFFSET) |((g4) << AVR32_ADCIFA_GCNV4_OFFSET) |((g3) << AVR32_ADCIFA_GCNV3_OFFSET) |((g2) << AVR32_ADCIFA_GCNV2_OFFSET) |((g1) << AVR32_ADCIFA_GCNV1_OFFSET) |((g0) << AVR32_ADCIFA_GCNV0_OFFSET); } |
#define | ADCIFA_CSWS_NOWSTATE 0x0 |
#define | ADCIFA_CSWS_WSTATE 0x1 |
#define | ADCIFA_disable() { AVR32_ADCIFA.cfg &= ~(1 << AVR32_ADCIFA_CFG_ADCEN); } |
Enable the ADCIFA. | |
#define | ADCIFA_enable() { AVR32_ADCIFA.cfg |= (1 << AVR32_ADCIFA_CFG_ADCEN); } |
Enable the ADCIFA. | |
#define | ADCIFA_HWLA_LEFTADJ 0x1 |
#define | ADCIFA_HWLA_NOADJ 0x0 |
#define | ADCIFA_is_eoc_sequencer_0() (((AVR32_ADCIFA.sr)&(1<<AVR32_ADCIFA_SR_SEOC0))==(1<<AVR32_ADCIFA_SR_SEOC0)) |
Sequencer 0 : Check end of Conversion. | |
#define | ADCIFA_is_eoc_sequencer_1() (((AVR32_ADCIFA.sr)&(1<<AVR32_ADCIFA_SR_SEOC1))==(1<<AVR32_ADCIFA_SR_SEOC1)) |
Sequencer 1 : Check end of Conversion. | |
#define | ADCIFA_is_eos_sequencer_0() (((AVR32_ADCIFA.sr)&(1<<AVR32_ADCIFA_SR_SEOS0))==(1<<AVR32_ADCIFA_SR_SEOS0)) |
Sequencer 0 : Check end of Sequence. | |
#define | ADCIFA_is_eos_sequencer_1() (((AVR32_ADCIFA.sr)&(1<<AVR32_ADCIFA_SR_SEOS1))==(1<<AVR32_ADCIFA_SR_SEOS1)) |
Sequencer 1 : Check end of Sequence. | |
#define | ADCIFA_is_startup_time() (((AVR32_ADCIFA.sr) & (1 << AVR32_ADCIFA_SR_SUTD)) == (1 << AVR32_ADCIFA_SR_SUTD)) |
Check Startup Time flag. | |
#define | ADCIFA_NONE 0xFF |
Parameter. | |
#define | ADCIFA_read_resx_sequencer_0(ind) ((int)AVR32_ADCIFA.resx[(ind)]) |
#define | ADCIFA_read_resx_sequencer_1(ind) ((int)AVR32_ADCIFA.resx[(ind)+8]) |
#define | ADCIFA_REF065VCC 0x1 |
#define | ADCIFA_REF1V 0x0 |
#define | ADCIFA_SA_EOS_SOFTACK 0x0 |
#define | ADCIFA_SA_NO_EOS_SOFTACK 0x1 |
#define | ADCIFA_SEQ0 0x0 |
#define | ADCIFA_SEQ0_SEQ1 0x3 |
#define | ADCIFA_SEQ1 0x1 |
#define | ADCIFA_set_gain_calibration(gcal) { AVR32_ADCIFA.adccal |=((gcal)<<AVR32_ADCIFA_ADCCAL_GCAL)&AVR32_ADCIFA_ADCCAL_GCAL_MASK; } |
Set Gain Calibration. | |
#define | ADCIFA_set_offset_calibration(ocal) { AVR32_ADCIFA.adccal |=((ocal)<<AVR32_ADCIFA_ADCCAL_OCAL)&AVR32_ADCIFA_ADCCAL_OCAL_MASK; } |
--------------------------- ADCIFA Core Management --------------------------------- | |
#define | ADCIFA_set_sh_gain_calibration(scal) { AVR32_ADCIFA.shcal =((scal)&(AVR32_ADCIFA_SHCAL_GAIN1_MASK | AVR32_ADCIFA_SHCAL_GAIN0_MASK)); } |
Set Sample & Hold Gain Calibration. | |
#define | ADCIFA_SHG_1 0x0 |
#define | ADCIFA_SHG_16 0x4 |
#define | ADCIFA_SHG_2 0x1 |
#define | ADCIFA_SHG_32 0x5 |
#define | ADCIFA_SHG_4 0x2 |
#define | ADCIFA_SHG_64 0x6 |
#define | ADCIFA_SHG_8 0x3 |
#define | ADCIFA_SOCB_ALLSEQ 0x0 |
#define | ADCIFA_SOCB_SINGLECONV 0x1 |
#define | ADCIFA_softsoc_sequencer(seq) { AVR32_ADCIFA.cr = (seq); } |
#define | ADCIFA_softsoc_sequencer_0() { AVR32_ADCIFA.cr = AVR32_ADCIFA_CR_SOC0_MASK; } |
Sequencer 0 : Software Start of Conversion. | |
#define | ADCIFA_softsoc_sequencer_1() { AVR32_ADCIFA.cr = AVR32_ADCIFA_CR_SOC1_MASK; } |
Sequencer 1 : Software Start of Conversion. | |
#define | ADCIFA_SRES_10B 0x1 |
#define | ADCIFA_SRES_12B 0x0 |
#define | ADCIFA_SRES_8B 0x2 |
#define | ADCIFA_START_UP_TIME 1000 |
#define | ADCIFA_STATUS_COMPLETED 0x2 |
This constant is used as return value for "adcifa_get_values_seq" function. | |
#define | ADCIFA_STATUS_NOT_COMPLETED 0x3 |
This constant is used as return value for "adcifa_get_values_seq" function. | |
#define | ADCIFA_TRGSEL_EVT 0x2 |
#define | ADCIFA_TRGSEL_ITIMER 0x1 |
#define | ADCIFA_TRGSEL_SOFT 0x0 |
#define | AVR32_ADCIFA_INN_ADCIN10 2 |
#define | AVR32_ADCIFA_INN_ADCIN11 3 |
#define | AVR32_ADCIFA_INN_ADCIN12 4 |
#define | AVR32_ADCIFA_INN_ADCIN13 5 |
#define | AVR32_ADCIFA_INN_ADCIN14 6 |
#define | AVR32_ADCIFA_INN_ADCIN15 7 |
#define | AVR32_ADCIFA_INN_ADCIN8 0 |
#define | AVR32_ADCIFA_INN_ADCIN9 1 |
#define | AVR32_ADCIFA_INN_DAC1_INT 8 |
#define | AVR32_ADCIFA_INN_GNDANA 9 |
#define | AVR32_ADCIFA_INP_ADCIN0 0 |
#define | AVR32_ADCIFA_INP_ADCIN1 1 |
#define | AVR32_ADCIFA_INP_ADCIN2 2 |
#define | AVR32_ADCIFA_INP_ADCIN3 3 |
#define | AVR32_ADCIFA_INP_ADCIN4 4 |
#define | AVR32_ADCIFA_INP_ADCIN5 5 |
#define | AVR32_ADCIFA_INP_ADCIN6 6 |
#define | AVR32_ADCIFA_INP_ADCIN7 7 |
#define | AVR32_ADCIFA_INP_DAC0_INT 8 |
#define | AVR32_ADCIFA_INP_GNDANA 10 |
#define | AVR32_ADCIFA_INP_TSENSE 9 |
Functions | |
U8 | adcifa_configure (volatile avr32_adcifa_t *adcifa, adcifa_opt_t *p_adcifa_opt, U32 pb_hz) |
Configure ADCIFA. Mandatory to call. If not called, ADC channels will have side effects. | |
U8 | adcifa_configure_sequencer (volatile avr32_adcifa_t *adcifa, U8 sequencer, adcifa_sequencer_opt_t *p_adcifa_sequencer_opt, adcifa_sequencer_conversion_opt_t *p_adcifa_sequencer_conversion_opt) |
Configure ADCIFA specific sequencer.
| |
void | adcifa_get_calibration_data (volatile avr32_adcifa_t *adcifa, adcifa_opt_t *p_adcifa_opt, U8 sequencer) |
Get ADCIFA Calibration Data. Mandatory to call if factory calibration data are wanted to be used. If not called, Calibration Data should be set by the application. | |
U8 | adcifa_get_values_from_sequencer (volatile avr32_adcifa_t *adcifa, U8 sequencer, adcifa_sequencer_opt_t *p_adcifa_sequencer_opt, S16 *adcifa_values) |
Get channel values for a specific sequence. | |
void | adcifa_start_sequencer (volatile avr32_adcifa_t *adcifa, U8 sequencer) |
Start analog to digital conversion for a specific sequencer. |
#define ADCIFA_CONFIGURATION_ACCEPTED 0x1 |
This constant is used as return value for "adcifa_configure" and "adcifa_configure_sequencer" functions.
Definition at line 271 of file adcifa.h.
Referenced by adcifa_configure(), and adcifa_configure_sequencer().
#define ADCIFA_CONFIGURATION_REFUSED 0x0 |
#define ADCIFA_configure_muxsel0n | ( | m7, | |||
m6, | |||||
m5, | |||||
m4, | |||||
m3, | |||||
m2, | |||||
m1, | |||||
m0 | ) |
Value:
{\ AVR32_ADCIFA.innsel10 = ((m7) << AVR32_ADCIFA_INNSEL10_CNV7_OFFSET) | ((m6) << AVR32_ADCIFA_INNSEL10_CNV6_OFFSET) | ((m5) << AVR32_ADCIFA_INNSEL10_CNV5_OFFSET) | ((m4) << AVR32_ADCIFA_INNSEL10_CNV4_OFFSET);\ AVR32_ADCIFA.innsel00 = ((m3) << AVR32_ADCIFA_INNSEL00_CNV3_OFFSET) | ((m2) << AVR32_ADCIFA_INNSEL00_CNV2_OFFSET) | ((m1) << AVR32_ADCIFA_INNSEL00_CNV1_OFFSET) | ((m0) << AVR32_ADCIFA_INNSEL00_CNV0_OFFSET);\ }
Definition at line 200 of file adcifa.h.
Referenced by adcifa_configure_sequencer().
#define ADCIFA_configure_muxsel0p | ( | m7, | |||
m6, | |||||
m5, | |||||
m4, | |||||
m3, | |||||
m2, | |||||
m1, | |||||
m0 | ) |
Value:
{\ AVR32_ADCIFA.inpsel10 = ((m7) << AVR32_ADCIFA_INNSEL10_CNV7_OFFSET) | ((m6) << AVR32_ADCIFA_INNSEL10_CNV6_OFFSET) | ((m5) << AVR32_ADCIFA_INNSEL10_CNV5_OFFSET) | ((m4) << AVR32_ADCIFA_INNSEL10_CNV4_OFFSET);\ AVR32_ADCIFA.inpsel00 = ((m3) << AVR32_ADCIFA_INNSEL00_CNV3_OFFSET) | ((m2) << AVR32_ADCIFA_INNSEL00_CNV2_OFFSET) | ((m1) << AVR32_ADCIFA_INNSEL00_CNV1_OFFSET) | ((m0) << AVR32_ADCIFA_INNSEL00_CNV0_OFFSET);\ }
Definition at line 193 of file adcifa.h.
Referenced by adcifa_configure_sequencer().
#define ADCIFA_configure_muxsel1n | ( | m7, | |||
m6, | |||||
m5, | |||||
m4, | |||||
m3, | |||||
m2, | |||||
m1, | |||||
m0 | ) |
Value:
{\ AVR32_ADCIFA.innsel11 = ((m7) << AVR32_ADCIFA_INNSEL10_CNV7_OFFSET) | ((m6) << AVR32_ADCIFA_INNSEL10_CNV6_OFFSET) | ((m5) << AVR32_ADCIFA_INNSEL10_CNV5_OFFSET) | ((m4) << AVR32_ADCIFA_INNSEL10_CNV4_OFFSET);\ AVR32_ADCIFA.innsel01 = ((m3) << AVR32_ADCIFA_INNSEL00_CNV3_OFFSET) | ((m2) << AVR32_ADCIFA_INNSEL00_CNV2_OFFSET) | ((m1) << AVR32_ADCIFA_INNSEL00_CNV1_OFFSET) | ((m0) << AVR32_ADCIFA_INNSEL00_CNV0_OFFSET);\ }
Definition at line 249 of file adcifa.h.
Referenced by adcifa_configure_sequencer().
#define ADCIFA_configure_muxsel1p | ( | m7, | |||
m6, | |||||
m5, | |||||
m4, | |||||
m3, | |||||
m2, | |||||
m1, | |||||
m0 | ) |
Value:
{\ AVR32_ADCIFA.inpsel11 = ((m7) << AVR32_ADCIFA_INNSEL10_CNV7_OFFSET) | ((m6) << AVR32_ADCIFA_INNSEL10_CNV6_OFFSET) | ((m5) << AVR32_ADCIFA_INNSEL10_CNV5_OFFSET) | ((m4) << AVR32_ADCIFA_INNSEL10_CNV4_OFFSET);\ AVR32_ADCIFA.inpsel01 = ((m3) << AVR32_ADCIFA_INNSEL00_CNV3_OFFSET) | ((m2) << AVR32_ADCIFA_INNSEL00_CNV2_OFFSET) | ((m1) << AVR32_ADCIFA_INNSEL00_CNV1_OFFSET) | ((m0) << AVR32_ADCIFA_INNSEL00_CNV0_OFFSET);\ }
Definition at line 242 of file adcifa.h.
Referenced by adcifa_configure_sequencer().
#define ADCIFA_configure_sequencer_0 | ( | cnvnb, | |||
sres, | |||||
trgsel, | |||||
socb, | |||||
csws, | |||||
hwla, | |||||
sa | ) |
Value:
{AVR32_ADCIFA.seqcfg0 = ( (cnvnb<<AVR32_ADCIFA_SEQCFG0_CNVNB)|\ (sres<<AVR32_ADCIFA_SEQCFG0_SRES)|\ (trgsel<<AVR32_ADCIFA_SEQCFG0_TRGSEL)|\ (socb<<AVR32_ADCIFA_SEQCFG0_SOCB)|\ (csws<<AVR32_ADCIFA_SEQCFG0_CSWS)|\ (hwla<<AVR32_ADCIFA_SEQCFG0_HWLA)|\ (sa<<AVR32_ADCIFA_SEQCFG0_SA) ); }
Configuration of Sequencer 0 cnvb : Number of conversion sres : ADCIFA Resolution trgsel : Trigger Selection socb : Start of Conversion Selection csws : CSWS Mode Selection hwla : HWLA Mode Selection sa : SA Mode Selection
Definition at line 174 of file adcifa.h.
Referenced by adcifa_configure_sequencer().
#define ADCIFA_configure_sequencer_1 | ( | cnvnb, | |||
sres, | |||||
trgsel, | |||||
socb, | |||||
csws, | |||||
hwla, | |||||
sa | ) |
Value:
{AVR32_ADCIFA.seqcfg1 = ((cnvnb)<<AVR32_ADCIFA_SEQCFG1_CNVNB)|\ ((sres)<<AVR32_ADCIFA_SEQCFG1_SRES)|\ ((trgsel)<<AVR32_ADCIFA_SEQCFG1_TRGSEL)|\ ((socb)<<AVR32_ADCIFA_SEQCFG1_SOCB)|\ ((csws)<<AVR32_ADCIFA_SEQCFG1_CSWS)|\ ((hwla)<<AVR32_ADCIFA_SEQCFG1_HWLA)|\ ((sa)<<AVR32_ADCIFA_SEQCFG1_SA);}
Configuration of Sequencer 1 cnvb : Number of conversion sres : ADCIFA Resolution trgsel : Trigger Selection socb : Start of Conversion Selection csws : CSWS Mode Selection hwla : HWLA Mode Selection sa : SA Mode Selection
Definition at line 223 of file adcifa.h.
Referenced by adcifa_configure_sequencer().
#define ADCIFA_configure_sh0gain | ( | g7, | |||
g6, | |||||
g5, | |||||
g4, | |||||
g3, | |||||
g2, | |||||
g1, | |||||
g0 | ) | { AVR32_ADCIFA.shg0 = ((g7) << AVR32_ADCIFA_GCNV7_OFFSET) | ((g6) << AVR32_ADCIFA_GCNV6_OFFSET) | ((g5) << AVR32_ADCIFA_GCNV5_OFFSET) |((g4) << AVR32_ADCIFA_GCNV4_OFFSET) |((g3) << AVR32_ADCIFA_GCNV3_OFFSET) |((g2) << AVR32_ADCIFA_GCNV2_OFFSET) |((g1) << AVR32_ADCIFA_GCNV1_OFFSET) |((g0) << AVR32_ADCIFA_GCNV0_OFFSET); } |
Configuration of Gain for Sequencer 0 g(x) : Gain for element x of Sequencer 0
Definition at line 207 of file adcifa.h.
Referenced by adcifa_configure_sequencer().
#define ADCIFA_configure_sh1gain | ( | g7, | |||
g6, | |||||
g5, | |||||
g4, | |||||
g3, | |||||
g2, | |||||
g1, | |||||
g0 | ) | { AVR32_ADCIFA.shg1 = ((g7) << AVR32_ADCIFA_GCNV7_OFFSET) | ((g6) << AVR32_ADCIFA_GCNV6_OFFSET) | ((g5) << AVR32_ADCIFA_GCNV5_OFFSET) |((g4) << AVR32_ADCIFA_GCNV4_OFFSET) |((g3) << AVR32_ADCIFA_GCNV3_OFFSET) |((g2) << AVR32_ADCIFA_GCNV2_OFFSET) |((g1) << AVR32_ADCIFA_GCNV1_OFFSET) |((g0) << AVR32_ADCIFA_GCNV0_OFFSET); } |
Configuration of Gain for Sequencer 1 g(x) : Gain for element x of Sequencer 1
Definition at line 256 of file adcifa.h.
Referenced by adcifa_configure_sequencer().
#define ADCIFA_CSWS_WSTATE 0x1 |
#define ADCIFA_disable | ( | ) | { AVR32_ADCIFA.cfg &= ~(1 << AVR32_ADCIFA_CFG_ADCEN); } |
#define ADCIFA_enable | ( | ) | { AVR32_ADCIFA.cfg |= (1 << AVR32_ADCIFA_CFG_ADCEN); } |
#define ADCIFA_HWLA_NOADJ 0x0 |
#define ADCIFA_is_eoc_sequencer_0 | ( | ) | (((AVR32_ADCIFA.sr)&(1<<AVR32_ADCIFA_SR_SEOC0))==(1<<AVR32_ADCIFA_SR_SEOC0)) |
Sequencer 0 : Check end of Conversion.
Definition at line 186 of file adcifa.h.
Referenced by adcifa_check_eoc().
#define ADCIFA_is_eoc_sequencer_1 | ( | ) | (((AVR32_ADCIFA.sr)&(1<<AVR32_ADCIFA_SR_SEOC1))==(1<<AVR32_ADCIFA_SR_SEOC1)) |
Sequencer 1 : Check end of Conversion.
Definition at line 235 of file adcifa.h.
Referenced by adcifa_check_eoc().
#define ADCIFA_is_eos_sequencer_0 | ( | ) | (((AVR32_ADCIFA.sr)&(1<<AVR32_ADCIFA_SR_SEOS0))==(1<<AVR32_ADCIFA_SR_SEOS0)) |
Sequencer 0 : Check end of Sequence.
Definition at line 189 of file adcifa.h.
Referenced by adcifa_check_eos().
#define ADCIFA_is_eos_sequencer_1 | ( | ) | (((AVR32_ADCIFA.sr)&(1<<AVR32_ADCIFA_SR_SEOS1))==(1<<AVR32_ADCIFA_SR_SEOS1)) |
Sequencer 1 : Check end of Sequence.
Definition at line 238 of file adcifa.h.
Referenced by adcifa_check_eos().
#define ADCIFA_is_startup_time | ( | ) | (((AVR32_ADCIFA.sr) & (1 << AVR32_ADCIFA_SR_SUTD)) == (1 << AVR32_ADCIFA_SR_SUTD)) |
#define ADCIFA_read_resx_sequencer_0 | ( | ind | ) | ((int)AVR32_ADCIFA.resx[(ind)]) |
Return result for conversion for Sequencer 0 ind : Index on element of Sequencer 0
Definition at line 211 of file adcifa.h.
Referenced by adcifa_get_values_from_sequencer().
#define ADCIFA_read_resx_sequencer_1 | ( | ind | ) | ((int)AVR32_ADCIFA.resx[(ind)+8]) |
Return result for conversion for Sequencer 1 ind : Index on element of Sequencer 1
Definition at line 260 of file adcifa.h.
Referenced by adcifa_get_values_from_sequencer().
#define ADCIFA_REF1V 0x0 |
#define ADCIFA_SA_EOS_SOFTACK 0x0 |
#define ADCIFA_SEQ0 0x0 |
Local Definition for Sequencer numbers
Definition at line 139 of file adcifa.h.
Referenced by adcifa_start_sequencer().
#define ADCIFA_SEQ0_SEQ1 0x3 |
#define ADCIFA_SEQ1 0x1 |
#define ADCIFA_set_gain_calibration | ( | gcal | ) | { AVR32_ADCIFA.adccal |=((gcal)<<AVR32_ADCIFA_ADCCAL_GCAL)&AVR32_ADCIFA_ADCCAL_GCAL_MASK; } |
#define ADCIFA_set_offset_calibration | ( | ocal | ) | { AVR32_ADCIFA.adccal |=((ocal)<<AVR32_ADCIFA_ADCCAL_OCAL)&AVR32_ADCIFA_ADCCAL_OCAL_MASK; } |
--------------------------- ADCIFA Core Management ---------------------------------
Set Offset Calibration
Definition at line 150 of file adcifa.h.
Referenced by adcifa_configure().
#define ADCIFA_set_sh_gain_calibration | ( | scal | ) | { AVR32_ADCIFA.shcal =((scal)&(AVR32_ADCIFA_SHCAL_GAIN1_MASK | AVR32_ADCIFA_SHCAL_GAIN0_MASK)); } |
Set Sample & Hold Gain Calibration.
Definition at line 154 of file adcifa.h.
Referenced by adcifa_configure().
#define ADCIFA_SHG_1 0x0 |
#define ADCIFA_SOCB_ALLSEQ 0x0 |
#define ADCIFA_softsoc_sequencer | ( | seq | ) | { AVR32_ADCIFA.cr = (seq); } |
#define ADCIFA_softsoc_sequencer_0 | ( | ) | { AVR32_ADCIFA.cr = AVR32_ADCIFA_CR_SOC0_MASK; } |
#define ADCIFA_softsoc_sequencer_1 | ( | ) | { AVR32_ADCIFA.cr = AVR32_ADCIFA_CR_SOC1_MASK; } |
#define ADCIFA_SRES_8B 0x2 |
#define ADCIFA_START_UP_TIME 1000 |
Local Definition for Start-Up time
Definition at line 145 of file adcifa.h.
Referenced by adcifa_configure().
#define ADCIFA_STATUS_COMPLETED 0x2 |
This constant is used as return value for "adcifa_get_values_seq" function.
Definition at line 274 of file adcifa.h.
Referenced by adcifa_get_values_from_sequencer(), and main().
#define ADCIFA_STATUS_NOT_COMPLETED 0x3 |
This constant is used as return value for "adcifa_get_values_seq" function.
Definition at line 277 of file adcifa.h.
Referenced by adcifa_get_values_from_sequencer().
#define ADCIFA_TRGSEL_SOFT 0x0 |
#define AVR32_ADCIFA_INN_ADCIN8 0 |
#define AVR32_ADCIFA_INP_ADCIN0 0 |
U8 adcifa_configure | ( | volatile avr32_adcifa_t * | adcifa, | |
adcifa_opt_t * | p_adcifa_opt, | |||
U32 | pb_hz | |||
) |
Configure ADCIFA. Mandatory to call. If not called, ADC channels will have side effects.
*adcifa | Base address of the ADCIFA | |
*p_adcifa_opt | Structure for the ADCIFA core configuration | |
pb_hz | Periphal Bus frequency |
U8 adcifa_configure_sequencer | ( | volatile avr32_adcifa_t * | adcifa, | |
U8 | sequencer, | |||
adcifa_sequencer_opt_t * | p_adcifa_sequencer_opt, | |||
adcifa_sequencer_conversion_opt_t * | p_adcifa_sequencer_conversion_opt | |||
) |
Configure ADCIFA specific sequencer.
*adcifa | Base address of the ADCIFA | |
sequencer | 0: sequencer 0 - 1: sequencer 1 | |
*p_adcifa_sequencer_opt | Structure for the sequencer configuration | |
*p_adcifa_sequencer_conversion_opt | Pointer on a buffer for each conversion on a sequencer |
Definition at line 116 of file adcifa.c.
References ADCIFA_CONFIGURATION_ACCEPTED, ADCIFA_configure_muxsel0n, ADCIFA_configure_muxsel0p, ADCIFA_configure_muxsel1n, ADCIFA_configure_muxsel1p, ADCIFA_configure_sequencer_0, ADCIFA_configure_sequencer_1, ADCIFA_configure_sh0gain, ADCIFA_configure_sh1gain, adcifa_sequencer_conversion_opt_t::channel_n, adcifa_sequencer_conversion_opt_t::channel_p, adcifa_sequencer_opt_t::convnb, adcifa_sequencer_opt_t::half_word_adjustment, adcifa_sequencer_opt_t::oversampling, adcifa_sequencer_opt_t::resolution, adcifa_sequencer_opt_t::software_acknowledge, adcifa_sequencer_opt_t::start_of_conversion, and adcifa_sequencer_opt_t::trigger_selection.
Referenced by main().
00120 { 00121 U8 g[8]={0}; 00122 U8 mp[8]={0}; 00123 U8 mn[8]={0}; 00124 U8 i; 00125 // Sanity Check 00126 Assert( adcifa!=NULL ); 00127 00128 // Switch case with sequencer 00129 switch (sequencer) 00130 { 00131 // Sequencer 0 00132 case 0: 00133 // Configure Sequencer 0 00134 ADCIFA_configure_sequencer_0((p_adcifa_sequencer_opt->convnb-1), 00135 p_adcifa_sequencer_opt->resolution, 00136 p_adcifa_sequencer_opt->trigger_selection, 00137 p_adcifa_sequencer_opt->start_of_conversion, 00138 p_adcifa_sequencer_opt->oversampling, 00139 p_adcifa_sequencer_opt->half_word_adjustment, 00140 p_adcifa_sequencer_opt->software_acknowledge); 00141 00142 // Configure Gain for Sequencer 0 00143 for (i = 0; i < p_adcifa_sequencer_opt->convnb; i++) 00144 g[i] = p_adcifa_sequencer_conversion_opt[i].gain; 00145 ADCIFA_configure_sh0gain(g[7], g[6], g[5], g[4], g[3], g[2], g[1], g[0]); 00146 00147 // Configure Mux for Sequencer 0 00148 for (i = 0; i < p_adcifa_sequencer_opt->convnb; i++) 00149 { 00150 mp[i] = p_adcifa_sequencer_conversion_opt[i].channel_p; 00151 mn[i] = p_adcifa_sequencer_conversion_opt[i].channel_n; 00152 } 00153 ADCIFA_configure_muxsel0p(mp[7], mp[6], mp[5], mp[4], mp[3], mp[2], mp[1], mp[0]); 00154 ADCIFA_configure_muxsel0n(mn[7], mn[6], mn[5], mn[4], mn[3], mn[2], mn[1], mn[0]); 00155 break; 00156 // Sequencer 1 00157 case 1: 00158 // Configure Sequencer 1 00159 ADCIFA_configure_sequencer_1(p_adcifa_sequencer_opt->convnb-1, 00160 p_adcifa_sequencer_opt->resolution, 00161 p_adcifa_sequencer_opt->trigger_selection, 00162 p_adcifa_sequencer_opt->start_of_conversion, 00163 p_adcifa_sequencer_opt->oversampling, 00164 p_adcifa_sequencer_opt->half_word_adjustment, 00165 p_adcifa_sequencer_opt->software_acknowledge); 00166 00167 // Configure Gain for Sequencer 1 00168 for (i = 0; i < p_adcifa_sequencer_opt->convnb; i++) 00169 g[i] = p_adcifa_sequencer_conversion_opt[i].gain; 00170 ADCIFA_configure_sh1gain(g[7], g[6], g[5], g[4], g[3], g[2], g[1], g[0]); 00171 00172 // Configure Mux for Sequencer 1 00173 for (i = 0 ; i < p_adcifa_sequencer_opt->convnb; i++) 00174 { 00175 mp[i] = p_adcifa_sequencer_conversion_opt[i].channel_p; 00176 mn[i] = p_adcifa_sequencer_conversion_opt[i].channel_n; 00177 } 00178 ADCIFA_configure_muxsel1p(mp[7], mp[6], mp[5], mp[4], mp[3], mp[2], mp[1], mp[0]); 00179 ADCIFA_configure_muxsel1n(mn[7], mn[6], mn[5], mn[4], mn[3], mn[2], mn[1], mn[0]); 00180 break; 00181 default: 00182 break; 00183 } 00184 return ADCIFA_CONFIGURATION_ACCEPTED; 00185 }
void adcifa_get_calibration_data | ( | volatile avr32_adcifa_t * | adcifa, | |
adcifa_opt_t * | p_adcifa_opt, | |||
U8 | sequencer | |||
) |
Get ADCIFA Calibration Data. Mandatory to call if factory calibration data are wanted to be used. If not called, Calibration Data should be set by the application.
*adcifa | Base address of the ADCIFA | |
*p_adcifa_opt | Structure for the ADCIFA core configuration | |
sequencer | 0: sequencer 0 - 1: sequencer 1 |
Definition at line 52 of file adcifa.c.
References adcifa_opt_t::gain_calibration_value, adcifa_opt_t::offset_calibration_value, and adcifa_opt_t::sh_calibration_value.
Referenced by main().
00055 { 00056 unsigned int* calibration_data_adc = (unsigned int*)AVR32_FLASHC_CALIBRATION_SECOND_WORD_ADDRESS; 00057 unsigned int* calibration_data_seq = (unsigned int*)AVR32_FLASHC_CALIBRATION_THIRD_WORD_ADDRESS; 00058 00059 // Get ADC Offset Calibration 00060 p_adcifa_opt->offset_calibration_value = (*calibration_data_adc >> 24); 00061 00062 // Get ADC Gain Calibration 00063 p_adcifa_opt->gain_calibration_value = ((*calibration_data_adc) & AVR32_ADCIFA_ADCCAL_GCAL_MASK) ; 00064 00065 if (sequencer == 0) 00066 { 00067 // Get Sample & Hold Gain Calibration 00068 p_adcifa_opt->sh_calibration_value = ((*calibration_data_seq) & AVR32_ADCIFA_SHCAL_GAIN0_MASK); 00069 } 00070 else 00071 { 00072 // Get Sample & Hold Gain Calibration 00073 p_adcifa_opt->sh_calibration_value = ((*calibration_data_seq >> AVR32_ADCIFA_SHCAL_GAIN1_OFFSET)& AVR32_ADCIFA_SHCAL_GAIN1_MASK); 00074 } 00075 }
U8 adcifa_get_values_from_sequencer | ( | volatile avr32_adcifa_t * | adcifa, | |
U8 | sequencer, | |||
adcifa_sequencer_opt_t * | p_adcifa_sequencer_opt, | |||
S16 * | adcifa_values | |||
) |
Get channel values for a specific sequence.
*adcifa | Base address of the ADCIFA | |
sequencer | 0: sequencer 0 - 1: sequencer 1 | |
*p_adcifa_sequencer_opt | Structure for the sequencer configuration | |
adcifa_values | Pointer on the converter values |
Definition at line 246 of file adcifa.c.
References adcifa_check_eos(), ADCIFA_read_resx_sequencer_0, ADCIFA_read_resx_sequencer_1, ADCIFA_STATUS_COMPLETED, ADCIFA_STATUS_NOT_COMPLETED, and adcifa_sequencer_opt_t::convnb.
Referenced by main().
00250 { 00251 U8 i; 00252 // Sanity Check 00253 Assert( adcifa!=NULL ); 00254 00255 // wait for end of sequence 00256 if(adcifa_check_eos(adcifa, sequencer) != HIGH) 00257 return ADCIFA_STATUS_NOT_COMPLETED; 00258 00259 switch(sequencer) 00260 { 00261 case 0: 00262 // Read values from Sequencer 0 00263 for (i = 0; i < p_adcifa_sequencer_opt->convnb; i++) 00264 { 00265 adcifa_values[i] = ADCIFA_read_resx_sequencer_0(i); 00266 } 00267 break; 00268 case 1: 00269 // Read values from Sequencer 1 00270 for (i = 0; i < p_adcifa_sequencer_opt->convnb; i++) 00271 { 00272 adcifa_values[i] = ADCIFA_read_resx_sequencer_1(i); 00273 } 00274 break; 00275 default: 00276 break; 00277 } 00278 00279 return ADCIFA_STATUS_COMPLETED; 00280 }
void adcifa_start_sequencer | ( | volatile avr32_adcifa_t * | adcifa, | |
U8 | sequencer | |||
) |
Start analog to digital conversion for a specific sequencer.
*adcifa | Base address of the ADCIFA | |
sequencer | 0: sequencer 0 - 1: sequencer 1 |
Definition at line 187 of file adcifa.c.
References ADCIFA_SEQ0, ADCIFA_SEQ0_SEQ1, ADCIFA_SEQ1, and ADCIFA_softsoc_sequencer.
Referenced by main().
00188 { 00189 // Sanity Check 00190 Assert( adcifa!=NULL ); 00191 00192 // Switch Sequencer 00193 switch (sequencer) 00194 { 00195 case ADCIFA_SEQ0: 00196 ADCIFA_softsoc_sequencer(AVR32_ADCIFA_CR_SOC0_MASK); 00197 break; 00198 case ADCIFA_SEQ1: 00199 ADCIFA_softsoc_sequencer(AVR32_ADCIFA_CR_SOC1_MASK); 00200 break; 00201 case ADCIFA_SEQ0_SEQ1: 00202 ADCIFA_softsoc_sequencer(AVR32_ADCIFA_CR_SOC0_MASK | AVR32_ADCIFA_CR_SOC1_MASK); 00203 break; 00204 default: 00205 break; 00206 } 00207 }