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00050 #ifndef _SSC_I2S_H_
00051 #define _SSC_I2S_H_
00052
00053 #include <avr32/io.h>
00054
00055 #ifdef AVR32_SSC_330_H_INCLUDED
00056 #define AVR32_SSC_TCMR_START_DETECT_ANY_EDGE_TF 0x7
00057 #endif
00058
00059
00060 #define SSC_I2S_TIMEOUT_VALUE 10000
00061
00062
00063
00065 enum
00066 {
00067 SSC_I2S_ERROR = -1,
00068 SSC_I2S_OK = 0,
00069 SSC_I2S_TIMEOUT = 1,
00070 SSC_I2S_ERROR_ARGUMENT,
00071 SSC_I2S_ERROR_RX,
00072 SSC_I2S_ERROR_TX
00073 };
00074
00076 enum
00077 {
00078 SSC_I2S_MODE_STEREO_OUT = 1,
00079 SSC_I2S_MODE_STEREO_OUT_EXT_CLK,
00080 SSC_I2S_MODE_SLAVE_STEREO_OUT,
00081 SSC_I2S_MODE_SLAVE_STEREO_IN,
00082 SSC_I2S_MODE_STEREO_OUT_MONO_IN,
00083 SSC_I2S_MODE_RIGHT_IN,
00084 SSC_I2S_MODE_STEREO_IN,
00085 SSC_I2S_MODE_STEREO_OUT_STEREO_IN
00086 };
00087
00088
00093 extern void ssc_i2s_reset(volatile avr32_ssc_t *ssc);
00094
00115 extern int ssc_i2s_init(volatile avr32_ssc_t *ssc,
00116 unsigned int sample_frequency,
00117 unsigned int data_bit_res,
00118 unsigned int frame_bit_res,
00119 unsigned char mode,
00120 unsigned int pba_hz);
00121
00131 extern int ssc_i2s_transfer(volatile avr32_ssc_t *ssc, unsigned int data);
00132
00138 extern void ssc_i2s_disable_interrupts(volatile avr32_ssc_t *ssc, unsigned long int_mask);
00139
00145 extern void ssc_i2s_enable_interrupts(volatile avr32_ssc_t *ssc, unsigned long int_mask);
00146
00153 extern unsigned long ssc_i2s_get_status(volatile avr32_ssc_t *ssc);
00154
00155
00156 #endif // _SSC_I2S_H_