pm_uc3c.c File Reference


Detailed Description

Power Manager(PM) driver interface.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file pm_uc3c.c.

#include "pm_uc3c.h"

Go to the source code of this file.

Data Structures

union  u_avr32_pm_cfdctrl_t
union  u_avr32_pm_cpusel_t
union  u_avr32_pm_pbasel_t
union  u_avr32_pm_pbbsel_t
union  u_avr32_pm_pbcsel_t

Functions

long pm_config_mainclk_safety (bool cfd, bool final)
 Configure the main clock safety mechanisms.
long pm_disable_clk_domain_div (pm_clk_domain_t clock_domain)
 Disable the division ratio for a clock domain.
long pm_disable_module (unsigned long module)
 Disable the clock of a module.
long pm_enable_module (unsigned long module)
 Module Functions.
long pm_set_clk_domain_div (pm_clk_domain_t clock_domain, pm_divratio_t divratio)
 Set the division ratio for a clock domain.
long pm_set_mclk_source (pm_clk_src_t src)
 Clock Functions.
long pm_wait_for_clk_ready (void)
 Wait actively for the clock settings to be effective.


Function Documentation

long pm_config_mainclk_safety ( bool  cfd,
bool  final 
)

Configure the main clock safety mechanisms.

Note:
Refer to the section Clock Failure Detector of the PM chapter in the datasheet
Warning:
The Critical Path Oscillator (CRIPOSC) must be enabled before enabling the Over Clock Protection mechanism.
Parameters:
cfd Enable/disable the Clock Failure Detection mechanism
final If true, make this configuration definitive
Returns:
Status.
Return values:
=0 Success.
<0 An error occured.

Definition at line 108 of file pm_uc3c.c.

References u_avr32_pm_cfdctrl_t::cfdctrl, u_avr32_pm_cfdctrl_t::CFDCTRL, and PM_UNLOCK.

00109 {
00110   u_avr32_pm_cfdctrl_t u_avr32_pm_cfdctrl = {AVR32_PM.cfdctrl};
00111 
00112   // Check if the CFDCTRL register is read-only.
00113   if(AVR32_PM.cfdctrl & AVR32_PM_CFDCTRL_SFV_MASK)
00114     return -1;
00115 
00116   // Unlock the write-protected CFDCTRL register
00117   AVR32_ENTER_CRITICAL_REGION( );
00118   // Modify
00119   u_avr32_pm_cfdctrl.CFDCTRL.cfden = cfd;
00120   u_avr32_pm_cfdctrl.CFDCTRL.sfv = final;
00121   // Write back
00122   PM_UNLOCK(AVR32_PM_CFDCTRL);  
00123   AVR32_PM.cfdctrl = u_avr32_pm_cfdctrl.cfdctrl;
00124   AVR32_LEAVE_CRITICAL_REGION( );
00125   
00126   return PASS;
00127 }

long pm_disable_clk_domain_div ( pm_clk_domain_t  clock_domain  ) 

Disable the division ratio for a clock domain.

Parameters:
clock_domain The clock domain to alter.
Warning:
Care should be taken that each new frequency of the synchronous clocks does not exceed the maximum frequency for each clock domain.
Returns:
Status.
Return values:
=0 Success.
<0 An error occured.

Definition at line 162 of file pm_uc3c.c.

Referenced by pm_set_all_cksel().

00163 {
00164   u_avr32_pm_cpusel_t u_avr32_pm_cpusel = {AVR32_PM.cpusel};
00165 
00166 //# Implementation note: the CPUSEL and PBASEL and PBBSEL and PBCSEL registers all have the
00167 //# same structure.
00168 
00169 //# Implementation note: the ckSEL registers are contiguous and memory-mapped in
00170 //# that order: CPUSEL, HSBSEL, PBASEL, PBBSEL, PBCSEL.
00171 
00172   // ckSEL must not be written while SR.CKRDY is 0.
00173   if(!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK))
00174     return -1;
00175 
00176   // Modify
00177   u_avr32_pm_cpusel.CPUSEL.cpudiv= DISABLE;
00178   AVR32_ENTER_CRITICAL_REGION( );
00179   // Unlock the write-protected ckSEL register
00180   PM_UNLOCK(AVR32_PM_CPUSEL + clock_domain*sizeof(avr32_pm_cpusel_t));
00181   // Update
00182   *(&(AVR32_PM.cpusel) + clock_domain)= u_avr32_pm_cpusel.cpusel;
00183   AVR32_LEAVE_CRITICAL_REGION( );
00184 
00185   return PASS;
00186 }

long pm_disable_module ( unsigned long  module  ) 

Disable the clock of a module.

Parameters:
module The module to shut down (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
Returns:
Status.
Return values:
0 Success.
<0 An error occured.

Definition at line 228 of file pm_uc3c.c.

00229 {
00230   unsigned long domain = module>>5;
00231 //# Implementation note: the ckMASK registers are contiguous and memory-mapped
00232 //# in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.
00233   volatile unsigned long *regptr = (volatile unsigned long*)(&(AVR32_PM.cpumask) + domain);
00234   unsigned long regvalue;
00235 
00236 
00237   // Read
00238   regvalue = *regptr;
00239   // Modify
00240   regvalue &= ~(1<<(module%32));
00241   AVR32_ENTER_CRITICAL_REGION( );
00242   // Unlock the write-protected ckMASK register
00243   PM_UNLOCK(AVR32_PM_CPUMASK + domain*sizeof(avr32_pm_cpumask_t));
00244   // Write
00245   *regptr = regvalue;
00246   AVR32_LEAVE_CRITICAL_REGION( );
00247 
00248   return PASS;
00249 }

long pm_enable_module ( unsigned long  module  ) 

Module Functions.

Enable the clock of a module.

Definition at line 205 of file pm_uc3c.c.

00206 {
00207   unsigned long domain = module>>5;
00208 //# Implementation note: the ckMASK registers are contiguous and memory-mapped
00209 //# in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.
00210   unsigned long *regptr = (unsigned long*)(&(AVR32_PM.cpumask) + domain);  
00211   unsigned long regvalue;
00212 
00213 
00214   // Read
00215   regvalue = *regptr;
00216   // Modify
00217   regvalue |= (1<<(module%32));
00218   AVR32_ENTER_CRITICAL_REGION( );
00219   // Unlock the write-protected ckMASK register
00220   PM_UNLOCK(AVR32_PM_CPUMASK + domain*sizeof(avr32_pm_cpumask_t));
00221   // Write
00222   *regptr = regvalue;
00223   AVR32_LEAVE_CRITICAL_REGION( );
00224 
00225   return PASS;
00226 }

long pm_set_clk_domain_div ( pm_clk_domain_t  clock_domain,
pm_divratio_t  divratio 
)

Set the division ratio for a clock domain.

Parameters:
clock_domain The clock domain to alter.
divratio The division ratio to set.
Warning:
Care should be taken that each new frequency of the synchronous clocks does not exceed the maximum frequency for each clock domain.
Returns:
Status.
Return values:
=0 Success.
<0 An error occured.

Definition at line 129 of file pm_uc3c.c.

Referenced by local_set_main_clock_to_rc120m(), and pm_set_all_cksel().

00130 {
00131   u_avr32_pm_cpusel_t u_avr32_pm_cpusel = {AVR32_PM.cpusel};
00132 
00133 //# Implementation note: the CPUSEL and PBASEL and PBBSEL registers all have the
00134 //# same structure.
00135 
00136 //# Implementation note: the ckSEL registers are contiguous and memory-mapped in
00137 //# that order: CPUSEL, HSBSEL, PBASEL, PBBSEL.
00138   
00139 #ifdef AVR32SFW_INPUT_CHECK
00140   // Check the divratio
00141   if((divratio > PM_CPUSEL_DIVRATIO_MAX)||(divratio < 0))
00142     return -1;
00143 #endif
00144 
00145   // ckSEL must not be written while SR.CKRDY is 0.
00146   if(!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK))
00147     return -1;
00148 
00149   // Modify
00150   u_avr32_pm_cpusel.CPUSEL.cpudiv= 1;
00151   u_avr32_pm_cpusel.CPUSEL.cpusel = divratio;
00152   AVR32_ENTER_CRITICAL_REGION( );
00153   // Unlock the write-protected ckSEL register
00154   PM_UNLOCK(AVR32_PM_CPUSEL + clock_domain*sizeof(avr32_pm_cpusel_t));
00155   // Update
00156   *(&(AVR32_PM.cpusel) + clock_domain)= u_avr32_pm_cpusel.cpusel;
00157   AVR32_LEAVE_CRITICAL_REGION( );
00158 
00159   return PASS;
00160 }

long pm_set_mclk_source ( pm_clk_src_t  src  ) 

Clock Functions.

Set the main clock.

Definition at line 97 of file pm_uc3c.c.

Referenced by local_set_main_clock_to_rc120m(), and pcl_switch_to_osc().

00098 {
00099   // Unlock the write-protected MCCTRL register
00100   AVR32_ENTER_CRITICAL_REGION( );
00101   PM_UNLOCK(AVR32_PM_MCCTRL);
00102   AVR32_PM.mcctrl = src;
00103   AVR32_LEAVE_CRITICAL_REGION( );
00104   
00105   return PASS;
00106 }

long pm_wait_for_clk_ready ( void   ) 

Wait actively for the clock settings to be effective.

Note:
To avoid an infinite loop, this function checks the clock ready flag PM_POLL_TIMEOUT times.
Returns:
Status.
Return values:
0 Success.
<0 Unable to reach a clock ready status within the polling limit.

Definition at line 188 of file pm_uc3c.c.

00189 {
00190   unsigned int timeout = PM_POLL_TIMEOUT;
00191   while (!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK))
00192   {
00193     if(--timeout == 0)
00194       return -1;
00195   }
00196   return PASS;
00197 }


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