pm_example2.c File Reference


Detailed Description

High frequency Main clock source and Generic clock configurations.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file pm_example2.c.

#include "board.h"
#include "gpio.h"
#include "pm.h"
#include "flashc.h"

Go to the source code of this file.

Defines

Generic Clock Configuration
#define EXAMPLE_CPUCLK_HZ   (48000000UL)
#define EXAMPLE_DFLL_COARSE_FDFLL96   150
#define EXAMPLE_DFLL_FINE_FDFLL96   65
#define EXAMPLE_GCLK_FUNCTION   AVR32_SCIF_GCLK_1_0_FUNCTION
#define EXAMPLE_GCLK_ID   AVR32_SCIF_GCLK_DFLL0_SSG
#define EXAMPLE_GCLK_PIN   AVR32_SCIF_GCLK_1_0_PIN

Functions

static void local_start_gc (void)
static void local_start_highfreq_clock (void)
int main (void)
static void software_delay (void)


Define Documentation

#define EXAMPLE_CPUCLK_HZ   (48000000UL)

Definition at line 151 of file pm_example2.c.

Referenced by local_start_highfreq_clock().

#define EXAMPLE_DFLL_COARSE_FDFLL96   150

Definition at line 154 of file pm_example2.c.

Referenced by local_start_highfreq_clock().

#define EXAMPLE_DFLL_FINE_FDFLL96   65

Definition at line 155 of file pm_example2.c.

Referenced by local_start_highfreq_clock().

#define EXAMPLE_GCLK_FUNCTION   AVR32_SCIF_GCLK_1_0_FUNCTION

Definition at line 150 of file pm_example2.c.

Referenced by local_start_gc().

#define EXAMPLE_GCLK_ID   AVR32_SCIF_GCLK_DFLL0_SSG

Definition at line 148 of file pm_example2.c.

Referenced by local_start_gc().

#define EXAMPLE_GCLK_PIN   AVR32_SCIF_GCLK_1_0_PIN

Definition at line 149 of file pm_example2.c.

Referenced by local_start_gc().


Function Documentation

static void local_start_gc ( void   )  [static]

Definition at line 308 of file pm_example2.c.

References EXAMPLE_GCLK_FUNCTION, EXAMPLE_GCLK_ID, EXAMPLE_GCLK_PIN, pm_gc_enable(), and pm_gc_setup().

Referenced by main().

00309 {
00310 #if BOARD == STK600_RCUC3L0 || BOARD == UC3L_EK
00311   // Note: for UC3L devices, the generic clock configurations are handled by the
00312   // SCIF module.
00313   // Setup gc to use the DFLL0 as source clock, divisor enabled, apply a division factor.
00314   // Since the DFLL0 frequency is 96MHz, set the division factor to 2 to have a
00315   // gclk frequency of 48MHz.
00316   scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_DFLL0, AVR32_GC_DIV_CLOCK, 2);
00317 
00318   /* Now enable the generic clock */
00319   scif_gc_enable(EXAMPLE_GCLK_ID);
00320 #elif BOARD == UC3C_EK 
00321   // Note: for UC3L and UC3C devices, the generic clock configurations are handled by the
00322   // SCIF module.
00323   /* setup gc on Osc0, no divisor */
00324   scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_PLL0, AVR32_SCIF_GC_NO_DIV_CLOCK, 0);
00325   
00326   /* Now enable the generic clock */
00327   scif_gc_enable(EXAMPLE_GCLK_ID);
00328 #else
00329   volatile avr32_pm_t* pm = &AVR32_PM;
00330   /* Setup generic clock on PLL0, with Osc0/PLL0, no divisor */
00331   /*
00332   void pm_gc_setup(volatile avr32_pm_t* pm,
00333                   unsigned int gc,
00334                   unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)
00335                   unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1
00336                   unsigned int diven,
00337                   unsigned int div) {
00338   */
00339   pm_gc_setup(pm,
00340               EXAMPLE_GCLK_ID,
00341               1,  // Use Osc (=0) or PLL (=1), here PLL
00342               0,  // Sel Osc0/PLL0 or Osc1/PLL1
00343               0,  // disable divisor
00344               0); // no divisor
00345 
00346   /* Enable Generic clock */
00347   pm_gc_enable(pm, EXAMPLE_GCLK_ID);
00348 #endif
00349   /* Set the GCLOCK function to the GPIO pin */
00350   gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION);
00351 }

static void local_start_highfreq_clock ( void   )  [static]

Definition at line 175 of file pm_example2.c.

References EXAMPLE_CPUCLK_HZ, EXAMPLE_DFLL_COARSE_FDFLL96, EXAMPLE_DFLL_FINE_FDFLL96, flashc_set_wait_state(), pm_cksel(), PM_CKSEL_DIVRATIO_2, PM_CKSEL_DIVRATIO_4, PM_CLK_DOMAIN_2, PM_CLK_SRC_DFLL0, PM_CLK_SRC_OSC0, PM_CLK_SRC_PLL0, pm_pll_enable(), pm_pll_set_option(), pm_pll_setup(), pm_set_clk_domain_div(), pm_set_mclk_source(), pm_switch_to_clock(), pm_switch_to_osc0(), and pm_wait_for_pll0_locked().

Referenced by main().

00176 {
00177 #if BOARD == STK600_RCUC3L0 || BOARD == UC3L_EK
00178   scif_dfll_openloop_conf_t dfllconfig = {EXAMPLE_DFLL_FINE_FDFLL96, EXAMPLE_DFLL_COARSE_FDFLL96};
00179 
00180   // Configure and start the DFLL0 in open loop mode to generate a frequency of 96MHz.
00181   scif_dfll0_openloop_start(&dfllconfig);
00182   
00183   // Since our target is to set the CPU&HSB frequency domains to 48MHz, we must
00184   // set one wait-state and enable the High-speed read mode on the flash controller. 
00185   flashcdw_set_flash_waitstate_and_readmode(EXAMPLE_CPUCLK_HZ);
00186   
00187   // Set the CPU clock domain to 48MHz (by applying a division ratio = 2).
00188   pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_2);
00189   
00190   // Set the PBA clock domain to 24MHz (by applying a division ratio = 4).
00191   pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_4);
00192   
00193   // Set the PBB clock domain to 48MHz (by applying a division ratio = 2).
00194   pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_2);
00195   
00196   // Set the main clock source to be DFLL0.
00197   pm_set_mclk_source(PM_CLK_SRC_DFLL0);
00198 #elif BOARD == UC3C_EK
00199   
00200   scif_pll_opt_t opt;
00201   
00202   // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
00203   scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
00204   
00205   // Enable the OSC0
00206   scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
00207   
00208   // Set the main clock source as being OSC0.
00209   pm_set_mclk_source(PM_CLK_SRC_OSC0);
00210 
00211   opt.osc = SCIF_OSC0;     // Sel Osc0 or Osc1
00212   opt.lockcount = 16;      // lockcount in main clock for the PLL wait lock
00213   opt.div = 1;             // DIV=1 in the formula
00214   opt.mul = 5;             // MUL=6 in the formula
00215   opt.pll_div2 = 1;        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
00216   opt.pll_wbwdisable = 0;  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
00217   opt.pll_freq = 1;        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
00218 
00219   scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock
00220       
00221   /* Enable PLL0 */
00222   scif_pll_enable(SCIF_PLL0);
00223 
00224   /* Wait for PLL0 locked */
00225   scif_wait_for_pll_locked(SCIF_PLL0) ;
00226   
00227   /* Divide PBA clock by 2 from main clock (PBA clock = 48MHz/2 = 24MHz).
00228      Pheripheral Bus A clock divisor enable = 1
00229      Pheripheral Bus A select = 0
00230      Pheripheral Bus B clock divisor enable = 0
00231      Pheripheral Bus B select = 0
00232      High Speed Bus clock divisor enable = 0
00233      High Speed Bus select = 0
00234   */  
00235   pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0); // PBA
00236 
00237   // Set one wait-state (WS) for flash controller. 0 WS access is up to 30MHz for HSB/CPU clock.
00238   // As we want to have 48MHz on HSB/CPU clock, we need to set 1 WS on flash controller.
00239   flashc_set_wait_state(1);
00240   
00241   // Set the main clock source as being PLL0.
00242   pm_set_mclk_source(PM_CLK_SRC_PLL0);
00243   
00244 #else
00245   volatile avr32_pm_t* pm = &AVR32_PM;
00246   /* \note All calculations here suppose that the Osc0 frequency is 12MHz. */
00247 
00248   pm_switch_to_osc0(pm, FOSC0, OSC0_STARTUP);  // Switch main clock to Osc0.
00249 
00250   /* Setup PLL0 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 12Mhzx8 = 96MHz output */
00251   /*void pm_pll_setup(volatile avr32_pm_t* pm,
00252                   unsigned int pll,
00253                   unsigned int mul,
00254                   unsigned int div,
00255                   unsigned int osc,
00256                   unsigned int lockcount) {
00257    */
00258   pm_pll_setup(pm,
00259                0,   // use PLL0
00260                7,   // MUL=7 in the formula
00261                1,   // DIV=1 in the formula
00262                0,   // Sel Osc0/PLL0 or Osc1/PLL1
00263                16); // lockcount in main clock for the PLL wait lock
00264 
00265   /*
00266    This function will set a PLL option.
00267    *pm Base address of the Power Manager (i.e. &AVR32_PM)
00268    pll PLL number 0
00269    pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
00270    pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
00271    pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
00272   */
00273   /* PLL output VCO frequency is 96MHz. We divide it by 2 with the pll_div2=1. This enable to get later main clock to 48MHz */
00274   pm_pll_set_option(pm, 0, 1, 1, 0);
00275 
00276   /* Enable PLL0 */
00277   /*
00278     void pm_pll_enable(volatile avr32_pm_t* pm,
00279                   unsigned int pll) {
00280   */
00281   pm_pll_enable(pm,0);
00282 
00283   /* Wait for PLL0 locked */
00284   pm_wait_for_pll0_locked(pm) ;
00285 
00286   /* Divide PBA clock by 2 from main clock (PBA clock = 48MHz/2 = 24MHz).
00287      Pheripheral Bus A clock divisor enable = 1
00288      Pheripheral Bus A select = 0
00289      Pheripheral Bus B clock divisor enable = 0
00290      Pheripheral Bus B select = 0
00291      High Speed Bus clock divisor enable = 0
00292      High Speed Bus select = 0
00293   */
00294   pm_cksel(pm, 1, 0, 0, 0, 0, 0);
00295 
00296   // Set one wait-state (WS) for flash controller. 0 WS access is up to 30MHz for HSB/CPU clock.
00297   // As we want to have 48MHz on HSB/CPU clock, we need to set 1 WS on flash controller.
00298   flashc_set_wait_state(1);
00299 
00300   pm_switch_to_clock(pm, AVR32_PM_MCSEL_PLL0); /* Switch main clock to 48MHz */
00301 #endif
00302 }

int main ( void   ) 

Definition at line 371 of file pm_example2.c.

References local_start_gc(), local_start_highfreq_clock(), and software_delay().

00372 {
00373   /* Start a high frequency clock and switch the main clock to that high frequency clock */
00374   local_start_highfreq_clock();
00375   
00376   /* Set-up a generic clock from a high frequency clock and output it to a gpio pin. */
00377   local_start_gc();
00378 
00379   /* Now toggle LED0 using a GPIO */
00380   while(1)
00381   {
00382     gpio_tgl_gpio_pin(LED0_GPIO);
00383     software_delay();
00384   }
00385 }

static void software_delay ( void   )  [static]

Definition at line 356 of file pm_example2.c.

Referenced by main().

00357 {
00358   volatile int i;
00359   for (i=0; i<1000000; i++);
00360 }


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