gpio_local_bus_example.c File Reference


Detailed Description

GPIO example application for AVR32 using the local bus interface.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file gpio_local_bus_example.c.

#include "compiler.h"
#include "preprocessor.h"
#include "board.h"
#include "pm.h"
#include "gpio.h"

Go to the source code of this file.

Defines

#define INSERT_GPIO_LOCAL_TGL_GPIO_PIN(idx, pin)   gpio_local_tgl_gpio_pin(pin);
Pin Configuration
#define GPIO_PIN_EXAMPLE   AVR32_PIN_PA10

Functions

static void fcpu_fpba_configure ()
int main (void)
 This is an example showing how to toggle a GPIO pin at high speed.


Define Documentation

#define GPIO_PIN_EXAMPLE   AVR32_PIN_PA10

Definition at line 125 of file gpio_local_bus_example.c.

Referenced by main().

#define INSERT_GPIO_LOCAL_TGL_GPIO_PIN ( idx,
pin   )     gpio_local_tgl_gpio_pin(pin);

Referenced by main().


Function Documentation

static void fcpu_fpba_configure (  )  [static]

Definition at line 142 of file gpio_local_bus_example.c.

Referenced by main().

00143 {
00144 #if UC3L
00145     static scif_gclk_opt_t gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, OFF };
00146     static pcl_freq_param_t pcl_dfll_freq_param =
00147     {
00148       .main_clk_src = PCL_MC_DFLL0,
00149       .cpu_f        = EXAMPLE_MCUCLK_HZ,
00150       .pba_f        = EXAMPLE_MCUCLK_HZ,
00151       .pbb_f        = EXAMPLE_MCUCLK_HZ,
00152       .dfll_f       = EXAMPLE_FDFLL_HZ,
00153       .pextra_params = &gc_dfllif_ref_opt
00154     };
00155 // Implementation for UC3L
00156     // Note: on the AT32UC3L-EK board, there is no crystal/external clock connected
00157     // to the OSC0 pinout XIN0/XOUT0. We shall then program the DFLL and switch the
00158     // main clock source to the DFLL.
00159     pcl_configure_clocks(&pcl_dfll_freq_param);
00160     // Note: since it is dynamically computing the appropriate field values of the
00161     // configuration registers from the parameters structure, this function is not
00162     // optimal in terms of code size. For a code size optimal solution, it is better
00163     // to create a new function from pcl_configure_clocks_dfll0() and modify it
00164     // to use preprocessor computation from pre-defined target frequencies.
00165 #elif UC3C
00166     // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
00167     scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
00168     // Enable the OSC0
00169     scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
00170     // Set the main clock source as being OSC0.
00171     pm_set_mclk_source(PM_CLK_SRC_OSC0);
00172 
00173     scif_pll_opt_t opt;
00174 
00175     // Setup PLL0 on Osc0, mul=10 ,no divisor, lockcount=16: (16Mhzx8)/2 = 64MHz output
00176     opt.osc = SCIF_OSC0;     // Sel Osc0 or Osc1
00177     opt.lockcount = 16;      // lockcount in main clock for the PLL wait lock
00178     opt.div = 1;             // DIV=1 in the formula
00179     opt.mul = 7;             // MUL=7 in the formula
00180     opt.pll_div2 = 1;        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
00181     opt.pll_wbwdisable = 0;  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
00182     opt.pll_freq = 1;        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
00183   
00184   
00185     scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock
00186   
00187     /* Enable PLL0 */
00188     scif_pll_enable(SCIF_PLL0);
00189   
00190     /* Wait for PLL0 locked */
00191     scif_wait_for_pll_locked(SCIF_PLL0) ;
00192 
00193     // Divide PLL0 output by 2 for CPU, HSB and PBx clocks = 32MHz
00194     pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) 0); // CPU
00195     pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) 0); // HSB
00196     pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) 0); // PBB          
00197     pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0); // PBA
00198     pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) 0); // PBC
00199   
00200     /* Set the main clock source as being PLL0. */
00201     pm_set_mclk_source(PM_CLK_SRC_PLL0);      
00202   
00203 #else
00204   // Switch the main clock source to Osc0.
00205   pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
00206 
00207   // Setup PLL0 on Osc0, mul=10 ,no divisor, lockcount=16: 12Mhzx11 = 132MHz output
00208   pm_pll_setup(&AVR32_PM, 0,  // pll.
00209                10,  // mul.
00210                1,   // div.
00211                0,   // osc.
00212                16); // lockcount.
00213   // PLL output VCO frequency is 132MHz.
00214   // We divide it by 2 with the pll_div2=1 to get a main clock at 66MHz.
00215   pm_pll_set_option(&AVR32_PM, 0, // pll.
00216                     1,  // pll_freq.
00217                     1,  // pll_div2.
00218                     0); // pll_wbwdisable.
00219   // Enable the PLL.
00220   pm_pll_enable(&AVR32_PM, 0);
00221   // Wait until the PLL output is stable.
00222   pm_wait_for_pll0_locked(&AVR32_PM);
00223   // Configure each clock domain to use the main clock divided by 2
00224   // => fCPU = fPBA = fPBB = 33MHz.
00225   pm_cksel(&AVR32_PM,
00226            1,   // pbadiv.
00227            0,   // pbasel.
00228            1,   // pbbdiv.
00229            0,   // pbbsel.
00230            1,   // hsbdiv=cpudiv
00231            0);  // hsbsel=cpusel
00232   // Switch the main clock source to PLL0.
00233   pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
00234 #endif
00235 }

int main ( void   ) 

This is an example showing how to toggle a GPIO pin at high speed.

Definition at line 240 of file gpio_local_bus_example.c.

References fcpu_fpba_configure(), GPIO_PIN_EXAMPLE, and INSERT_GPIO_LOCAL_TGL_GPIO_PIN.

00241 {
00242   // Initialize domain clocks (CPU, HSB, PBA and PBB) to the max frequency available
00243   // without flash wait states.
00244   // Some of the registers in the GPIO module are mapped onto the CPU local bus.
00245   // To ensure maximum transfer speed and cycle determinism, any slaves being
00246   // addressed by the CPU on the local bus must be able to receive and transmit
00247   // data on the bus at CPU clock speeds. The consequences of this is that the
00248   // GPIO module has to run at the CPU clock frequency when local bus transfers
00249   // are being performed => we want fPBA = fCPU.
00250   fcpu_fpba_configure();
00251 
00252   // Enable the local bus interface for GPIO.
00253   gpio_local_init();
00254 
00255   // Enable the output driver of the example pin.
00256   // Note that the GPIO mode of pins is enabled by default after reset.
00257   gpio_local_enable_pin_output_driver(GPIO_PIN_EXAMPLE);
00258 
00259   // Toggle the example GPIO pin at high speed in a loop.
00260   while (1)
00261   {
00262     // Explicit loop unrolling allowing consecutive ST.W instructions without
00263     // loop overhead if compiler optimization is activated, except every 128
00264     // ST.W for the while loop.
00265 #define INSERT_GPIO_LOCAL_TGL_GPIO_PIN(idx, pin) \
00266     gpio_local_tgl_gpio_pin(pin);
00267     MREPEAT(128, INSERT_GPIO_LOCAL_TGL_GPIO_PIN, GPIO_PIN_EXAMPLE)
00268 #undef INSERT_GPIO_LOCAL_TGL_GPIO_PIN
00269   }
00270 }


Generated on Fri Feb 19 02:25:03 2010 for AVR32 - GPIO Driver - Local Bus Interface by  doxygen 1.5.5