scif_uc3l.h File Reference


Detailed Description

System Control InterFace(SCIF) driver interface.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file scif_uc3l.h.

#include "compiler.h"

Go to the source code of this file.

Data Structures

struct  scif_dfll_closedloop_conf_t
 DFLL closed-loop mode settings. More...
struct  scif_dfll_openloop_conf_t
 DFLL open-loop mode settings. More...
struct  scif_dfll_ssg_conf_t
 DFLL SSG settings. More...
struct  scif_gclk_opt_t
 Generic clock generation settings. More...
struct  scif_osc32_opt_t
 OSC32 startup options. More...
struct  scif_osc_opt_t
 OSC0/OSC1 startup options. More...

DFLL Control Functions

#define scif_dfll0_closedloop_dither_gc_enable(pgc_conf)   scif_dfll0_ssg_gc_enable(pgc_conf)
 Configure and enable the generic clock used by the closed-loop mode dithering stage and by the SSG.
#define scif_dfll0_closedloop_mainref_gc_enable(pgc_conf)   scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_REF, pgc_conf)
 Configure and enable the closed-loop mode main reference generic clock.
#define scif_dfll0_ssg_gc_enable(pgc_conf)   scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_SSG, pgc_conf)
 Configure and enable the SSG reference generic clock.
long int scif_dfll0_closedloop_configure_and_start (const scif_gclk_opt_t *gc_dfllif_ref_opt, unsigned long long target_freq_hz, bool enable_ssg)
 Depending on the target frequency, compute the DFLL configuration parameters and start the DFLL0 in closed loop mode.
long int scif_dfll0_closedloop_start (const scif_dfll_closedloop_conf_t *pdfllconfig)
 Configure and start the DFLL0 in closed loop mode.
long int scif_dfll0_openloop_start (const scif_dfll_openloop_conf_t *pdfllconfig)
 Configure and start the DFLL0 in open loop mode.
long int scif_dfll0_openloop_start_auto (unsigned long TargetFreqkHz)
 Automatic configuration and start of the DFLL0 in open loop mode.
long int scif_dfll0_openloop_stop (void)
 Stop the DFLL0 in open loop mode.
long int scif_dfll0_openloop_updatefreq (const scif_dfll_openloop_conf_t *pdfllconfig)
 Update the frequency of the DFLL0 in open loop mode.
long int scif_dfll0_openloop_updatefreq_auto (unsigned long TargetFreq)
 Automatic configuration to update the frequency of the DFLL0 in open loop mode.
long int scif_dfll0_ssg_enable (scif_dfll_ssg_conf_t *pssg_conf)
 Configure and enable the SSG.

Defines

#define AVR32_SCIF_OSCCTRL0_OSCEN_DISABLE   0x00000000
#define AVR32_SCIF_OSCCTRL0_OSCEN_ENABLE   0x00000001
#define AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE   0x00000000
#define AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE   0x00000001
#define SCIF_DFLL_MAXFREQ_HZ   150000000L
#define SCIF_DFLL_MAXFREQ_KHZ   150000
 The max DFLL output frequency.
#define SCIF_DFLL_MINFREQ_HZ   20000000L
#define SCIF_DFLL_MINFREQ_KHZ   20000
 The min DFLL output frequency.
#define SCIF_EXT_CRYSTAL_MAX_FREQ_HZ   20000000
#define SCIF_EXT_CRYSTAL_MIN_FREQ_HZ   4000000
 Device-specific data.
#define SCIF_NOT_SUPPORTED   (-10000)
 Define "not supported" for the chosen implementation.
#define SCIF_OSC32_FREQ_HZ   32768
 The OSC32 frequency.
#define SCIF_POLL_TIMEOUT   100000
 The timeguard used for polling in ticks.
#define SCIF_RC120M_FREQ_HZ   120000000L
 The RC120M frequency.
#define SCIF_RC120M_FREQ_KHZ   120000
#define SCIF_RC32K_FREQ_HZ   32768
 The RC32K slow clock frequency.
#define SCIF_RC32K_FREQ_KHZ   (SCIF_RC32K_FREQ_HZ/100)
#define SCIF_SLOWCLOCK_FREQ_HZ   AVR32_SCIF_RCOSC_FREQUENCY
 The RCSYS slow clock frequency.
#define SCIF_SLOWCLOCK_FREQ_KHZ   (SCIF_SLOWCLOCK_FREQ_HZ/100)
#define SCIF_UNLOCK(reg)   (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg))
 Unlock SCIF register macro.

Enumerations

enum  scif_gcctrl_oscsel_t {
  SCIF_GCCTRL_SLOWCLOCK = AVR32_SCIF_GC_USES_CLK_SLOW, SCIF_GCCTRL_OSC32K = AVR32_SCIF_GC_USES_CLK_32, SCIF_GCCTRL_OSC0 = AVR32_SCIF_GC_USES_OSC0, SCIF_GCCTRL_OSC1 = AVR32_SCIF_GC_USES_OSC1,
  SCIF_GCCTRL_PLL0 = AVR32_SCIF_GC_USES_PLL0, SCIF_GCCTRL_PLL1 = AVR32_SCIF_GC_USES_PLL1, SCIF_GCCTRL_RC8M = AVR32_SCIF_GC_USES_RCOSC8, SCIF_GCCTRL_CPUCLOCK = AVR32_SCIF_GC_USES_CLK_CPU,
  SCIF_GCCTRL_HSBCLOCK = AVR32_SCIF_GC_USES_CLK_HSB, SCIF_GCCTRL_PBACLOCK = AVR32_SCIF_GC_USES_CLK_PBA, SCIF_GCCTRL_PBBCLOCK = AVR32_SCIF_GC_USES_CLK_PBB, SCIF_GCCTRL_OSCSEL_INVALID,
  SCIF_GCCTRL_SLOWCLOCK = AVR32_SCIF_GC_USES_CLK_SLOW, SCIF_GCCTRL_OSC32K = AVR32_SCIF_GC_USES_CLK_32, SCIF_GCCTRL_DFLL0 = AVR32_SCIF_GC_USES_DFLL0, SCIF_GCCTRL_OSC0 = AVR32_SCIF_GC_USES_OSC0,
  SCIF_GCCTRL_RC120M = AVR32_SCIF_GC_USES_RC120M, SCIF_GCCTRL_CPUCLOCK = AVR32_SCIF_GC_USES_CLK_CPU, SCIF_GCCTRL_HSBCLOCK = AVR32_SCIF_GC_USES_CLK_HSB, SCIF_GCCTRL_PBACLOCK = AVR32_SCIF_GC_USES_CLK_PBA,
  SCIF_GCCTRL_PBBCLOCK = AVR32_SCIF_GC_USES_CLK_PBB, SCIF_GCCTRL_RC32K = AVR32_SCIF_GC_USES_RC32K, SCIF_GCCTRL_CRIPOSC = AVR32_SCIF_GC_USES_CRIPOSC, SCIF_GCCTRL_CLK1K = AVR32_SCIF_GC_USES_CLK_1K,
  SCIF_GCCTRL_OSCSEL_INVALID
}
 The different clock source for the generic clocks. More...
enum  scif_osc_mode_t {
  SCIF_OSC_MODE_EXT_CLK = 0, SCIF_OSC_MODE_2PIN_CRYSTAL = 1, SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR = 2, SCIF_OSC_MODE_EXT_CLK = 0,
  SCIF_OSC_MODE_2PIN_CRYSTAL = 1, SCIF_OSC_MODE_NOT_SUPPORTED_1 = 2, SCIF_OSC_MODE_NOT_SUPPORTED_2 = 3, SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR = 4,
  SCIF_OSC_MODE_NOT_SUPPORTED_3 = 5, SCIF_OSC_MODE_NOT_SUPPORTED_4 = 6, SCIF_OSC_MODE_NOT_SUPPORTED_5 = 7
}
 The different oscillator modes. More...
enum  scif_osc_t { SCIF_OSC0 = 0, SCIF_OSC1 = 1, SCIF_OSC0 = 0, SCIF_OSC1 = 1 }
 The different oscillators. More...

Functions

Interrupt Functions
__inline__ void scif_clear_interrupts_status (unsigned long mask)
 Clear raised interrupts from the SCIF.
__inline__ void scif_disable_interrupts (unsigned long mask)
 Disable SCIF interrupts.
__inline__ void scif_enable_interrupts (unsigned long mask)
 Enable SCIF interrupts.
__inline__ unsigned long scif_get_enabled_interrupts (void)
 Read the SCIF currently enabled interrupts.
__inline__ unsigned long scif_get_interrupts_status (void)
 Read the interrupt status of the SCIF.
OSC0/OSC1 Functions
long int scif_configure_osc_crystalmode (scif_osc_t osc, unsigned int fcrystal)
 Configure an oscillator in crystal mode.
long int scif_enable_osc (scif_osc_t osc, unsigned int startup, bool wait_for_ready)
 Enable an oscillator with a given startup time.
bool scif_is_osc_ready (scif_osc_t osc)
 Is an oscillator stable and ready to be used as clock source?
long int scif_start_osc (scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready)
 Configure and start an OSC0/OSC1 oscillator.
long int scif_stop_osc (scif_osc_t osc)
 Stop an oscillator.
32kHz internal RCosc (RC32K) Functions
void scif_disable_rc32out (void)
 Unforce the RC32 signal from being output on the dedicated pin (PB04 on revB, PA20 on revC and later).
void scif_start_rc32k (void)
 Start the 32kHz internal RCosc (RC32K) clock.
void scif_stop_rc32k (void)
 Stop the 32kHz internal RCosc (RC32K) clock.
Generic Clock Functions
long int scif_gc_enable (unsigned int gclk)
 Enable a generic clock.
long int scif_gc_setup (unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor)
 Setup a generic clock.
long int scif_start_gclk (unsigned int gclk, const scif_gclk_opt_t *opt)
 Setup and start a generic clock.
long int scif_stop_gclk (unsigned int gclk)
 Stop a generic clock.
Power and Clocks Status Functions
__inline__ unsigned long scif_get_pclk_status (void)
 Read the Power and Clocks Status of the SCIF.
OSC32 Functions
__inline__ bool scif_is_osc32_ready ()
 Is OSC32 stable and ready to be used as clock source?
__inline__ void scif_osc32_1kout_dis ()
 Disable the 1kHz output of the OSC32 oscillator.
__inline__ void scif_osc32_1kout_ena ()
 Enable the 1kHz output of the OSC32 oscillator.
__inline__ void scif_osc32_32kout_dis ()
 Disable the 32kHz output of the OSC32 oscillator.
__inline__ void scif_osc32_32kout_ena ()
 Enable the 32kHz output of the OSC32 oscillator.
long int scif_start_osc32 (const scif_osc32_opt_t *opt, bool wait_for_ready)
 Configure and start the OSC32 oscillator.
long int scif_stop_osc32 ()
 Stop the OSC32 oscillator.
Miscellaneous Functions
long int scif_pclksr_statushigh_wait (unsigned long statusMask)
 Wait for a status high in the Power and Clocks status register.
120MHz RCosc Functions
void scif_start_rc120M (void)
 Start the 120MHz internal RCosc (RC120M) clock.
void scif_stop_rc120M (void)
 Stop the 120MHz internal RCosc (RC120M) clock.


Define Documentation

#define AVR32_SCIF_OSCCTRL0_OSCEN_DISABLE   0x00000000

Definition at line 62 of file scif_uc3l.h.

#define AVR32_SCIF_OSCCTRL0_OSCEN_ENABLE   0x00000001

Definition at line 61 of file scif_uc3l.h.

#define AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE   0x00000000

Definition at line 64 of file scif_uc3l.h.

Referenced by scif_stop_osc32().

#define AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE   0x00000001

Definition at line 63 of file scif_uc3l.h.

#define scif_dfll0_closedloop_dither_gc_enable ( pgc_conf   )     scif_dfll0_ssg_gc_enable(pgc_conf)

Configure and enable the generic clock used by the closed-loop mode dithering stage and by the SSG.

Parameters:
pgc_conf The settings for the generic clock [INPUT]
Returns:
Status.
Return values:
0 Dithering & SSG reference generic clock configured and started successfully.
<0 Error.

Definition at line 597 of file scif_uc3l.h.

#define scif_dfll0_closedloop_mainref_gc_enable ( pgc_conf   )     scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_REF, pgc_conf)

Configure and enable the closed-loop mode main reference generic clock.

Parameters:
pgc_conf The settings for the generic clock [INPUT]
Returns:
Status.
Return values:
0 Main reference generic clock configured and started successfully.
<0 Error.

Definition at line 554 of file scif_uc3l.h.

Referenced by local_start_dfll_clock(), and scif_dfll0_closedloop_configure_and_start().

#define scif_dfll0_ssg_gc_enable ( pgc_conf   )     scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_SSG, pgc_conf)

Configure and enable the SSG reference generic clock.

Note:
The frequency of the SSG reference clock should be higher than the CLK_DFLLIF_REF to ensure that the DFLLIF can lock.
Parameters:
pgc_conf The settings for the generic clock [INPUT]
Returns:
Status.
Return values:
0 SSG Generic clock configured and started successfully.
<0 Error.

Definition at line 532 of file scif_uc3l.h.

#define SCIF_DFLL_MAXFREQ_HZ   150000000L

#define SCIF_DFLL_MAXFREQ_KHZ   150000

The max DFLL output frequency.

Definition at line 97 of file scif_uc3l.h.

Referenced by scif_dfll0_openloop_start_auto().

#define SCIF_DFLL_MINFREQ_HZ   20000000L

#define SCIF_DFLL_MINFREQ_KHZ   20000

The min DFLL output frequency.

Definition at line 93 of file scif_uc3l.h.

Referenced by scif_dfll0_openloop_start_auto().

#define SCIF_EXT_CRYSTAL_MAX_FREQ_HZ   20000000

Definition at line 72 of file scif_uc3l.h.

#define SCIF_EXT_CRYSTAL_MIN_FREQ_HZ   4000000

Device-specific data.

< External crystal/clock min frequency (in Herz) External crystal/clock max frequency (in Herz)

Definition at line 70 of file scif_uc3l.h.

#define SCIF_NOT_SUPPORTED   (-10000)

Define "not supported" for the chosen implementation.

Definition at line 119 of file scif_uc3l.h.

#define SCIF_OSC32_FREQ_HZ   32768

The OSC32 frequency.

Definition at line 113 of file scif_uc3l.h.

#define SCIF_POLL_TIMEOUT   100000

The timeguard used for polling in ticks.

Definition at line 116 of file scif_uc3l.h.

#define SCIF_RC120M_FREQ_HZ   120000000L

The RC120M frequency.

Definition at line 109 of file scif_uc3l.h.

Referenced by scif_dfll0_closedloop_configure_and_start().

#define SCIF_RC120M_FREQ_KHZ   120000

Definition at line 110 of file scif_uc3l.h.

#define SCIF_RC32K_FREQ_HZ   32768

The RC32K slow clock frequency.

Definition at line 105 of file scif_uc3l.h.

Referenced by scif_dfll0_closedloop_configure_and_start().

#define SCIF_RC32K_FREQ_KHZ   (SCIF_RC32K_FREQ_HZ/100)

Definition at line 106 of file scif_uc3l.h.

#define SCIF_SLOWCLOCK_FREQ_HZ   AVR32_SCIF_RCOSC_FREQUENCY

The RCSYS slow clock frequency.

Definition at line 101 of file scif_uc3l.h.

Referenced by local_start_dfll_clock(), and scif_dfll0_closedloop_configure_and_start().

#define SCIF_SLOWCLOCK_FREQ_KHZ   (SCIF_SLOWCLOCK_FREQ_HZ/100)

Definition at line 102 of file scif_uc3l.h.

#define SCIF_UNLOCK ( reg   )     (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg))

Unlock SCIF register macro.

Definition at line 229 of file scif_uc3l.h.


Enumeration Type Documentation

The different clock source for the generic clocks.

Enumerator:
SCIF_GCCTRL_SLOWCLOCK 
SCIF_GCCTRL_OSC32K 
SCIF_GCCTRL_OSC0 
SCIF_GCCTRL_OSC1 
SCIF_GCCTRL_PLL0 
SCIF_GCCTRL_PLL1 
SCIF_GCCTRL_RC8M 
SCIF_GCCTRL_CPUCLOCK 
SCIF_GCCTRL_HSBCLOCK 
SCIF_GCCTRL_PBACLOCK 
SCIF_GCCTRL_PBBCLOCK 
SCIF_GCCTRL_OSCSEL_INVALID 
SCIF_GCCTRL_SLOWCLOCK 
SCIF_GCCTRL_OSC32K 
SCIF_GCCTRL_DFLL0 
SCIF_GCCTRL_OSC0 
SCIF_GCCTRL_RC120M 
SCIF_GCCTRL_CPUCLOCK 
SCIF_GCCTRL_HSBCLOCK 
SCIF_GCCTRL_PBACLOCK 
SCIF_GCCTRL_PBBCLOCK 
SCIF_GCCTRL_RC32K 
SCIF_GCCTRL_CRIPOSC 
SCIF_GCCTRL_CLK1K 
SCIF_GCCTRL_OSCSEL_INVALID 

Definition at line 75 of file scif_uc3l.h.

00076 {
00077   SCIF_GCCTRL_SLOWCLOCK  = AVR32_SCIF_GC_USES_CLK_SLOW,
00078   SCIF_GCCTRL_OSC32K  = AVR32_SCIF_GC_USES_CLK_32,
00079   SCIF_GCCTRL_DFLL0  = AVR32_SCIF_GC_USES_DFLL0,
00080   SCIF_GCCTRL_OSC0  = AVR32_SCIF_GC_USES_OSC0,
00081   SCIF_GCCTRL_RC120M  = AVR32_SCIF_GC_USES_RC120M,
00082   SCIF_GCCTRL_CPUCLOCK  = AVR32_SCIF_GC_USES_CLK_CPU,
00083   SCIF_GCCTRL_HSBCLOCK  = AVR32_SCIF_GC_USES_CLK_HSB,
00084   SCIF_GCCTRL_PBACLOCK  = AVR32_SCIF_GC_USES_CLK_PBA,
00085   SCIF_GCCTRL_PBBCLOCK  = AVR32_SCIF_GC_USES_CLK_PBB,
00086   SCIF_GCCTRL_RC32K  = AVR32_SCIF_GC_USES_RC32K,
00087   SCIF_GCCTRL_CRIPOSC  = AVR32_SCIF_GC_USES_CRIPOSC,
00088   SCIF_GCCTRL_CLK1K  = AVR32_SCIF_GC_USES_CLK_1K,
00089   SCIF_GCCTRL_OSCSEL_INVALID
00090 } scif_gcctrl_oscsel_t;

The different oscillator modes.

Enumerator:
SCIF_OSC_MODE_EXT_CLK 
SCIF_OSC_MODE_2PIN_CRYSTAL 
SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR 
SCIF_OSC_MODE_EXT_CLK 
SCIF_OSC_MODE_2PIN_CRYSTAL 
SCIF_OSC_MODE_NOT_SUPPORTED_1 
SCIF_OSC_MODE_NOT_SUPPORTED_2 
SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR 
SCIF_OSC_MODE_NOT_SUPPORTED_3 
SCIF_OSC_MODE_NOT_SUPPORTED_4 
SCIF_OSC_MODE_NOT_SUPPORTED_5 

Definition at line 130 of file scif_uc3l.h.

00131 {
00132   SCIF_OSC_MODE_EXT_CLK = 0,            // For both OSC0 & OSC32
00133   SCIF_OSC_MODE_2PIN_CRYSTAL = 1,       // For both OSC0 and OSC32
00134   SCIF_OSC_MODE_NOT_SUPPORTED_1 = 2,
00135   SCIF_OSC_MODE_NOT_SUPPORTED_2 = 3,
00136   SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR = 4, // For OSC32 only
00137   SCIF_OSC_MODE_NOT_SUPPORTED_3 = 5,
00138   SCIF_OSC_MODE_NOT_SUPPORTED_4 = 6,
00139   SCIF_OSC_MODE_NOT_SUPPORTED_5 = 7
00140 } scif_osc_mode_t;

enum scif_osc_t

The different oscillators.

Enumerator:
SCIF_OSC0 
SCIF_OSC1 
SCIF_OSC0 
SCIF_OSC1 

Definition at line 123 of file scif_uc3l.h.

00124 {
00125   SCIF_OSC0  = 0,
00126   SCIF_OSC1  = 1
00127 } scif_osc_t;


Function Documentation

__inline__ void scif_clear_interrupts_status ( unsigned long  mask  ) 

Clear raised interrupts from the SCIF.

Parameters:
mask The interrupts to clear.

Definition at line 290 of file scif_uc3l.h.

00291 {
00292   AVR32_SCIF.icr = mask;
00293 }

long int scif_configure_osc_crystalmode ( scif_osc_t  osc,
unsigned int  fcrystal 
)

Configure an oscillator in crystal mode.

Parameters:
osc The oscillator to configure [INPUT]
fcrystal Crystal frequency (Hz) [INPUT]
Returns:
Status.
Return values:
0 Oscillator successfully configured.
<0 Error configuring the oscillator.

Definition at line 228 of file scif_uc3c.c.

References u_avr32_scif_oscctrl_t::OSCCTRL, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, SCIF_OSC0, SCIF_OSC1, SCIF_OSC_MODE_2PIN_CRYSTAL, and SCIF_UNLOCK.

00229 {
00230   u_avr32_scif_oscctrl_t   u_avr32_scif_oscctrl;
00231   
00232   if (osc == SCIF_OSC0)
00233   {    
00234     // Read Register
00235     u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0] = AVR32_SCIF.OSCCTRL[SCIF_OSC0] ;    
00236     // Modify : Configure the oscillator mode to crystal and set the gain according to the
00237     // cyrstal frequency.
00238     u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
00239     u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0].gain = (fcrystal <  900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
00240                                                    (fcrystal < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
00241                                                    (fcrystal < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
00242                                                                           AVR32_SCIF_OSCCTRL0_GAIN_G3;
00243     AVR32_ENTER_CRITICAL_REGION( );
00244     // Unlock the write-protected OSCCTRL0 register
00245     SCIF_UNLOCK(AVR32_SCIF_OSCCTRL);
00246     // Write Back
00247     AVR32_SCIF.OSCCTRL[SCIF_OSC0] = u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC0];
00248     AVR32_LEAVE_CRITICAL_REGION( );
00249   }
00250   else
00251   { 
00252     // Read Register
00253     u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1] = AVR32_SCIF.OSCCTRL[SCIF_OSC1] ;    
00254     // Modify : Configure the oscillator mode to crystal and set the gain according to the
00255     // cyrstal frequency.
00256     u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1].mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
00257     u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1].gain = (fcrystal <  900000) ? AVR32_SCIF_OSCCTRL1_GAIN_G0 :
00258                                                    (fcrystal < 3000000) ? AVR32_SCIF_OSCCTRL1_GAIN_G1 :
00259                                                    (fcrystal < 8000000) ? AVR32_SCIF_OSCCTRL1_GAIN_G2 :
00260                                                                           AVR32_SCIF_OSCCTRL1_GAIN_G3;
00261     AVR32_ENTER_CRITICAL_REGION( );
00262     // Unlock the write-protected OSCCTRL1 register
00263     SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4);
00264     // Write Back
00265     AVR32_SCIF.OSCCTRL[SCIF_OSC1] = u_avr32_scif_oscctrl.OSCCTRL[SCIF_OSC1];
00266     AVR32_LEAVE_CRITICAL_REGION( );
00267   }
00268 
00269   return PASS;
00270 }

long int scif_dfll0_closedloop_configure_and_start ( const scif_gclk_opt_t gc_dfllif_ref_opt,
unsigned long long  target_freq_hz,
bool  enable_ssg 
)

Depending on the target frequency, compute the DFLL configuration parameters and start the DFLL0 in closed loop mode.

Note:
Configures and enables the generic clock CLK_DFLLIF_REF to serve as the main reference.

This function only supports the following source clocks for the CLK_DFLLIF_REF generic clock: SCIF_GCCTRL_SLOWCLOCK (aka RCSYS), SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC32K, SCIF_GCCTRL_OSC0, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_CLK1K.

Parameters:
gc_dfllif_ref_opt The settings for the CLK_DFLLIF_REF generic clock [INPUT]
target_freq_hz The target frequency (in Hz) [INPUT]
enable_ssg Enable/disable the SSG feature [INPUT]
Returns:
Status.
Return values:
0 DFLL0 configured and started successfully.
<0 Error.

Definition at line 615 of file scif_uc3l.c.

References scif_gclk_opt_t::clock_source, scif_dfll_closedloop_conf_t::coarse, scif_dfll_closedloop_conf_t::coarsemaxstep, scif_gclk_opt_t::diven, scif_gclk_opt_t::divider, scif_gclk_opt_t::extosc_f, scif_dfll_closedloop_conf_t::finemaxstep, scif_dfll_closedloop_conf_t::fmul, scif_dfll0_closedloop_mainref_gc_enable, scif_dfll0_closedloop_start(), SCIF_DFLL_MAXFREQ_HZ, SCIF_DFLL_MINFREQ_HZ, SCIF_GCCTRL_CLK1K, SCIF_GCCTRL_OSC0, SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_RC32K, SCIF_GCCTRL_SLOWCLOCK, SCIF_RC120M_FREQ_HZ, SCIF_RC32K_FREQ_HZ, and SCIF_SLOWCLOCK_FREQ_HZ.

00618 {
00619   scif_dfll_closedloop_conf_t DfllConfig;
00620   int gc_source_clock_freq_hz;
00621 
00622   // This function only supports the following source clocks for the CLK_DFLLIF_REF generic clock:
00623   // SCIF_GCCTRL_SLOWCLOCK (aka RCSYS), SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC32K,
00624   // SCIF_GCCTRL_OSC0, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_CLK1K.
00625   if(SCIF_GCCTRL_SLOWCLOCK == gc_dfllif_ref_opt->clock_source)
00626     gc_source_clock_freq_hz = SCIF_SLOWCLOCK_FREQ_HZ;
00627   else if((SCIF_GCCTRL_OSC32K == gc_dfllif_ref_opt->clock_source) || (SCIF_GCCTRL_RC32K == gc_dfllif_ref_opt->clock_source))
00628     gc_source_clock_freq_hz = SCIF_RC32K_FREQ_HZ;
00629   else if(SCIF_GCCTRL_OSC0 == gc_dfllif_ref_opt->clock_source)
00630     gc_source_clock_freq_hz = gc_dfllif_ref_opt->extosc_f;
00631   else if(SCIF_GCCTRL_RC120M == gc_dfllif_ref_opt->clock_source)
00632     gc_source_clock_freq_hz = SCIF_RC120M_FREQ_HZ;
00633   else if(SCIF_GCCTRL_CLK1K == gc_dfllif_ref_opt->clock_source)
00634     gc_source_clock_freq_hz = 1000;
00635   else
00636     return -1;
00637 
00638   // Configure and start the DFLL main reference generic clock (CLK_DFLLIF_REF).
00639   if(scif_dfll0_closedloop_mainref_gc_enable(gc_dfllif_ref_opt))
00640     return(-1);
00641 
00642   // Configure the DFLL.
00643   // The coarse value (= (dfll_f - SCIF_DFLL_MINFREQ_KHZ)*255/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ))
00644   DfllConfig.coarse = ((unsigned long long)(target_freq_hz - SCIF_DFLL_MINFREQ_HZ)*255)/(SCIF_DFLL_MAXFREQ_HZ - SCIF_DFLL_MINFREQ_HZ);
00645 
00646   // The fmul value (= (fDFLL*2^16)/fref, with fref being the frequency of the
00647   // DFLL main reference generic clock)
00648   if(0 == gc_dfllif_ref_opt->diven)
00649     DfllConfig.fmul = ((unsigned long long)target_freq_hz<<16)/gc_source_clock_freq_hz;
00650   else
00651     DfllConfig.fmul = ((((unsigned long long)target_freq_hz<<16)/gc_source_clock_freq_hz)<<1)*(1+gc_dfllif_ref_opt->divider);
00652 
00653   // The fine and coarse maxstep values
00654 #if (defined(__GNUC__) \
00655       && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00656   ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00657       && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00658       // UC3L revC and higher
00659   DfllConfig.finemaxstep = 0x0000004;
00660   DfllConfig.coarsemaxstep = 0x0000004;
00661 #else
00662       // UC3L revB
00663       //+ Errata UC3L revB: 35.2.7 SCIF.12 DFLLIF indicates coarse lock too early
00664       //+ The DFLLIF might indicate coarse lock too early, the DFLL will lose
00665       //+ coarse lock and regain it later.
00666       //+ Fix/Workaround
00667       //+ Use max step size (DFLL0MAXSTEP.MAXSTEP) of 4 or higher.
00668   DfllConfig.maxstep = 0x0040004;
00669 #endif
00670 
00671   // Dithering disabled.
00672       //+ Errata UC3L revB: 35.2.7 SCIF.13 DFLLIF dithering does not work
00673       //+ The DFLLIF dithering does not work.
00674       //+ Fix/Workaround
00675       //+ None.
00676 
00677   // Configure and start the DFLL0 in closed loop mode.
00678   if(scif_dfll0_closedloop_start(&DfllConfig))
00679     return -1;
00680 
00681   // TODO: Future implementation note: add use of the generic clock CLK_DFLLIF_DITHER
00682   // as a reference for the SSG feature.
00683   if(TRUE == enable_ssg)
00684   {
00685   ;
00686   }
00687   return PASS;
00688 }

long int scif_dfll0_closedloop_start ( const scif_dfll_closedloop_conf_t pdfllconfig  ) 

Configure and start the DFLL0 in closed loop mode.

Note:
The main reference generic clock must have previously been started.
Parameters:
pdfllconfig The DFLL parameters in closed loop mode [INPUT]
Returns:
Status.
Return values:
0 DFLL0 configured and started successfully.
<0 Error.

Definition at line 520 of file scif_uc3l.c.

References scif_dfll_closedloop_conf_t::coarse, scif_dfll_closedloop_conf_t::coarsemaxstep, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_dfll_closedloop_conf_t::finemaxstep, scif_dfll_closedloop_conf_t::fmul, SCIF_DFLL0_MODE_CLOSEDLOOP, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

Referenced by local_start_dfll_clock(), and scif_dfll0_closedloop_configure_and_start().

00521 {
00522   u_avr32_scif_dfll0conf_t  u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00523 #if (defined(__GNUC__) \
00524       && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00525   ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00526       && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00527   volatile unsigned long    tempo;
00528 #endif
00529 
00530 
00531 #ifdef AVR32SFW_INPUT_CHECK
00532   if((pdfllconfig->coarse >> AVR32_SCIF_DFLL0CONF_COARSE_SIZE))
00533     return -1;
00534 #if (defined(__GNUC__) \
00535       && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00536   ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00537       && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00538       // UC3L revC and higher
00539   if( (pdfllconfig->finemaxstep >> AVR32_SCIF_DFLL0STEP_FSTEP_SIZE)
00540    || (pdfllconfig->coarsemaxstep >> AVR32_SCIF_DFLL0STEP_CSTEP_SIZE) )
00541     return -1;
00542 #else
00543       // UC3L revB
00544   if((pdfllconfig->maxstep >> AVR32_SCIF_DFLL0STEP_MAXSTEP_SIZE))
00545     return -1;
00546 #endif
00547 #endif
00548 
00549   // Enable the DFLL0: DFLL0CONF.EN=1
00550   u_avr32_scif_dfll0conf.DFLL0CONF.en = ENABLE;
00551   AVR32_ENTER_CRITICAL_REGION( );
00552   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00553   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00554   AVR32_LEAVE_CRITICAL_REGION( );
00555 
00556   // Wait for PCLKSR.DFLL0RDY is high
00557   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00558     return -1;
00559     
00560   // Set the maxstep values
00561 #if (defined(__GNUC__) \
00562       && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00563   ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00564       && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00565       // UC3L revC and higher
00566   tempo = ((pdfllconfig->coarsemaxstep << AVR32_SCIF_DFLL0STEP_CSTEP_OFFSET)&AVR32_SCIF_DFLL0STEP_CSTEP_MASK)
00567           | ((pdfllconfig->finemaxstep << AVR32_SCIF_DFLL0STEP_FSTEP_OFFSET)&AVR32_SCIF_DFLL0STEP_FSTEP_MASK);
00568   AVR32_ENTER_CRITICAL_REGION( );
00569   SCIF_UNLOCK(AVR32_SCIF_DFLL0STEP);
00570   AVR32_SCIF.dfll0step = tempo;
00571   AVR32_LEAVE_CRITICAL_REGION( );
00572 #else
00573       // UC3L revB
00574   AVR32_ENTER_CRITICAL_REGION( );
00575   SCIF_UNLOCK(AVR32_SCIF_DFLL0STEP);
00576   AVR32_SCIF.dfll0step = (pdfllconfig->maxstep << AVR32_SCIF_DFLL0STEP_MAXSTEP_OFFSET)&AVR32_SCIF_DFLL0STEP_MAXSTEP_MASK;
00577   AVR32_LEAVE_CRITICAL_REGION( );
00578 #endif
00579   
00580   // Wait for PCLKSR.DFLL0RDY is high
00581   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00582     return -1;
00583   
00584   // Set the fmul
00585   AVR32_ENTER_CRITICAL_REGION( );
00586   SCIF_UNLOCK(AVR32_SCIF_DFLL0FMUL);
00587   AVR32_SCIF.dfll0fmul = (pdfllconfig->fmul << AVR32_SCIF_DFLL0FMUL_FMUL_OFFSET)&AVR32_SCIF_DFLL0FMUL_FMUL_MASK;
00588   AVR32_LEAVE_CRITICAL_REGION( );
00589   
00590   // Wait for PCLKSR.DFLL0RDY is high
00591   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00592     return -1;
00593 
00594   // Set the DFLL0 to operate in closed-loop mode: DFLL0CONF.MODE=1
00595   u_avr32_scif_dfll0conf.DFLL0CONF.mode = SCIF_DFLL0_MODE_CLOSEDLOOP;
00596   u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse;
00597   AVR32_ENTER_CRITICAL_REGION( );
00598   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00599   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00600   AVR32_LEAVE_CRITICAL_REGION( );
00601 
00602   // Wait for PCLKSR.DFLL0RDY is high
00603   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00604     return -1;
00605     
00606   // Wait until the DFLL is locked on Fine value, and is ready to be selected as
00607   // clock source with a highly accurate output clock.
00608   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0LOCKF_MASK))
00609     return -1;
00610     
00611   return PASS;
00612 }

long int scif_dfll0_openloop_start ( const scif_dfll_openloop_conf_t pdfllconfig  ) 

Configure and start the DFLL0 in open loop mode.

Parameters:
pdfllconfig The DFLL parameters in open loop mode [INPUT]
Returns:
Status.
Return values:
0 DFLL0 configured and started successfully.
<0 Error.

Definition at line 342 of file scif_uc3l.c.

References scif_dfll_openloop_conf_t::coarse, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_dfll_openloop_conf_t::fine, SCIF_DFLL0_MODE_OPENLOOP, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

Referenced by scif_dfll0_openloop_start_auto().

00343 {
00344   u_avr32_scif_dfll0conf_t  u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00345 
00346 
00347 #ifdef AVR32SFW_INPUT_CHECK
00348   if((pdfllconfig->fine >> AVR32_SCIF_DFLL0CONF_FINE_SIZE))
00349     return -1;
00350   if((pdfllconfig->coarse >> AVR32_SCIF_DFLL0CONF_COARSE_SIZE))
00351     return -1;
00352 #endif
00353 
00354   // Enable the DFLL0: DFLL0CONF.EN=1
00355   u_avr32_scif_dfll0conf.DFLL0CONF.en = ENABLE;
00356   AVR32_ENTER_CRITICAL_REGION( );
00357   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00358   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00359   AVR32_LEAVE_CRITICAL_REGION( );
00360   
00361   // Wait for PCLKSR.DFLL0RDY is high
00362   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00363     return -1;
00364 
00365   // Set the DFLL0 to operate in open mode: DFLL0CONF.MODE=0
00366   u_avr32_scif_dfll0conf.DFLL0CONF.mode = SCIF_DFLL0_MODE_OPENLOOP;
00367   AVR32_ENTER_CRITICAL_REGION( );
00368   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00369   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00370   AVR32_LEAVE_CRITICAL_REGION( );
00371   
00372   // Wait for PCLKSR.DFLL0RDY is high
00373   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00374     return -1;
00375   
00376   // Write DFLL0CONF.COARSE & DFLL0CONF.FINE
00377   u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse;
00378   u_avr32_scif_dfll0conf.DFLL0CONF.fine = pdfllconfig->fine;
00379   AVR32_ENTER_CRITICAL_REGION( );
00380   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00381   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00382   AVR32_LEAVE_CRITICAL_REGION( );
00383 
00384   // Wait for PCLKSR.DFLL0RDY is high
00385   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00386     return -1;
00387   
00388   return PASS;
00389 }

long int scif_dfll0_openloop_start_auto ( unsigned long  TargetFreqkHz  ) 

Automatic configuration and start of the DFLL0 in open loop mode.

Parameters:
TargetFreqkHz The DFLL target frequency (in kHz) [INPUT]
Returns:
Status.
Return values:
0 DFLL0 configured and started successfully.
<0 Error.

Definition at line 395 of file scif_uc3l.c.

References scif_dfll_openloop_conf_t::coarse, scif_dfll_openloop_conf_t::fine, scif_dfll0_openloop_start(), SCIF_DFLL_COARSE_MAX, SCIF_DFLL_FINE_HALF, SCIF_DFLL_FINE_MAX, SCIF_DFLL_MAXFREQ_KHZ, and SCIF_DFLL_MINFREQ_KHZ.

00396 {
00397   scif_dfll_openloop_conf_t Dfll0Conf;
00398   unsigned long             Coarse;
00399   unsigned long             Fine;
00400   unsigned long             CoarseFreq;
00401   unsigned long             DeltaFreq;
00402 
00403 
00404 #ifdef AVR32SFW_INPUT_CHECK
00405   if((TargetFreqkHz < SCIF_DFLL_MINFREQ_KHZ) || (TargetFreqkHz > SCIF_DFLL_MAXFREQ_KHZ))
00406     return -1;
00407 #endif
00408 
00409   //**
00410   //** Dynamically compute the COARSE and FINE values.
00411   //**
00412   // Fdfll = (Fmin+(Fmax-Fmin)*(COARSE/0xFF))*(1+X*(FINE-0x100)/0x1FF)=CoarseFreq*(1+X*(FINE-0x100)/0x1FF)
00413 
00414   // Compute the COARSE value.
00415   Coarse = ((TargetFreqkHz - SCIF_DFLL_MINFREQ_KHZ)*SCIF_DFLL_COARSE_MAX)/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ);
00416   // Compute the COARSE DFLL frequency.
00417   CoarseFreq = SCIF_DFLL_MINFREQ_KHZ + (((SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ)/SCIF_DFLL_COARSE_MAX)*Coarse);
00418   // Compute the coarse error.
00419   DeltaFreq = TargetFreqkHz - CoarseFreq;
00420   // Compute the FINE value.
00421   // Fine = ((DeltaFreq*SCIF_DFLL_FINE_MAX)*10/CoarseFreq) + SCIF_DFLL_FINE_HALF;
00422   // Theorical equation don't work on silicon: the best was to use X=5/2 to
00423   // find FINE, then do FINE/4.
00424   Fine = ((DeltaFreq*SCIF_DFLL_FINE_MAX)*2/CoarseFreq*5) + SCIF_DFLL_FINE_HALF;
00425   Fine >>=2;
00426 
00427   Dfll0Conf.coarse = Coarse;
00428   Dfll0Conf.fine = Fine;
00429   return(scif_dfll0_openloop_start(&Dfll0Conf));
00430 }

long int scif_dfll0_openloop_stop ( void   ) 

Stop the DFLL0 in open loop mode.

Returns:
Status.
Return values:
0 DFLL0 successfully stopped.
<0 Error.

Definition at line 464 of file scif_uc3l.c.

References u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

00465 {
00466   u_avr32_scif_dfll0conf_t  u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00467   
00468     
00469   // Before disabling the DFLL, the output freq of the DFLL should be set to a 
00470   // minimum: set COARSE to 0x00.
00471 
00472   // Wait for PCLKSR.DFLL0RDY is high
00473   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00474     return -1;
00475   
00476   // Write DFLL0CONF.COARSE
00477   u_avr32_scif_dfll0conf.DFLL0CONF.coarse = 0;
00478   AVR32_ENTER_CRITICAL_REGION( );
00479   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00480   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00481   AVR32_LEAVE_CRITICAL_REGION( );
00482   
00483   // Wait for PCLKSR.DFLL0RDY is high
00484   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00485     return -1;
00486     
00487   // Disable the DFLL
00488   u_avr32_scif_dfll0conf.DFLL0CONF.en = 0;
00489   AVR32_ENTER_CRITICAL_REGION( );
00490   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00491   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00492   AVR32_LEAVE_CRITICAL_REGION( );
00493   
00494   // Wait for PCLKSR.DFLL0RDY is high
00495   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00496     return -1;
00497     
00498   return PASS;
00499 }

long int scif_dfll0_openloop_updatefreq ( const scif_dfll_openloop_conf_t pdfllconfig  ) 

Update the frequency of the DFLL0 in open loop mode.

Parameters:
pdfllconfig The DFLL parameters in open loop mode [INPUT]
Returns:
Status.
Return values:
0 DFLL0 frequency updated successfully.
<0 Error.

Definition at line 432 of file scif_uc3l.c.

References scif_dfll_openloop_conf_t::coarse, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_dfll_openloop_conf_t::fine, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

00433 {
00434   u_avr32_scif_dfll0conf_t  u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00435 
00436 
00437 #ifdef AVR32SFW_INPUT_CHECK
00438   if((pdfllconfig->fine >> AVR32_SCIF_DFLL0CONF_FINE_SIZE))
00439     return -1;
00440 #endif
00441 
00442   // It is assumed that the DFLL is enabled and operates in open-loop mode.
00443 
00444   // Wait for PCLKSR.DFLL0RDY is high
00445   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00446     return -1;
00447 
00448   // Write DFLL0CONF.COARSE & DFLL0CONF.FINE
00449   u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse;
00450   u_avr32_scif_dfll0conf.DFLL0CONF.fine = pdfllconfig->fine;
00451   AVR32_ENTER_CRITICAL_REGION( );
00452   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00453   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00454   AVR32_LEAVE_CRITICAL_REGION( );
00455 
00456   // Wait for PCLKSR.DFLL0RDY is high
00457   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00458     return -1;
00459 
00460   return PASS;
00461 }

long int scif_dfll0_openloop_updatefreq_auto ( unsigned long  TargetFreq  ) 

Automatic configuration to update the frequency of the DFLL0 in open loop mode.

Parameters:
TargetFreq The DFLL target frequency (in kHz) [INPUT]
Returns:
Status.
Return values:
0 DFLL0 frequency updated successfully.
<0 Error.

long int scif_dfll0_ssg_enable ( scif_dfll_ssg_conf_t pssg_conf  ) 

Configure and enable the SSG.

Note:
The SSG reference generic clock must have previously been enabled.
Parameters:
pssg_conf The settings for the SCIF.DFLL0SSG register [INPUT]
Returns:
Status.
Return values:
0 SSG Generic clock configured and started successfully.
<0 Error.

Definition at line 502 of file scif_uc3l.c.

References scif_dfll_ssg_conf_t::amplitude, u_avr32_scif_dfll0ssg_t::dfll0ssg, u_avr32_scif_dfll0ssg_t::DFLL0SSG, SCIF_UNLOCK, scif_dfll_ssg_conf_t::step_size, and scif_dfll_ssg_conf_t::use_random.

00503 {
00504   u_avr32_scif_dfll0ssg_t  u_avr32_scif_dfll0ssg = {AVR32_SCIF.dfll0ssg};
00505   
00506 
00507   u_avr32_scif_dfll0ssg.DFLL0SSG.en = ENABLE;
00508   u_avr32_scif_dfll0ssg.DFLL0SSG.prbs = pssg_conf->use_random;
00509   u_avr32_scif_dfll0ssg.DFLL0SSG.amplitude = pssg_conf->amplitude;
00510   u_avr32_scif_dfll0ssg.DFLL0SSG.stepsize = pssg_conf->step_size;
00511   AVR32_ENTER_CRITICAL_REGION( );
00512   SCIF_UNLOCK(AVR32_SCIF_DFLL0SSG);
00513   AVR32_SCIF.dfll0ssg = u_avr32_scif_dfll0ssg.dfll0ssg;
00514   AVR32_LEAVE_CRITICAL_REGION( );
00515 
00516   return PASS;
00517 }

__inline__ void scif_disable_interrupts ( unsigned long  mask  ) 

Disable SCIF interrupts.

Parameters:
mask the interrupts to disable.

Definition at line 254 of file scif_uc3l.h.

00255 {
00256   AVR32_SCIF.idr = mask;
00257 }

void scif_disable_rc32out ( void   ) 

Unforce the RC32 signal from being output on the dedicated pin (PB04 on revB, PA20 on revC and later).

Definition at line 751 of file scif_uc3l.c.

Referenced by scif_start_osc32().

00752 {
00753   unsigned long temp;
00754   AVR32_ENTER_CRITICAL_REGION( );
00755   temp = AVR32_PM.ppcr & (~AVR32_PM_PPCR_FRC32_MASK);
00756   // Unforce the RC32 signal from being output on the dedicated pin (PB04 on revB, PA20 on revC and later).
00757   AVR32_PM.unlock = 0xAA000000 | AVR32_PM_PPCR;
00758   AVR32_PM.ppcr = temp;
00759   AVR32_LEAVE_CRITICAL_REGION( );
00760 }

__inline__ void scif_enable_interrupts ( unsigned long  mask  ) 

Enable SCIF interrupts.

Parameters:
mask the interrupts to enable.

Definition at line 242 of file scif_uc3l.h.

00243 {
00244   AVR32_SCIF.ier = mask;
00245 }

long int scif_enable_osc ( scif_osc_t  osc,
unsigned int  startup,
bool  wait_for_ready 
)

Enable an oscillator with a given startup time.

Parameters:
osc The oscillator to configure [INPUT]
startup Oscillator startup time (one of AVR32_SCIF_OSCCTRLx_STARTUP_x_RCOSC) [INPUT]
wait_for_ready Wait for the oscillator to be stable before return [INPUT]
Returns:
Status.
Return values:
0 Oscillator successfully started
<0 Error starting the oscillator.

Definition at line 291 of file scif_uc3c.c.

References u_avr32_scif_oscctrl_t::OSCCTRL, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

00292 {
00293 
00294   u_avr32_scif_oscctrl_t   u_avr32_scif_oscctrl;
00295 
00296   // Read Register
00297   u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ;      
00298   // Modify: Configure the oscillator startup and enable the osc.
00299   u_avr32_scif_oscctrl.OSCCTRL[osc].startup = startup;
00300   u_avr32_scif_oscctrl.OSCCTRL[osc].oscen = ENABLE;
00301   AVR32_ENTER_CRITICAL_REGION( );
00302   // Unlock the write-protected OSCCTRL0 register
00303   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);
00304   // Write Back
00305   AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc];
00306   AVR32_LEAVE_CRITICAL_REGION( );
00307 
00308   if(true == wait_for_ready)
00309   {
00310     // Wait until OSC0 is stable and ready to be used.
00311     if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK))
00312       return -1;
00313   }
00314       
00315   return PASS;
00316 }

long int scif_gc_enable ( unsigned int  gclk  ) 

Enable a generic clock.

Parameters:
gclk generic clock number (0 for gc0...)
Returns:
Status.
Return values:
0 Success.
<0 An error occured.

Definition at line 662 of file scif_uc3c.c.

Referenced by local_start_gc().

00663 {
00664 #ifdef AVR32SFW_INPUT_CHECK
00665   // Check that the generic clock number is correct
00666   if( gclk > AVR32_SCIF_GCLK_NUM )
00667   {
00668     return -1;
00669   }
00670 #endif  // AVR32SFW_INPUT_CHECK
00671 
00672   // If the generic clock is already enabled, do nothing.
00673   if(!(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK))
00674     AVR32_SCIF.gcctrl[gclk] |= AVR32_SCIF_GCCTRL_CEN_MASK;
00675     
00676   return PASS;
00677 
00678 }

long int scif_gc_setup ( unsigned int  gclk,
scif_gcctrl_oscsel_t  clk_src,
unsigned int  diven,
unsigned int  divfactor 
)

Setup a generic clock.

Parameters:
gclk generic clock number (0 for gc0...)
clk_src The input clock source to use for the generic clock
diven Generic clock divisor enable
divfactor Generic clock divisor
Note:
If the generic clock is already enabled, this function will disable it, apply the configuration then restart the generic clock.
Returns:
Status.
Return values:
0 Success.
<0 An error occured.

Definition at line 614 of file scif_uc3c.c.

References SCIF_GCCTRL_OSCSEL_INVALID, and scif_stop_gclk().

Referenced by local_start_gc().

00615 {
00616   int restart_gc = false;
00617   
00618   
00619   // Change the division factor to conform to the equation: fgclk = fsrc/divfactor = fsrc/(2*(div+1))
00620   divfactor = (divfactor>>1) -1;
00621 
00622 #ifdef AVR32SFW_INPUT_CHECK
00623   // Check that the generic clock number is correct
00624   if( gclk > AVR32_SCIF_GCLK_NUM )
00625   {
00626     return -1;
00627   }
00628   // Check that the clock source for the generic clock is correct.
00629   if(( clk_src >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( clk_src < 0 ))
00630   {
00631     return -1;
00632   }
00633   // Check that the required division factor is correct.
00634   if(diven)
00635   {
00636     if(divfactor >= (1<<AVR32_SCIF_GCCTRL_DIV_SIZE))
00637       return -1;
00638   }
00639 #endif  // AVR32SFW_INPUT_CHECK
00640 
00641   // If the generic clock is already enabled, disable it before changing its setup.
00642   if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00643   {
00644     restart_gc = true;
00645     if(scif_stop_gclk(gclk) < 0)
00646       return -1;  // Could not stop the generic clock.
00647   }
00648 
00649   // Setup the generic clock.
00650   AVR32_SCIF.gcctrl[gclk] = ((divfactor << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK)
00651                             |((diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK)
00652                             |((clk_src << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK);
00653                             
00654   // Restart the gc if it previously was enabled.
00655   if(true == restart_gc)
00656     AVR32_SCIF.gcctrl[gclk] |= AVR32_SCIF_GCCTRL_CEN_MASK ;
00657 
00658   return PASS;
00659 }

__inline__ unsigned long scif_get_enabled_interrupts ( void   ) 

Read the SCIF currently enabled interrupts.

Returns:
The enabled interrupts.

Definition at line 266 of file scif_uc3l.h.

00267 {
00268   return(AVR32_SCIF.imr);
00269 }

__inline__ unsigned long scif_get_interrupts_status ( void   ) 

Read the interrupt status of the SCIF.

Returns:
The interrupts which have been triggered.

Definition at line 278 of file scif_uc3l.h.

00279 {
00280   return(AVR32_SCIF.isr);
00281 }

__inline__ unsigned long scif_get_pclk_status ( void   ) 

Read the Power and Clocks Status of the SCIF.

Returns:
The content of the PCLKSR register

Definition at line 309 of file scif_uc3l.h.

00310 {
00311   return(AVR32_SCIF.pclksr);
00312 }

__inline__ bool scif_is_osc32_ready (  ) 

Is OSC32 stable and ready to be used as clock source?

Returns:
Status.
Return values:
true oscillator stable and ready
false oscillator not enabled or not ready.

Definition at line 409 of file scif_uc3l.h.

00410 {
00411   return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC32RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC32RDY_OFFSET);
00412 }

bool scif_is_osc_ready ( scif_osc_t  osc  ) 

Is an oscillator stable and ready to be used as clock source?

Parameters:
osc The oscillator [INPUT]
Returns:
Status.
Return values:
true oscillator stable and ready
false oscillator not enabled or not ready.

Definition at line 197 of file scif_uc3c.c.

References SCIF_OSC0.

00198 {
00199   if (osc == SCIF_OSC0)
00200   {
00201     return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC0RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC0RDY_OFFSET);
00202   }
00203   else
00204   {
00205     return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC1RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC1RDY_OFFSET);  
00206   }
00207 }

__inline__ void scif_osc32_1kout_dis (  ) 

Disable the 1kHz output of the OSC32 oscillator.

Definition at line 431 of file scif_uc3l.h.

00432 {
00433   AVR32_SCIF.oscctrl32 &= ~AVR32_SCIF_EN1K_MASK;
00434 }

__inline__ void scif_osc32_1kout_ena (  ) 

Enable the 1kHz output of the OSC32 oscillator.

Definition at line 420 of file scif_uc3l.h.

00421 {
00422   AVR32_SCIF.oscctrl32 |= AVR32_SCIF_EN1K_MASK;
00423 }

__inline__ void scif_osc32_32kout_dis (  ) 

Disable the 32kHz output of the OSC32 oscillator.

Definition at line 453 of file scif_uc3l.h.

00454 {
00455   AVR32_SCIF.oscctrl32 &= ~AVR32_SCIF_EN32K_MASK;
00456 }

__inline__ void scif_osc32_32kout_ena (  ) 

Enable the 32kHz output of the OSC32 oscillator.

Definition at line 442 of file scif_uc3l.h.

00443 {
00444   AVR32_SCIF.oscctrl32 |= AVR32_SCIF_EN32K_MASK;
00445 }

long int scif_pclksr_statushigh_wait ( unsigned long  statusMask  ) 

Wait for a status high in the Power and Clocks status register.

Parameters:
statusMask Mask field of the status to poll [INPUT]
Returns:
Status.
Return values:
0 Status is high.
<0 SCIF_POLL_TIMEOUT Timeout expired before the status was high.
Wait for a status high in the Power and Clocks status register.

Misc

Wait for a status high in the Power and Clocks status register.

Parameters:
statusMask Mask field of the status to poll [INPUT]
Returns:
Status.
Return values:
0 Status is high.
<0 SCIF_POLL_TIMEOUT Timeout expired before the status was high.

Definition at line 903 of file scif_uc3l.c.

References SCIF_POLL_TIMEOUT.

00904 {
00905   unsigned int  timeout = SCIF_POLL_TIMEOUT;
00906   
00907   while(!(AVR32_SCIF.pclksr & statusMask))
00908   {
00909     if(--timeout == 0)
00910       return -1;
00911   }
00912   return PASS;
00913 }

long int scif_start_gclk ( unsigned int  gclk,
const scif_gclk_opt_t opt 
)

Setup and start a generic clock.

Parameters:
gclk The generic clock number to setup and start (cf. datasheet)
opt The settings for the generic clock.
Returns:
Status.
Return values:
0 Success.
<0 An error occured.

Definition at line 559 of file scif_uc3c.c.

References scif_gclk_opt_t::clock_source, scif_gclk_opt_t::diven, scif_gclk_opt_t::divider, and SCIF_GCCTRL_OSCSEL_INVALID.

00560 {
00561 #ifdef AVR32SFW_INPUT_CHECK
00562   // Check that the generic clock number is correct
00563   if( gclk > AVR32_SCIF_GCLK_NUM )
00564   {
00565     return -1;
00566   }
00567   // Check that the clock source for the generic clock is correct.
00568   if(( opt->clock_source >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( opt->clock_source < 0 ))
00569   {
00570     return -1;
00571   }
00572 #endif  // AVR32SFW_INPUT_CHECK
00573 
00574   // If the generic clock is already enabled, return an error.
00575   if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00576     return -1;
00577 
00578   // Configure & start the generic clock.
00579   AVR32_SCIF.gcctrl[gclk] = ((opt->divider << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK)
00580                             |((opt->diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK)
00581                             |((opt->clock_source << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK)
00582                             |(AVR32_SCIF_GCCTRL_CEN_MASK);
00583 
00584   return PASS;
00585 }

long int scif_start_osc ( scif_osc_t  osc,
const scif_osc_opt_t opt,
bool  wait_for_ready 
)

Configure and start an OSC0/OSC1 oscillator.

Parameters:
osc The oscillator to start [INPUT]
opt The configuration of the oscillator [INPUT]
wait_for_ready Wait for the oscillator to be stable before return [INPUT]
Note:
To avoid an infinite loop, this function checks the osc0 ready flag SCIF_POLL_TIMEOUT times.
Returns:
Status.
Return values:
0 Oscillator start successfull.
<0 Error starting the oscillator.
Configure and start an OSC0/OSC1 oscillator.

Power and Clocks Status Functions OSC0/OSC1 Functions

Definition at line 128 of file scif_uc3c.c.

References scif_osc_opt_t::freq_hz, scif_osc_opt_t::gain, scif_osc_opt_t::mode, u_avr32_scif_oscctrl_t::OSCCTRL, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, SCIF_EXT_CRYSTAL_MAX_FREQ_HZ, SCIF_EXT_CRYSTAL_MIN_FREQ_HZ, SCIF_OSC0, SCIF_OSC_MODE_2PIN_CRYSTAL, SCIF_OSC_MODE_EXT_CLK, scif_pclksr_statushigh_wait(), SCIF_UNLOCK, and scif_osc_opt_t::startup.

00129 {
00130   u_avr32_scif_oscctrl_t   u_avr32_scif_oscctrl;
00131   
00132 #ifdef AVR32SFW_INPUT_CHECK
00133   // Check that the input frequency is in the supported frequency range.
00134   if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ)
00135       || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ))
00136   {
00137     return -1;
00138   }
00139   // Check : for OSC0/OSC1, only 2 modes are supported
00140   if( (opt->mode != SCIF_OSC_MODE_EXT_CLK)
00141       && (opt->mode != SCIF_OSC_MODE_2PIN_CRYSTAL))
00142   {
00143     return -1;
00144   }
00145   
00146   if (osc == SCIF_OSC0)
00147   {
00148     // Check that the startup value is in the supported range.
00149     if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC)
00150     {
00151       return -1;
00152     }
00153     // Check that the gain value is in the supported range.
00154     if(opt->gain > AVR32_SCIF_OSCCTRL0_GAIN_G3)
00155     {
00156       return -1;
00157     }
00158   }
00159   else
00160   {
00161     // Check that the startup value is in the supported range.
00162     if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL1_STARTUP_16384_RCOSC)
00163     {
00164       return -1;
00165     }
00166     // Check that the gain value is in the supported range.
00167     if(opt->gain > AVR32_SCIF_OSCCTRL1_GAIN_G3)
00168     {
00169       return -1;
00170     }  
00171   }
00172 #endif  // AVR32SFW_INPUT_CHECK
00173   // Read Register
00174   u_avr32_scif_oscctrl.OSCCTRL[osc] = AVR32_SCIF.OSCCTRL[osc] ;
00175   // Modify: Configure & start OSC0.
00176   u_avr32_scif_oscctrl.OSCCTRL[osc].mode = opt->mode;
00177   u_avr32_scif_oscctrl.OSCCTRL[osc].gain = opt->gain;
00178   u_avr32_scif_oscctrl.OSCCTRL[osc].startup = opt->startup;
00179   u_avr32_scif_oscctrl.OSCCTRL[osc].oscen = ENABLE;
00180   AVR32_ENTER_CRITICAL_REGION( );
00181   // Unlock the write-protected OSCCTRL0 register
00182   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);    
00183   // Write Back
00184   AVR32_SCIF.OSCCTRL[osc] = u_avr32_scif_oscctrl.OSCCTRL[osc];
00185   AVR32_LEAVE_CRITICAL_REGION( );
00186 
00187   if(true == wait_for_ready)
00188   {
00189     // Wait until OSC0 is stable and ready to be used.
00190     if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK))
00191       return -1;
00192   }
00193   return PASS;
00194 }

long int scif_start_osc32 ( const scif_osc32_opt_t opt,
bool  wait_for_ready 
)

Configure and start the OSC32 oscillator.

Parameters:
opt The configuration of the oscillator [INPUT]
wait_for_ready Wait for the oscillator to be stable before return [INPUT]
Note:
To avoid an infinite loop, this function checks the osc32 ready flag SCIF_POLL_TIMEOUT times.
Returns:
Status.
Return values:
0 Oscillator start successfull.
<0 Error starting the oscillator.

Definition at line 422 of file scif_uc3c.c.

References scif_osc32_opt_t::en1k, scif_osc32_opt_t::en32k, scif_osc32_opt_t::freq_hz, scif_osc32_opt_t::mode, u_avr32_scif_oscctrl32_t::OSCCTRL32, u_avr32_scif_oscctrl32_t::oscctrl32, scif_osc32_opt_t::pinsel, scif_disable_rc32out(), SCIF_EXT_CRYSTAL_MAX_FREQ_HZ, SCIF_EXT_CRYSTAL_MIN_FREQ_HZ, SCIF_OSC_MODE_2PIN_CRYSTAL, SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR, SCIF_OSC_MODE_EXT_CLK, SCIF_OSC_MODE_NOT_SUPPORTED_1, SCIF_OSC_MODE_NOT_SUPPORTED_2, scif_pclksr_statushigh_wait(), SCIF_UNLOCK, and scif_osc32_opt_t::startup.

00423 {
00424   u_avr32_scif_oscctrl32_t  u_avr32_scif_oscctrl32;
00425   
00426   
00427 #ifdef AVR32SFW_INPUT_CHECK
00428   // Check that the input frequency is in the supported frequency range.
00429   if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ)
00430       || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ))
00431   {
00432     return -1;
00433   }
00434   // Check : for OSC0/OSC1, only 2 modes are supported
00435   if( (opt->mode < SCIF_OSC_MODE_EXT_CLK)
00436       || (opt->mode > SCIF_OSC_MODE_2PIN_CRYSTAL)
00437       || (opt->mode == SCIF_OSC_MODE_NOT_SUPPORTED_1)
00438       || (opt->mode == SCIF_OSC_MODE_NOT_SUPPORTED_2) )
00439   {
00440     return -1;
00441   }
00442   // Check that the startup value is in the supported range.
00443   if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL32_STARTUP_524288_RCOSC)
00444   {
00445     return -1;
00446   }
00447 #endif  // AVR32SFW_INPUT_CHECK
00448 
00449   // Read Register
00450   u_avr32_scif_oscctrl32.oscctrl32 = AVR32_SCIF.oscctrl32 ;  
00451   
00452   // Modify : Configure & start OSC32.
00453   u_avr32_scif_oscctrl32.OSCCTRL32.mode = opt->mode;
00454   u_avr32_scif_oscctrl32.OSCCTRL32.startup = opt->startup;
00455   u_avr32_scif_oscctrl32.OSCCTRL32.osc32en = ENABLE;
00456   
00457   AVR32_ENTER_CRITICAL_REGION( );
00458   // Unlock the write-protected OSCCTRL32 register
00459   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32);
00460   
00461   // Write Back
00462   AVR32_SCIF.oscctrl32 = u_avr32_scif_oscctrl32.oscctrl32;
00463   AVR32_LEAVE_CRITICAL_REGION( );
00464 
00465   if(true == wait_for_ready)
00466   {
00467     // Wait until OSC32 is stable and ready to be used.
00468     if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC32RDY_MASK))
00469       return -1;
00470   }
00471   
00472   return PASS;
00473 }

void scif_start_rc120M ( void   ) 

Start the 120MHz internal RCosc (RC120M) clock.

Start the 120MHz internal RCosc (RC120M) clock.

Critical Path Oscillator Functions 120MHz RCosc Functions

Definition at line 532 of file scif_uc3c.c.

References SCIF_UNLOCK.

00533 {
00534   AVR32_ENTER_CRITICAL_REGION( );
00535   // Unlock the write-protected RC120MCR register
00536   SCIF_UNLOCK(AVR32_SCIF_RC120MCR);
00537   AVR32_SCIF.rc120mcr = AVR32_SCIF_RC120MCR_EN_MASK;
00538   AVR32_LEAVE_CRITICAL_REGION( );
00539 }

void scif_start_rc32k ( void   ) 

Start the 32kHz internal RCosc (RC32K) clock.

Definition at line 730 of file scif_uc3l.c.

References SCIF_UNLOCK.

00731 {
00732   AVR32_ENTER_CRITICAL_REGION( );
00733   // Unlock the write-protected RC32KCR register
00734   SCIF_UNLOCK(AVR32_SCIF_RC32KCR);
00735   AVR32_SCIF.rc32kcr = AVR32_SCIF_RC32KCR_EN_MASK;
00736   AVR32_LEAVE_CRITICAL_REGION( );
00737 }

long int scif_stop_gclk ( unsigned int  gclk  ) 

Stop a generic clock.

Parameters:
gclk The generic clock number to stop.
Note:
To avoid an infinite loop, this function checks the Clock enable flag SCIF_POLL_TIMEOUT times.
Returns:
Status.
Return values:
0 Success.
<0 Unable to stop generic clock.

Definition at line 588 of file scif_uc3c.c.

References SCIF_POLL_TIMEOUT.

Referenced by scif_gc_setup().

00589 {
00590   unsigned int  timeout = SCIF_POLL_TIMEOUT;
00591   
00592 #ifdef AVR32SFW_INPUT_CHECK
00593   // Check that the generic clock number is correct
00594   if( gclk > AVR32_SCIF_GCLK_NUM )
00595   {
00596     return -1;
00597   }
00598 #endif  // AVR32SFW_INPUT_CHECK
00599 
00600   // Stop the generic clock.
00601   AVR32_SCIF.gcctrl[gclk] &= ~AVR32_SCIF_GCCTRL_CEN_MASK;
00602   
00603   // Wait until the generic clock is actually stopped.
00604   while(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00605   {
00606     if(--timeout == 0)
00607       return -1;
00608   }
00609   
00610   return PASS;
00611 }

long int scif_stop_osc ( scif_osc_t  osc  ) 

Stop an oscillator.

Parameters:
osc The oscillator to stop
Returns:
Status.
Return values:
0 Oscillator successfully stopped.
<0 An error occured when stopping the oscillator.

Definition at line 210 of file scif_uc3c.c.

References SCIF_UNLOCK.

00211 {
00212 
00213   unsigned long temp;
00214 
00215   temp = AVR32_SCIF.oscctrl[osc];
00216   temp &= ~(AVR32_SCIF_OSCCTRL_OSCEN_DISABLE << AVR32_SCIF_OSCCTRL_OSCEN_OFFSET);
00217   AVR32_ENTER_CRITICAL_REGION( );
00218   // Unlock the write-protected OSCCTRL0 register
00219   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL + 4*osc);
00220   // Stop OSC0.
00221   AVR32_SCIF.oscctrl[osc] = temp;
00222   AVR32_LEAVE_CRITICAL_REGION( );
00223       
00224   return PASS;
00225 }

long int scif_stop_osc32 (  ) 

Stop the OSC32 oscillator.

Returns:
Status.
Return values:
0 Oscillator successfully stopped.
<0 An error occured when stopping the oscillator.

Definition at line 476 of file scif_uc3c.c.

References AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE, and SCIF_UNLOCK.

00477 {
00478   unsigned long temp = AVR32_SCIF.oscctrl32;
00479   temp &= ~(AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE << AVR32_SCIF_OSCCTRL32_OSC32EN_OFFSET);
00480 
00481   AVR32_ENTER_CRITICAL_REGION( );
00482   // Unlock the write-protected OSCCTRL32 register
00483   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32);
00484   
00485   // Stop OSC32.
00486   AVR32_SCIF.oscctrl32 = temp;
00487   AVR32_LEAVE_CRITICAL_REGION( );
00488 
00489   return PASS;
00490 }

void scif_stop_rc120M ( void   ) 

Stop the 120MHz internal RCosc (RC120M) clock.

Definition at line 541 of file scif_uc3c.c.

References SCIF_UNLOCK.

00542 {
00543   unsigned long temp = AVR32_SCIF.rc120mcr;
00544 
00545   AVR32_ENTER_CRITICAL_REGION( );
00546   // Unlock the write-protected RC120MCR register
00547   SCIF_UNLOCK(AVR32_SCIF_RC120MCR);
00548   temp &= ~AVR32_SCIF_RC120MCR_EN_MASK;
00549   AVR32_SCIF.rc120mcr = temp;
00550   AVR32_LEAVE_CRITICAL_REGION( );
00551 }

void scif_stop_rc32k ( void   ) 

Stop the 32kHz internal RCosc (RC32K) clock.

Definition at line 739 of file scif_uc3l.c.

References SCIF_UNLOCK.

00740 {
00741   unsigned long temp = AVR32_SCIF.rc32kcr;
00742 
00743   temp &= ~AVR32_SCIF_RC32KCR_EN_MASK;
00744   AVR32_ENTER_CRITICAL_REGION( );
00745   // Unlock the write-protected RC32KCR register
00746   SCIF_UNLOCK(AVR32_SCIF_RC32KCR);
00747   AVR32_SCIF.rc32kcr = temp;
00748   AVR32_LEAVE_CRITICAL_REGION( );
00749 }


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