This file contains basic functions for the AVR32 CAN, with support for all modes, settings and clock speeds.
Definition in file canif.h.
#include "avr32/io.h"
#include "compiler.h"
#include "preprocessor.h"
#include "conf_can.h"
Go to the source code of this file.
Data Structures | |
struct | can_msg_t |
Defines | |
#define | BRP_MAX 64 |
#define | BRP_MIN 1 |
#define | CANIF_bit_timing(ch) (canif_auto_baudrate(ch) ) |
#define | CANIF_channel_enable_status(ch) ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_CES_MASK) >> AVR32_CANIF_CANSR_CES_OFFSET ) |
CANIFSR Register Access. | |
#define | CANIF_CHANNEL_MODE_LISTENING 1 |
#define | CANIF_CHANNEL_MODE_LOOPBACK 2 |
#define | CANIF_CHANNEL_MODE_NORMAL 0 |
CANIFCFG Register Access. | |
#define | CANIF_channel_overload_status(ch) ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_OVS_MASK) >> AVR32_CANIF_CANSR_OVS_OFFSET ) |
#define | CANIF_channel_receive_status(ch) ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_RS_MASK) >> AVR32_CANIF_CANSR_RS_OFFSET ) |
#define | CANIF_channel_transmit_status(ch) ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_TS_MASK) >> AVR32_CANIF_CANSR_TS_OFFSET ) |
#define | CANIF_clr_ide(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->ide_bit = 0;} |
#define | CANIF_clr_idemask(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->ide_mask_bit = 0);} |
#define | CANIF_clr_interrupt_status(ch) { AVR32_CANIF.channel[ch].caniscr = CANIF_get_interrupt_status(ch); } |
#define | CANIF_clr_mob(ch, mob) |
#define | CANIF_clr_overrun_mode(ch) { AVR32_CANIF.channel[ch].cancfg &= ~(1<<AVR32_CANIF_CANCFG_OVRM_OFFSET); } |
#define | CANIF_clr_reset(ch) { AVR32_CANIF.channel[ch].canctrl = (0<<AVR32_CANIF_CANCTRL_INIT_OFFSET); } |
#define | CANIF_clr_rtr(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->rtr_bit = 0;} |
#define | CANIF_clr_rtrmask(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->rtr_mask_bit = 0;} |
#define | CANIF_conf_bt(ch) |
#define | CANIF_config_rx(ch, mob) {CANIF_mob_clr_dir(ch,mob) } |
#define | CANIF_config_tx(ch, mob) {CANIF_mob_set_dir(ch,mob) } |
#define | CANIF_disable(ch) { AVR32_CANIF.channel[ch].canctrl &= ~(1<<AVR32_CANIF_CANCTRL_CEN_OFFSET);} |
#define | CANIF_disable_interrupt(ch) { AVR32_CANIF.channel[ch].canidr = 0x00000189 ; } |
CANIFIDR Register Access. | |
#define | CANIF_disable_wakeup(ch) { AVR32_CANIF.channel[ch].canctrl &= ~(1<<AVR32_CANIF_CANCTRL_WKEN_OFFSET); } |
#define | CANIF_enable(ch) { AVR32_CANIF.channel[ch].canctrl |= (1<<AVR32_CANIF_CANCTRL_CEN_OFFSET);} |
#define | CANIF_enable_interrupt(ch) { AVR32_CANIF.channel[ch].canier = 0x00000189 ; } |
CANIFIER Register Access. | |
#define | CANIF_enable_wakeup(ch) { AVR32_CANIF.channel[ch].canctrl |= (1<<AVR32_CANIF_CANCTRL_WKEN_OFFSET); } |
#define | CANIF_full_abort(ch) { CANIF_disable(ch) } |
#define | CANIF_get_channel_mode(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_CMODE_MASK)>> AVR32_CANIF_CANCFG_CMODE_OFFSET) ) |
#define | CANIF_get_error_mode(ch) { ((AVR32_CANIF.channel[ch].canfc & AVR32_CANIF_CANFC_EMODE_MASK)>> AVR32_CANIF_CANFC_EMODE_OFFSET) } |
CANIFFC Register Access. | |
#define | CANIF_get_ext_id(ch, mob) ((CANIF_mob_get_ptr_data(ch,mob))->id & 0x1FFFFFFF ) |
#define | CANIF_get_ide(ch, mob) ((CANIF_mob_get_ptr_data(ch,mob))->ide_bit) |
#define | CANIF_get_idemask(ch, mob) ((CANIF_mob_get_ptr_data(ch,mob))->ide_mask_bit) |
#define | CANIF_get_interrupt_aerr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_AERR_MASK)>> AVR32_CANIF_CANISR_AERR_OFFSET )) |
#define | CANIF_get_interrupt_berr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_BERR_MASK)>> AVR32_CANIF_CANISR_BERR_OFFSET )) |
#define | CANIF_get_interrupt_boff_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_BOFF_MASK)>> AVR32_CANIF_CANISR_BOFF_OFFSET )) |
#define | CANIF_get_interrupt_cerr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_cERR_MASK)>> AVR32_CANIF_CANISR_CERR_OFFSET )) |
#define | CANIF_get_interrupt_error_status(ch) ( AVR32_CANIF.channel[ch].canisr & 0x3F) |
#define | CANIF_get_interrupt_ferr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_FERR_MASK)>> AVR32_CANIF_CANISR_FERR_OFFSET )) |
#define | CANIF_get_interrupt_lastmob_selected(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_LSMOB_MASK)>> AVR32_CANIF_CANISR_LSMOB_OFFSET )) |
#define | CANIF_get_interrupt_serr_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_SERR_MASK)>> AVR32_CANIF_CANISR_SERR_OFFSET )) |
#define | CANIF_get_interrupt_status(ch) ( AVR32_CANIF.channel[ch].canisr) |
CANIFISCR Register Access. | |
#define | CANIF_get_interrupt_wakeup_status(ch) ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_WKUP_MASK)>> AVR32_CANIF_CANISR_WKUP_OFFSET )) |
#define | CANIF_get_mobctrl(ch, mob) (((unsigned volatile long*)&(AVR32_CANIF.channel[ch].mobctrl))[mob*3]) |
MOBCTRL Register Access. | |
#define | CANIF_get_overrun_mode(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_OVRM_MASK)>> AVR32_CANIF_CANCFG_OVRM_OFFSET) ) |
#define | CANIF_get_phs1(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_PHS1_MASK)>> AVR32_CANIF_CANCFG_PHS1_OFFSET) ) |
#define | CANIF_get_phs2(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_PHS2_MASK)>> AVR32_CANIF_CANCFG_PHS2_OFFSET) ) |
#define | CANIF_get_pres(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_PRES_MASK)>> AVR32_CANIF_CANCFG_PRES_OFFSET) ) |
#define | CANIF_get_prs(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_PRS_MASK)>> AVR32_CANIF_CANCFG_PRS_OFFSET) ) |
#define | CANIF_get_ram_add(ch) ( AVR32_CANIF.channel[ch].canramb ) |
CANRAMB Register Access. | |
#define | CANIF_get_rec(ch) { ((AVR32_CANIF.channel[ch].canfc & AVR32_CANIF_CANFC_REC_MASK)>> AVR32_CANIF_CANFC_REC_OFFSET) } |
#define | CANIF_get_rtr(ch, mob) ((CANIF_mob_get_ptr_data(ch,mob))->rtr_bit ) |
#define | CANIF_get_rtrmask(ch, mob) ((CANIF_mob_get_ptr_data(ch,mob))->rtr_mask_bit) |
#define | CANIF_get_sjw(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_SJW_MASK)>> AVR32_CANIF_CANCFG_SJW_OFFSET) ) |
#define | CANIF_get_sm(ch) ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_SM_MASK)>> AVR32_CANIF_CANCFG_SM_OFFSET) ) |
#define | CANIF_get_std_id(ch, mob) ((CANIF_mob_get_ptr_data(ch,mob))->id & 0x000007FF ) |
#define | CANIF_get_tec(ch) { ((AVR32_CANIF.channel[ch].canfc & AVR32_CANIF_CANFC_TEC_MASK)>> AVR32_CANIF_CANFC_TEC_OFFSET) } |
#define | CANIF_mob_allocate(ch) (CANIF_mob_get_mob_free(ch)) |
#define | CANIF_mob_clear_rxok_status(ch, mob) {AVR32_CANIF.channel[ch].mrxiscr = 1<<mob;} |
MRXISCR Register Access. | |
#define | CANIF_mob_clear_status(ch, mob) {CANIF_mob_set_status(ch,mob,0x0F)} |
#define | CANIF_mob_clear_txok_status(ch, mob) {AVR32_CANIF.channel[ch].mtxiscr = 1<<mob;} |
MTXISCR Register Access. | |
#define | CANIF_mob_clr_automode(ch, mob) { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)&~(1<<AVR32_CANIF_AM_OFFSET));} |
#define | CANIF_mob_clr_dir(ch, mob) { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)&~(1<<AVR32_CANIF_DIR_OFFSET));} |
#define | CANIF_mob_clr_dlc(ch, mob) { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)&~(0x0F<<AVR32_CANIF_DLC_OFFSET));} |
#define | CANIF_mob_disable(ch, mob) {AVR32_CANIF.channel[ch].mobdr = 1<<mob;} |
MOBDR Register Access. | |
#define | CANIF_mob_disable_interrupt(ch, mob) {AVR32_CANIF.channel[ch].mobidr = 1<<mob;} |
MOBIDR Register Access. | |
#define | CANIF_mob_enable(ch, mob) {AVR32_CANIF.channel[ch].mober = 1<<mob;} |
MOBER Register Access. | |
#define | CANIF_mob_enable_interrupt(ch, mob) {AVR32_CANIF.channel[ch].mobier = 1<<mob;} |
MOBIER Register Access. | |
#define | CANIF_mob_enable_status(ch, mob) ((AVR32_CANIF.channel[ch].mobesr >> mob)&1) |
MOBESR Register Access. | |
#define | CANIF_mob_free(ch, mob) {CANIF_mob_disable(ch,mob)} |
#define | CANIF_mob_free_get_addr_data(ch) (CANIF_SIZE_OF_CANIF_MSG*CANIF_mob_get_mob_free(ch)+CANIF_get_ram_add(ch)) |
#define | CANIF_mob_free_get_ptr_data(ch) ((can_msg_t *)(CANIF_SIZE_OF_CANIF_MSG*CANIF_mob_get_mob_free(ch)+CANIF_get_ram_add(ch))) |
#define | CANIF_mob_get_addr_data(ch, mob) ((CANIF_SIZE_OF_CANIF_MSG*mob+CANIF_get_ram_add(ch))) |
#define | CANIF_mob_get_dir(ch, mob) ( (CANIF_get_mobctrl(ch,mob)&AVR32_CANIF_CANDIR_MASK) >> AVR32_CANIF_DIR_OFFSET ) |
#define | CANIF_mob_get_dlc(ch, mob) ( (CANIF_get_mobctrl(ch,mob)&AVR32_CANIF_DLC_MASK)>>AVR32_CANIF_DLC_OFFSET ) |
#define | CANIF_mob_get_mob_free(ch) ((AVR32_CANIF.channel[ch].mobsch&AVR32_CANIF_MOBSCH_MAV_MASK)>>AVR32_CANIF_MOBSCH_MAV_OFFSET) |
MOBSCH Register Access. | |
#define | CANIF_mob_get_mob_rxok(ch) ((AVR32_CANIF.channel[ch].mobsch&AVR32_CANIF_MOBSCH_MRXOK_MASK)>>AVR32_CANIF_MOBSCH_MRXOK_OFFSET) |
#define | CANIF_mob_get_mob_txok(ch) ((AVR32_CANIF.channel[ch].mobsch&AVR32_CANIF_MOBSCH_MTXOK_MASK)>>AVR32_CANIF_MOBSCH_MTXOK_OFFSET) |
#define | CANIF_mob_get_ptr_data(ch, mob) ((can_msg_t *)(CANIF_SIZE_OF_CANIF_MSG*mob+CANIF_get_ram_add(ch))) |
#define | CANIF_mob_get_rxok_status(ch, mob) ((AVR32_CANIF.channel[ch].mrxisr >> mob)& 1) |
MRXISR Register Access. | |
#define | CANIF_mob_get_status(ch, mob) (((unsigned volatile long*) &(AVR32_CANIF.channel[ch].mobsr))[mob*3]) |
MOBSR Register Access. | |
#define | CANIF_mob_get_txok_status(ch, mob) ((AVR32_CANIF.channel[ch].mtxisr >> mob)& 1) |
MTXISR Register Access. | |
#define | CANIF_mob_set_automode(ch, mob) { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)| (1<<AVR32_CANIF_AM_OFFSET));} |
#define | CANIF_mob_set_dir(ch, mob) { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)| (1<<AVR32_CANIF_DIR_OFFSET));} |
#define | CANIF_mob_set_dlc(ch, mob, dlc) { CANIF_set_mobctrl(ch,mob,(CANIF_get_mobctrl(ch,mob)| (dlc<<AVR32_CANIF_DLC_OFFSET))); } |
#define | CANIF_mob_set_status(ch, mob, val) {((unsigned volatile long*) &(AVR32_CANIF.channel[ch].mobscr))[mob*3]=val;} |
#define | CANIF_mobctrl(ch, mob) (((unsigned volatile long*)&(AVR32_CANIF.channel[ch].mobctrl))[mob*3]) |
#define | CANIF_send_overload(ch) { AVR32_CANIF.channel[ch].canctrl |= (1<<AVR32_CANIF_CANCTRL_OVRQ_OFFSET); } |
#define | CANIF_set_channel_mode(ch, mode) |
#define | CANIF_set_data(ch, mob, _data) {(CANIF_mob_get_ptr_data(ch,mob))->data.u64 = _data;} |
#define | CANIF_set_ext_id(ch, mob, _id) {(CANIF_mob_get_ptr_data(ch,mob))->id = (1<<IDE_BIT)|(_id);} |
#define | CANIF_set_ext_idmask(ch, mob, mask) {(CANIF_mob_get_ptr_data(ch,mob))->id_mask = mask;} |
#define | CANIF_set_ide(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->ide_bit = 1;} |
#define | CANIF_set_idemask(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->ide_mask_bit = 1;} |
#define | CANIF_set_mobctrl(ch, mob, val) (((unsigned volatile long*)&(AVR32_CANIF.channel[ch].mobctrl))[mob*3]=val) |
#define | CANIF_set_overrun_mode(ch) { AVR32_CANIF.channel[ch].cancfg |= (1<<AVR32_CANIF_CANCFG_OVRM_OFFSET); } |
#define | CANIF_set_phs1(ch, phs1) |
#define | CANIF_set_phs2(ch, phs2) |
#define | CANIF_set_pres(ch, pres) |
#define | CANIF_set_prs(ch, prs) |
#define | CANIF_set_ram_add(ch, add) { AVR32_CANIF.channel[ch].canramb = add; } |
#define | CANIF_set_reset(ch) { AVR32_CANIF.channel[ch].canctrl = (1<<AVR32_CANIF_CANCTRL_INIT_OFFSET); } |
CANCTRL Register Access. | |
#define | CANIF_set_rtr(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->rtr_bit = 1;} |
#define | CANIF_set_rtrmask(ch, mob) {(CANIF_mob_get_ptr_data(ch,mob))->rtr_mask_bit = 1;} |
#define | CANIF_set_sjw(ch, sjw) |
#define | CANIF_set_sm(ch, sm) { AVR32_CANIF.channel[ch].cancfg |= (sm<<AVR32_CANIF_CANCFG_SM_OFFSET); } |
#define | CANIF_set_std_id(ch, mob, _id) {(CANIF_mob_get_ptr_data(ch,mob))->id = (_id);} |
#define | CANIF_set_std_idmask(ch, mob, mask) {(CANIF_mob_get_ptr_data(ch,mob))->id_mask = mask;} |
#define | CANIF_SIZE_OF_CANIF_MSG (sizeof(can_msg_t)) |
#define | DATA 0 |
#define | EXTD 1 |
#define | IDE_BIT 29 |
#define | MOB_ACK_ERROR (AVR32_CANIF_AERR_MASK) |
#define | MOB_BIT_ERROR (AVR32_CANIF_BERR_MASK) |
#define | MOB_CRC_ERROR (AVR32_CANIF_CERR_MASK) |
#define | MOB_DISABLE 0xFF |
#define | MOB_FORM_ERROR (AVR32_CANIF_FERR_MASK) |
#define | MOB_NOT_COMPLETED 0x00 |
#define | MOB_NOT_REACHED |
#define | MOB_RX_COMPLETED (AVR32_CANIF_MOBSR_RXOK_MASK) |
#define | MOB_RX_COMPLETED_DLCW ((AVR32_CANIF_MOBSR_RXOK_MASK)|(AVR32_CANIF_MOBSR_DLCW_MASK)) |
#define | MOB_STUFF_ERROR (AVR32_CANIF_SERR_MASK) |
#define | MOB_TX_COMPLETED (AVR32_CANIF_MOBSR_TXOK_MASK) |
#define | NO_MOB 0xff |
#define | NTQ_MAX 25 |
#define | NTQ_MIN 8 |
#define | PHS1_MAX 8 |
#define | PHS1_MIN 2 |
#define | PHS2_MAX 8 |
#define | PHS2_MIN 2 |
#define | PRS_MAX 8 |
#define | PRS_MIN 1 |
#define | REMOTE 1 |
#define | RTR_BIT 30 |
#define | SJW_MAX 4 |
#define | SJW_MIN 1 |
#define | STATUS_CLEARED 0x00 |
#define | STD 0 |
Functions | |
U8 | canif_auto_baudrate (U8 ch) |
Config Baudrate in Autobaud mode. | |
void | canif_clear_all_mob (U8 ch, U8 nb_mob) |
Clear all mob of a channel. | |
U8 | canif_fixed_baudrate (U8 ch) |
Config Baudrate with fixed baudrate. | |
U8 | canif_get_mob_status (unsigned char ch, unsigned char mob) |
Gets the mob status. |
#define CANIF_bit_timing | ( | ch | ) | (canif_auto_baudrate(ch) ) |
#define CANIF_channel_enable_status | ( | ch | ) | ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_CES_MASK) >> AVR32_CANIF_CANSR_CES_OFFSET ) |
#define CANIF_CHANNEL_MODE_LISTENING 1 |
#define CANIF_CHANNEL_MODE_LOOPBACK 2 |
#define CANIF_CHANNEL_MODE_NORMAL 0 |
CANIFCFG Register Access.
Definition at line 152 of file canif.h.
Referenced by can_example_prepare_data(), and can_init().
#define CANIF_channel_overload_status | ( | ch | ) | ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_OVS_MASK) >> AVR32_CANIF_CANSR_OVS_OFFSET ) |
#define CANIF_channel_receive_status | ( | ch | ) | ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_RS_MASK) >> AVR32_CANIF_CANSR_RS_OFFSET ) |
#define CANIF_channel_transmit_status | ( | ch | ) | ( (AVR32_CANIF.channel[ch].cansr&AVR32_CANIF_CANSR_TS_MASK) >> AVR32_CANIF_CANSR_TS_OFFSET ) |
#define CANIF_clr_ide | ( | ch, | |||
mob | ) | {(CANIF_mob_get_ptr_data(ch,mob))->ide_bit = 0;} |
#define CANIF_clr_idemask | ( | ch, | |||
mob | ) | {(CANIF_mob_get_ptr_data(ch,mob))->ide_mask_bit = 0);} |
#define CANIF_clr_interrupt_status | ( | ch | ) | { AVR32_CANIF.channel[ch].caniscr = CANIF_get_interrupt_status(ch); } |
Definition at line 206 of file canif.h.
Referenced by can0_int_busoff_handler(), can0_int_cerr_handler(), can0_int_wakeup_handler(), can1_int_busoff_handler(), can1_int_cerr_handler(), and can1_int_wakeup_handler().
#define CANIF_clr_mob | ( | ch, | |||
mob | ) |
Value:
{(CANIF_mob_get_ptr_data(ch,mob))->id = 0; \ (CANIF_mob_get_ptr_data(ch,mob))->id_mask = 0; \ (CANIF_mob_get_ptr_data(ch,mob))->data.u64 = 0;}
Definition at line 290 of file canif.h.
Referenced by can_mob_alloc(), and canif_clear_all_mob().
#define CANIF_clr_overrun_mode | ( | ch | ) | { AVR32_CANIF.channel[ch].cancfg &= ~(1<<AVR32_CANIF_CANCFG_OVRM_OFFSET); } |
#define CANIF_clr_reset | ( | ch | ) | { AVR32_CANIF.channel[ch].canctrl = (0<<AVR32_CANIF_CANCTRL_INIT_OFFSET); } |
#define CANIF_clr_rtr | ( | ch, | |||
mob | ) | {(CANIF_mob_get_ptr_data(ch,mob))->rtr_bit = 0;} |
#define CANIF_clr_rtrmask | ( | ch, | |||
mob | ) | {(CANIF_mob_get_ptr_data(ch,mob))->rtr_mask_bit = 0;} |
#define CANIF_conf_bt | ( | ch | ) |
Value:
{ CANIF_set_sjw(ch,BAUDRATE##_SJW); \ CANIF_set_prs(ch,BAUDRATE##_PRS); \ CANIF_set_pres(ch,BAUDRATE##_PRES); \ CANIF_set_phs2(ch,BAUDRATE##_PHS2); \ CANIF_set_phs1(ch,BAUDRATE##_PHS1); }
Definition at line 178 of file canif.h.
Referenced by canif_fixed_baudrate().
#define CANIF_config_rx | ( | ch, | |||
mob | ) | {CANIF_mob_clr_dir(ch,mob) } |
#define CANIF_config_tx | ( | ch, | |||
mob | ) | {CANIF_mob_set_dir(ch,mob) } |
#define CANIF_disable | ( | ch | ) | { AVR32_CANIF.channel[ch].canctrl &= ~(1<<AVR32_CANIF_CANCTRL_CEN_OFFSET);} |
#define CANIF_disable_interrupt | ( | ch | ) | { AVR32_CANIF.channel[ch].canidr = 0x00000189 ; } |
#define CANIF_disable_wakeup | ( | ch | ) | { AVR32_CANIF.channel[ch].canctrl &= ~(1<<AVR32_CANIF_CANCTRL_WKEN_OFFSET); } |
#define CANIF_enable | ( | ch | ) | { AVR32_CANIF.channel[ch].canctrl |= (1<<AVR32_CANIF_CANCTRL_CEN_OFFSET);} |
#define CANIF_enable_interrupt | ( | ch | ) | { AVR32_CANIF.channel[ch].canier = 0x00000189 ; } |
CANIFIER Register Access.
Definition at line 190 of file canif.h.
Referenced by can_enable_interrupt().
#define CANIF_enable_wakeup | ( | ch | ) | { AVR32_CANIF.channel[ch].canctrl |= (1<<AVR32_CANIF_CANCTRL_WKEN_OFFSET); } |
#define CANIF_get_channel_mode | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_CMODE_MASK)>> AVR32_CANIF_CANCFG_CMODE_OFFSET) ) |
#define CANIF_get_error_mode | ( | ch | ) | { ((AVR32_CANIF.channel[ch].canfc & AVR32_CANIF_CANFC_EMODE_MASK)>> AVR32_CANIF_CANFC_EMODE_OFFSET) } |
#define CANIF_get_ext_id | ( | ch, | |||
mob | ) | ((CANIF_mob_get_ptr_data(ch,mob))->id & 0x1FFFFFFF ) |
#define CANIF_get_ide | ( | ch, | |||
mob | ) | ((CANIF_mob_get_ptr_data(ch,mob))->ide_bit) |
#define CANIF_get_idemask | ( | ch, | |||
mob | ) | ((CANIF_mob_get_ptr_data(ch,mob))->ide_mask_bit) |
#define CANIF_get_interrupt_aerr_status | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_AERR_MASK)>> AVR32_CANIF_CANISR_AERR_OFFSET )) |
#define CANIF_get_interrupt_berr_status | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_BERR_MASK)>> AVR32_CANIF_CANISR_BERR_OFFSET )) |
#define CANIF_get_interrupt_boff_status | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_BOFF_MASK)>> AVR32_CANIF_CANISR_BOFF_OFFSET )) |
#define CANIF_get_interrupt_cerr_status | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_cERR_MASK)>> AVR32_CANIF_CANISR_CERR_OFFSET )) |
#define CANIF_get_interrupt_error_status | ( | ch | ) | ( AVR32_CANIF.channel[ch].canisr & 0x3F) |
Definition at line 197 of file canif.h.
Referenced by can_mob_get_status(), and canif_get_mob_status().
#define CANIF_get_interrupt_ferr_status | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_FERR_MASK)>> AVR32_CANIF_CANISR_FERR_OFFSET )) |
#define CANIF_get_interrupt_lastmob_selected | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_LSMOB_MASK)>> AVR32_CANIF_CANISR_LSMOB_OFFSET )) |
#define CANIF_get_interrupt_serr_status | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_SERR_MASK)>> AVR32_CANIF_CANISR_SERR_OFFSET )) |
#define CANIF_get_interrupt_status | ( | ch | ) | ( AVR32_CANIF.channel[ch].canisr) |
#define CANIF_get_interrupt_wakeup_status | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].canisr & AVR32_CANIF_CANISR_WKUP_MASK)>> AVR32_CANIF_CANISR_WKUP_OFFSET )) |
#define CANIF_get_mobctrl | ( | ch, | |||
mob | ) | (((unsigned volatile long*)&(AVR32_CANIF.channel[ch].mobctrl))[mob*3]) |
#define CANIF_get_overrun_mode | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_OVRM_MASK)>> AVR32_CANIF_CANCFG_OVRM_OFFSET) ) |
#define CANIF_get_phs1 | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_PHS1_MASK)>> AVR32_CANIF_CANCFG_PHS1_OFFSET) ) |
#define CANIF_get_phs2 | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_PHS2_MASK)>> AVR32_CANIF_CANCFG_PHS2_OFFSET) ) |
#define CANIF_get_pres | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_PRES_MASK)>> AVR32_CANIF_CANCFG_PRES_OFFSET) ) |
#define CANIF_get_prs | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_PRS_MASK)>> AVR32_CANIF_CANCFG_PRS_OFFSET) ) |
#define CANIF_get_ram_add | ( | ch | ) | ( AVR32_CANIF.channel[ch].canramb ) |
#define CANIF_get_rec | ( | ch | ) | { ((AVR32_CANIF.channel[ch].canfc & AVR32_CANIF_CANFC_REC_MASK)>> AVR32_CANIF_CANFC_REC_OFFSET) } |
#define CANIF_get_rtr | ( | ch, | |||
mob | ) | ((CANIF_mob_get_ptr_data(ch,mob))->rtr_bit ) |
#define CANIF_get_rtrmask | ( | ch, | |||
mob | ) | ((CANIF_mob_get_ptr_data(ch,mob))->rtr_mask_bit) |
#define CANIF_get_sjw | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_SJW_MASK)>> AVR32_CANIF_CANCFG_SJW_OFFSET) ) |
#define CANIF_get_sm | ( | ch | ) | ( ((AVR32_CANIF.channel[ch].cancfg & AVR32_CANIF_CANCFG_SM_MASK)>> AVR32_CANIF_CANCFG_SM_OFFSET) ) |
#define CANIF_get_std_id | ( | ch, | |||
mob | ) | ((CANIF_mob_get_ptr_data(ch,mob))->id & 0x000007FF ) |
#define CANIF_get_tec | ( | ch | ) | { ((AVR32_CANIF.channel[ch].canfc & AVR32_CANIF_CANFC_TEC_MASK)>> AVR32_CANIF_CANFC_TEC_OFFSET) } |
#define CANIF_mob_allocate | ( | ch | ) | (CANIF_mob_get_mob_free(ch)) |
#define CANIF_mob_clear_rxok_status | ( | ch, | |||
mob | ) | {AVR32_CANIF.channel[ch].mrxiscr = 1<<mob;} |
MRXISCR Register Access.
Definition at line 247 of file canif.h.
Referenced by can0_int_rx_handler(), and can1_int_rx_handler().
#define CANIF_mob_clear_status | ( | ch, | |||
mob | ) | {CANIF_mob_set_status(ch,mob,0x0F)} |
Definition at line 224 of file canif.h.
Referenced by can0_int_rx_handler(), can0_int_tx_handler(), can1_int_rx_handler(), can1_int_tx_handler(), and can_clear_status().
#define CANIF_mob_clear_txok_status | ( | ch, | |||
mob | ) | {AVR32_CANIF.channel[ch].mtxiscr = 1<<mob;} |
MTXISCR Register Access.
Definition at line 253 of file canif.h.
Referenced by can0_int_tx_handler(), and can1_int_tx_handler().
#define CANIF_mob_clr_automode | ( | ch, | |||
mob | ) | { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)&~(1<<AVR32_CANIF_AM_OFFSET));} |
#define CANIF_mob_clr_dir | ( | ch, | |||
mob | ) | { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)&~(1<<AVR32_CANIF_DIR_OFFSET));} |
#define CANIF_mob_clr_dlc | ( | ch, | |||
mob | ) | { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)&~(0x0F<<AVR32_CANIF_DLC_OFFSET));} |
#define CANIF_mob_disable | ( | ch, | |||
mob | ) | {AVR32_CANIF.channel[ch].mobdr = 1<<mob;} |
#define CANIF_mob_disable_interrupt | ( | ch, | |||
mob | ) | {AVR32_CANIF.channel[ch].mobidr = 1<<mob;} |
#define CANIF_mob_enable | ( | ch, | |||
mob | ) | {AVR32_CANIF.channel[ch].mober = 1<<mob;} |
#define CANIF_mob_enable_interrupt | ( | ch, | |||
mob | ) | {AVR32_CANIF.channel[ch].mobier = 1<<mob;} |
#define CANIF_mob_enable_status | ( | ch, | |||
mob | ) | ((AVR32_CANIF.channel[ch].mobesr >> mob)&1) |
MOBESR Register Access.
Definition at line 238 of file canif.h.
Referenced by canif_get_mob_status().
#define CANIF_mob_free | ( | ch, | |||
mob | ) | {CANIF_mob_disable(ch,mob)} |
#define CANIF_mob_free_get_addr_data | ( | ch | ) | (CANIF_SIZE_OF_CANIF_MSG*CANIF_mob_get_mob_free(ch)+CANIF_get_ram_add(ch)) |
#define CANIF_mob_free_get_ptr_data | ( | ch | ) | ((can_msg_t *)(CANIF_SIZE_OF_CANIF_MSG*CANIF_mob_get_mob_free(ch)+CANIF_get_ram_add(ch))) |
#define CANIF_mob_get_addr_data | ( | ch, | |||
mob | ) | ((CANIF_SIZE_OF_CANIF_MSG*mob+CANIF_get_ram_add(ch))) |
#define CANIF_mob_get_dir | ( | ch, | |||
mob | ) | ( (CANIF_get_mobctrl(ch,mob)&AVR32_CANIF_CANDIR_MASK) >> AVR32_CANIF_DIR_OFFSET ) |
#define CANIF_mob_get_dlc | ( | ch, | |||
mob | ) | ( (CANIF_get_mobctrl(ch,mob)&AVR32_CANIF_DLC_MASK)>>AVR32_CANIF_DLC_OFFSET ) |
#define CANIF_mob_get_mob_free | ( | ch | ) | ((AVR32_CANIF.channel[ch].mobsch&AVR32_CANIF_MOBSCH_MAV_MASK)>>AVR32_CANIF_MOBSCH_MAV_OFFSET) |
#define CANIF_mob_get_mob_rxok | ( | ch | ) | ((AVR32_CANIF.channel[ch].mobsch&AVR32_CANIF_MOBSCH_MRXOK_MASK)>>AVR32_CANIF_MOBSCH_MRXOK_OFFSET) |
Definition at line 228 of file canif.h.
Referenced by can0_int_rx_handler(), and can1_int_rx_handler().
#define CANIF_mob_get_mob_txok | ( | ch | ) | ((AVR32_CANIF.channel[ch].mobsch&AVR32_CANIF_MOBSCH_MTXOK_MASK)>>AVR32_CANIF_MOBSCH_MTXOK_OFFSET) |
Definition at line 229 of file canif.h.
Referenced by can0_int_tx_handler(), and can1_int_tx_handler().
#define CANIF_mob_get_ptr_data | ( | ch, | |||
mob | ) | ((can_msg_t *)(CANIF_SIZE_OF_CANIF_MSG*mob+CANIF_get_ram_add(ch))) |
#define CANIF_mob_get_rxok_status | ( | ch, | |||
mob | ) | ((AVR32_CANIF.channel[ch].mrxisr >> mob)& 1) |
#define CANIF_mob_get_status | ( | ch, | |||
mob | ) | (((unsigned volatile long*) &(AVR32_CANIF.channel[ch].mobsr))[mob*3]) |
MOBSR Register Access.
Definition at line 222 of file canif.h.
Referenced by can_mob_get_status(), and canif_get_mob_status().
#define CANIF_mob_get_txok_status | ( | ch, | |||
mob | ) | ((AVR32_CANIF.channel[ch].mtxisr >> mob)& 1) |
#define CANIF_mob_set_automode | ( | ch, | |||
mob | ) | { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)| (1<<AVR32_CANIF_AM_OFFSET));} |
#define CANIF_mob_set_dir | ( | ch, | |||
mob | ) | { CANIF_set_mobctrl(ch,mob,CANIF_get_mobctrl(ch,mob)| (1<<AVR32_CANIF_DIR_OFFSET));} |
#define CANIF_mob_set_dlc | ( | ch, | |||
mob, | |||||
dlc | ) | { CANIF_set_mobctrl(ch,mob,(CANIF_get_mobctrl(ch,mob)| (dlc<<AVR32_CANIF_DLC_OFFSET))); } |
#define CANIF_mob_set_status | ( | ch, | |||
mob, | |||||
val | ) | {((unsigned volatile long*) &(AVR32_CANIF.channel[ch].mobscr))[mob*3]=val;} |
#define CANIF_mobctrl | ( | ch, | |||
mob | ) | (((unsigned volatile long*)&(AVR32_CANIF.channel[ch].mobctrl))[mob*3]) |
#define CANIF_send_overload | ( | ch | ) | { AVR32_CANIF.channel[ch].canctrl |= (1<<AVR32_CANIF_CANCTRL_OVRQ_OFFSET); } |
#define CANIF_set_channel_mode | ( | ch, | |||
mode | ) |
Value:
{ AVR32_CANIF.channel[ch].cancfg &= ~(AVR32_CANIF_CANCFG_CMODE_MASK); \ AVR32_CANIF.channel[ch].cancfg |= (mode<<AVR32_CANIF_CANCFG_CMODE_OFFSET); }
Definition at line 156 of file canif.h.
Referenced by can_init().
#define CANIF_set_data | ( | ch, | |||
mob, | |||||
_data | ) | {(CANIF_mob_get_ptr_data(ch,mob))->data.u64 = _data;} |
#define CANIF_set_ext_id | ( | ch, | |||
mob, | |||||
_id | ) | {(CANIF_mob_get_ptr_data(ch,mob))->id = (1<<IDE_BIT)|(_id);} |
#define CANIF_set_ext_idmask | ( | ch, | |||
mob, | |||||
mask | ) | {(CANIF_mob_get_ptr_data(ch,mob))->id_mask = mask;} |
#define CANIF_set_ide | ( | ch, | |||
mob | ) | {(CANIF_mob_get_ptr_data(ch,mob))->ide_bit = 1;} |
#define CANIF_set_idemask | ( | ch, | |||
mob | ) | {(CANIF_mob_get_ptr_data(ch,mob))->ide_mask_bit = 1;} |
#define CANIF_set_mobctrl | ( | ch, | |||
mob, | |||||
val | ) | (((unsigned volatile long*)&(AVR32_CANIF.channel[ch].mobctrl))[mob*3]=val) |
#define CANIF_set_overrun_mode | ( | ch | ) | { AVR32_CANIF.channel[ch].cancfg |= (1<<AVR32_CANIF_CANCFG_OVRM_OFFSET); } |
#define CANIF_set_phs1 | ( | ch, | |||
phs1 | ) |
#define CANIF_set_phs2 | ( | ch, | |||
phs2 | ) |
#define CANIF_set_pres | ( | ch, | |||
pres | ) |
#define CANIF_set_prs | ( | ch, | |||
prs | ) |
#define CANIF_set_ram_add | ( | ch, | |||
add | ) | { AVR32_CANIF.channel[ch].canramb = add; } |
#define CANIF_set_reset | ( | ch | ) | { AVR32_CANIF.channel[ch].canctrl = (1<<AVR32_CANIF_CANCTRL_INIT_OFFSET); } |
#define CANIF_set_rtr | ( | ch, | |||
mob | ) | {(CANIF_mob_get_ptr_data(ch,mob))->rtr_bit = 1;} |
#define CANIF_set_rtrmask | ( | ch, | |||
mob | ) | {(CANIF_mob_get_ptr_data(ch,mob))->rtr_mask_bit = 1;} |
#define CANIF_set_sjw | ( | ch, | |||
sjw | ) |
#define CANIF_set_sm | ( | ch, | |||
sm | ) | { AVR32_CANIF.channel[ch].cancfg |= (sm<<AVR32_CANIF_CANCFG_SM_OFFSET); } |
#define CANIF_set_std_id | ( | ch, | |||
mob, | |||||
_id | ) | {(CANIF_mob_get_ptr_data(ch,mob))->id = (_id);} |
#define CANIF_set_std_idmask | ( | ch, | |||
mob, | |||||
mask | ) | {(CANIF_mob_get_ptr_data(ch,mob))->id_mask = mask;} |
#define MOB_DISABLE 0xFF |
#define MOB_NOT_COMPLETED 0x00 |
#define MOB_NOT_REACHED |
#define MOB_RX_COMPLETED (AVR32_CANIF_MOBSR_RXOK_MASK) |
Definition at line 105 of file canif.h.
Referenced by can_mob_get_status(), and canif_get_mob_status().
#define MOB_RX_COMPLETED_DLCW ((AVR32_CANIF_MOBSR_RXOK_MASK)|(AVR32_CANIF_MOBSR_DLCW_MASK)) |
Definition at line 106 of file canif.h.
Referenced by can_mob_get_status(), and canif_get_mob_status().
#define MOB_TX_COMPLETED (AVR32_CANIF_MOBSR_TXOK_MASK) |
Definition at line 104 of file canif.h.
Referenced by can_mob_get_status(), and canif_get_mob_status().
#define NO_MOB 0xff |
U8 canif_auto_baudrate | ( | U8 | ch | ) |
Config Baudrate in Autobaud mode.
Definition at line 109 of file canif.c.
00110 { 00111 /* 00112 U8 u8_temp0; //! Temporary variable 00113 U8 brp, prs, ntq, phs1, phs2; //! Bit timing segment variables 00114 U8 phs1_inc; //! Computing needed 00115 U8 bt_not_found, wait_for_rx, evaluate; //! Keys for "while()" loops 00116 U8 try_conf; //! Key for configurate CAN 00117 U8 ovrtim_flag=0; //! Timer overflow count 00118 U16 conf_index; //! Count of bit timing configuration tried 00119 U8 bt_performed; //! Return flag 00120 00122 phs1_inc = evaluate = 0; 00123 bt_performed = 0; 00124 conf_index = 0; 00125 bt_not_found = 1; 00126 00129 if (mode==0) 00130 { 00131 brp = BRP_MIN; 00132 ntq = NTQ_MIN; 00133 phs1 = PHS1_MIN; 00134 phs2 = PHS2_MIN; 00135 prs = ntq - ( phs1 + phs2 + 1 ); 00136 try_conf = 1; //! Try this configuration 00137 wait_for_rx = 1; //! Enable "while (wait_for_rx ..." loop 00138 } 00139 else //! mode = 1 00140 { 00141 brp = Max ((((PRES & BRP_MSK) >> 1) +1) , BRP_MIN ); 00142 prs = Max ((((PRS & PRS_MSK) >> 1) +1) , PRS_MIN ); 00143 phs1 = Max ((((PHS1 & PHS1_MSK) >> 1) +1) , PHS1_MIN); 00144 phs2 = Max ((((PHS2 & PHS2_MSK) >> 4) +1) , PHS2_MIN); 00145 ntq = Max ((prs + phs1 + phs2 + 1) , NTQ_MIN); 00146 phs1_inc = evaluate = 1; //! To enter in "while (evaluate ..." loop 00147 try_conf = 0; //! Look for the next configuration 00148 wait_for_rx = 0; //! Skip "while (wait_for_rx ..." loop 00149 } 00150 00152 can_clear_all_mob(mob_ram); 00153 00154 while (bt_not_found == 1) 00155 { 00156 if (try_conf == 1) 00157 { 00158 Can_reset(); 00159 conf_index++; 00160 ovrtim_flag=0; 00161 00163 PRES = ((brp-1) << PRES); 00164 PHS1 = (((phs2 >> 1)-1) << SJW) |((prs-1) << PRS); 00165 PHS2 = (((phs2-1) << PHS2) | ((phs1-1) << PHS1) | (1<<SMP)); 00166 00171 CANTCON = (U8)(conf_index >> 3); 00172 00174 Can_set_mob(MOB_0); //! Use MOb-0 00175 CANSTMOB = 0; //! Reset MOb status (undone by "Can_reset()") 00176 CANCDMOB = (MOB_Rx_ENA << CONMOB); //! MOb 0 in receive mode 00177 00179 CANGCON = (1<<LISTEN) | (1<<ENASTB);//! Enable CAN controller in "listen" mode 00180 while ((CANGSTA & (1<<ENFG)) == 0); //! Wait for Enable OK 00181 CANGIT = 0xFF; //! Reset General errors and OVRTIM flag 00182 } 00183 00189 while (wait_for_rx == 1) 00190 { 00191 u8_temp0 = CANSTMOB; 00193 if ((u8_temp0 & (1<<RXOK)) != 0) 00194 { //! --- It is the successful output of "can_auto_baudrate" function 00195 wait_for_rx = 0; //! Out of "while (wait_for_rx ..." loop 00196 evaluate = 0; //! Will skip "while (evaluate ..." loop 00197 bt_not_found = 0; //! Out of "while (bt_not_found ..." loop 00198 bt_performed = 1; //! Return flag = TRUE 00199 DISABLE_MOB; //! Disable MOb-0 00200 CANGCON = 0x00; //! Disable CAN controller & reset "listen" mode 00201 while ((CANGSTA & (1<<ENFG)) != 0); //! Wait for Disable OK 00202 } 00204 else 00205 { 00207 if ((u8_temp0 & ((1<<BERR)|(1<<SERR)|(1<<CERR)|(1<<FERR)|(1<<AERR))) !=0) 00208 { 00209 evaluate = 1; //! Will enter in "while (evaluate ..." loop 00210 wait_for_rx = 0; //! Out of "while (wait_for_rx ..." loop 00211 } 00212 00213 u8_temp0 = CANGIT; 00214 00216 if ((u8_temp0 & (1<<OVRTIM)) !=0 ) 00217 { 00218 if (ovrtim_flag==0) 00219 { 00221 CANGIT |= (1<<OVRTIM); // Reset OVRTIM 00222 ovrtim_flag++; 00223 } 00224 else 00225 { 00227 CANGIT |= (1<<OVRTIM); // Reset OVRTIM 00228 evaluate = 1; //! Will enter in "while (evaluate ..." loop 00229 wait_for_rx = 0; //! Out of "while (wait_for_rx ..." loop 00230 } 00231 } 00232 00234 if ((u8_temp0 & ((1<<SERG)|(1<<CERG)|(1<<FERG)|(1<<AERG))) !=0) 00235 { 00236 evaluate = 1; //! Will enter in "while (evaluate ..." loop 00237 wait_for_rx = 0; //! Out of "while (wait_for_rx ..." loop 00238 try_conf = 1; //! Try this configuration 00239 } 00240 } 00241 } // while wait_for_rx ... 00242 00251 while (evaluate == 1) 00252 { 00253 if (phs1_inc != 0) phs1++; 00254 phs1_inc = 1; 00255 00256 // --- The following test takes into account the previous incrementation of phs1 00257 if ((phs1 > PHS1_MAX) && (phs2 >= PHS2_MAX)) 00258 { 00259 phs1 = PHS1_MIN; 00260 phs2 = PHS2_MIN; 00261 phs1_inc = 0; 00262 if (ntq != NTQ_MAX) ntq++; 00263 else 00264 { 00265 ntq = NTQ_MIN; 00266 if (brp != BRP_MAX) brp++; 00267 else 00268 { 00270 evaluate = 0; //! Out of "while (evaluate ..." loop 00271 bt_performed = 0; //! Return flag = FALSE 00272 bt_not_found = 0; //! Out of "while (bt_not_found ..." loop 00273 DISABLE_MOB; //! Disable MOb-0 00274 CANGCON = 0x00; //! Disable CAN controller & reset "listen" mode 00275 while ((CANGSTA & (1<<ENFG)) != 0); //! Wait for Disable OK 00276 } 00277 } 00278 } 00279 else // if (phs1 > PHS1_MAX ... 00280 { 00282 if (phs1>5) 00283 { 00284 if (phs1>(phs2+1)) phs1=(++phs2); 00285 } 00286 else 00287 { 00288 phs2=phs1; 00289 } 00290 prs = ntq - ( phs1 + phs2 + 1 ); 00291 00293 if ((prs <= PRS_MAX) && (prs >= PRS_MIN)) 00294 { 00296 if (((phs2<<2) >= (1+prs+phs1)) && ((phs2+phs2+phs2) <= (1+prs+phs1))) 00297 { 00298 evaluate = 0; //! Out of "while (evaluate ..." loop & 00299 wait_for_rx = 1; //! new "while (bt_not_found ..." loop 00300 } 00301 } 00302 } 00303 } // while (evaluate ... 00304 } // while (bt_not_found ... 00305 00306 return (bt_performed); 00307 */ 00308 return 1; 00309 }
void canif_clear_all_mob | ( | U8 | ch, | |
U8 | nb_mob | |||
) |
Clear all mob of a channel.
Definition at line 57 of file canif.c.
References CANIF_clr_mob.
Referenced by can_init().
00059 { 00060 unsigned char mob_number; 00061 for (mob_number = 0; mob_number < nb_mob; mob_number++) 00062 { 00063 CANIF_clr_mob(ch,mob_number) 00064 } 00065 }
U8 canif_fixed_baudrate | ( | U8 | ch | ) |
Config Baudrate with fixed baudrate.
Definition at line 311 of file canif.c.
References CANIF_conf_bt.
00312 { 00313 CANIF_conf_bt(ch); 00314 /*CAN_enable(ch); 00315 while(!CAN_channel_enable_status(ch));*/ 00316 return 1; 00317 }
U8 canif_get_mob_status | ( | unsigned char | ch, | |
unsigned char | mob | |||
) |
Gets the mob status.