EMB Project Status (06/14/2010 - 18:30:12)
Project File: EMB.ise Implementation State: Programming File Not Generated
Module Name: toplevel
  • Errors:
No Errors
Target Device: xc3s500e-5pq208
  • Warnings:
1 Warning
Product Version:ISE 11.1
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0, Component Switching Limit: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 551 9,312 5%  
Number of 4 input LUTs 210 9,312 2%  
Number of occupied Slices 503 4,656 10%  
    Number of Slices containing only related logic 503 503 100%  
    Number of Slices containing unrelated logic 0 503 0%  
Total Number of 4 input LUTs 210 9,312 2%  
Number of bonded IOBs 98 158 62%  
Number of RAMB16s 4 20 20%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 2.20      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon Jun 14 18:28:20 201001 Warning3 Infos
Translation ReportCurrentMon Jun 14 18:28:40 2010000
Map ReportCurrentMon Jun 14 18:29:04 2010005 Infos
Place and Route ReportCurrentMon Jun 14 18:29:44 2010000
Power Report     
Post-PAR Static Timing ReportCurrentMon Jun 14 18:29:52 2010002 Infos
Bitgen ReportCurrentMon Jun 14 18:30:10 2010000
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 06/16/2010 - 09:04:30