00001 /*This file has been prepared for Doxygen automatic documentation generation.*/ 00080 #include "board.h" 00081 #include "gpio.h" 00082 00083 #if UC3L 00084 // Note: for UC3L devices, the osc configurations are handled by the SCIF module 00085 // and the synchronous clocks used to clock the main digital logic are handled 00086 // by the PM module. 00087 #include "scif_uc3l.h" 00088 #include "pm_uc3l.h" 00089 #include "flashcdw.h" 00090 #elif UC3C 00091 // Note: for UC3C devices, the osc configurations are handled by the SCIF module 00092 // and the synchronous clocks used to clock the main digital logic are handled 00093 // by the PM module. 00094 #include "pm_uc3c.h" 00095 #include "scif_uc3c.h" 00096 #include "flashc.h" 00097 #endif 00098 #include "board.h" 00099 00100 00103 00104 #if BOARD == STK600_RCUC3L0 || BOARD == UC3L_EK 00105 # define EXAMPLE_GCLK_ID AVR32_SCIF_GCLK_DFLL0_SSG 00106 # define EXAMPLE_GCLK_PIN AVR32_SCIF_GCLK_1_0_PIN 00107 # define EXAMPLE_GCLK_FUNCTION AVR32_SCIF_GCLK_1_0_FUNCTION 00108 # define EXAMPLE_CPUCLK_HZ (30000000UL) 00109 // Note that GCLK_1_0 is GPIO pin 6/pin pa06/pin#10 on a UC3L QFP48 package; with 00110 // the RCUC3L0 routing card, this pin is mapped on STK600.PORTA.PA6. 00111 #endif 00112 00113 #if !defined(EXAMPLE_GCLK_ID) || \ 00114 !defined(EXAMPLE_GCLK_PIN) || \ 00115 !defined(EXAMPLE_GCLK_FUNCTION) 00116 # error The generic clock configuration to use in this example is missing. 00117 #endif 00119 00120 00121 /* \brief Start RC120M, switch main clock to RC120M. 00122 */ 00123 static void local_set_main_clock_to_rc120m(void) 00124 { 00125 // Start the 120MHz internal RCosc (RC120M) clock 00126 scif_start_rc120M(); 00127 00128 // Since our target is to set the CPU&HSB frequency domains to 30MHz, set the 00129 // appropriate wait-state and speed read mode on the flash controller. 00130 flashcdw_set_flash_waitstate_and_readmode(EXAMPLE_CPUCLK_HZ); 00131 00132 // Set the CPU clock domain to 30MHz (by applying a division ratio = 4). 00133 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_4); 00134 00135 // Set the PBA clock domain to 30MHz (by applying a division ratio = 4). 00136 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_4); 00137 00138 // Set the PBB clock domain to 30MHz (by applying a division ratio = 4). 00139 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_4); 00140 00141 // Set the main clock source to be the RC120M. 00142 pm_set_mclk_source(PM_CLK_SRC_RC120M); 00143 } 00144 00145 00146 /* \brief Set-up a generic clock to run from RC120M and output it to a gpio pin. 00147 * 00148 */ 00149 static void local_start_gc(void) 00150 { 00151 // Note: for UC3L devices, the generic clock configurations are handled by the 00152 // SCIF module. 00153 // Setup gc to use RC120M as source clock, divisor enabled, apply a division factor. 00154 // Since the RC120M frequency is 120MHz, set the division factor to 4 to have a 00155 // gclk frequency of 30MHz. 00156 scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_RC120M, AVR32_GC_DIV_CLOCK, 4); 00157 00158 // Now enable the generic clock 00159 scif_gc_enable(EXAMPLE_GCLK_ID); 00160 00161 // Set the GCLOCK function to the GPIO pin 00162 gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION); 00163 } 00164 00165 /* \brief Software Delay 00166 * 00167 */ 00168 static void software_delay(void) 00169 { 00170 volatile int i; 00171 for (i=0; i<1000000; i++); 00172 } 00173 00174 00175 /* \brief This is an example that shows how to do the following: 00176 * - start the RC120M RC Osc 00177 * - switch the main clock to RC120M/4 00178 * - set-up a generic clock with the RC120M RC Osc as a source 00179 * - output a generic clock to GCLK_1_0(STK600_RCUC3L0 & AT32UC3L-EK) 00180 * 00181 */ 00182 int main(void) 00183 { 00184 // Start RC120M, switch main clock to RC120M/4. 00185 local_set_main_clock_to_rc120m(); 00186 00187 /* Set-up a generic clock from a high frequency clock and output it to a gpio pin. */ 00188 local_start_gc(); 00189 00190 /* Now toggle LED0 using a GPIO */ 00191 while(1) 00192 { 00193 gpio_tgl_gpio_pin(LED0_GPIO); 00194 software_delay(); 00195 } 00196 }