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AVR UC3 Series Software Framework: DACIFB Driver

Copyright © 2007 Atmel Corporation

Introduction

The Bus Matrix implements a multi-layer bus structure, that enables parallel access paths between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to up to 16 HSB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix provides 16 Special Function Registers (SFR) that allow the Bus Matrix to support application specific features.

 

HMARTIX Driver

The driver is composed of hmatrix.c.

 

One examples is available:

Last Default Master example.

 


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