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00048 #ifndef _AES_H_
00049 #define _AES_H_
00050
00051 #include <avr32/io.h>
00052 #include "compiler.h"
00053
00054
00056 #define AES_PMODE_DECIPHER 0 // decipher
00057 #define AES_PMODE_CIPHER 1 // cipher
00058
00059
00061 #define AES_START_MODE_MANUAL 0 // Manual mode
00062 #define AES_START_MODE_AUTO 1 // Auto mode
00063 #define AES_START_MODE_DMA 2 // DMA mode (TODO: TO REMOVE)
00064
00066 #define AES_KEY_SIZE_128 0 // 128bit
00067 #define AES_KEY_SIZE_192 1 // 192bit
00068 #define AES_KEY_SIZE_256 2 // 256bit
00069
00071 #define AES_ECB_MODE 0 // Electronic Code Book mode
00072 #define AES_CBC_MODE 1 // Cipher Block Chaining mode
00073 #define AES_OFB_MODE 2 // Output FeedBack mode
00074 #define AES_CFB_MODE 3 // Cipher FeedBack mode
00075 #define AES_CTR_MODE 4 // Counter mode
00076
00078 #define AES_URAT_INPUTWRITE_DMA 0 // Input Data Register written during the data processing in DMA mode(TODO: TO REMOVE)
00079 #define AES_URAT_OUTPUTREAD_PROCESS 1 // Output Data Register read during the data processing
00080 #define AES_URAT_MRWRITE_PROCESS 2 // Mode Register written during the data processing
00081 #define AES_URAT_OUTPUTREAD_SUBKEY 3 // Output Data Register read during the sub-keys generation
00082 #define AES_URAT_MRWRITE_SUBKEY 4 // Mode Register written during the sub-keys generation
00083 #define AES_URAT_READ_WRITEONLY 5 // Write-only register read access
00084
00085
00087 typedef struct
00088 {
00089 unsigned char ProcessingMode;
00090 unsigned char ProcessingDelay;
00091 unsigned char StartMode;
00092 unsigned char KeySize;
00093 unsigned char OpMode;
00094 unsigned char LodMode;
00095 unsigned char CFBSize;
00096 unsigned char CounterMeasureMask;
00097 }aes_config_t;
00098
00099
00101 typedef struct
00102 {
00103 unsigned char datrdy;
00104 unsigned char urad;
00105 }aes_isrconfig_t;
00106
00107
00108
00117 void aes_configure( volatile avr32_aes_t *aes, const aes_config_t *pAesConfig );
00118
00119
00128 extern void aes_isr_configure( volatile avr32_aes_t *aes, const aes_isrconfig_t *pAesIsrConfig );
00129
00130
00138 extern unsigned int aes_get_status( volatile avr32_aes_t *aes );
00139
00140
00146 #if __GNUC__
00147 __attribute__((__always_inline__))
00148 #endif
00149 extern __inline__ void aes_start( volatile avr32_aes_t *aes )
00150 {
00151 aes->cr = AVR32_AES_CR_START_MASK;
00152 }
00153
00154
00160 #if __GNUC__
00161 __attribute__((__always_inline__))
00162 #endif
00163 extern __inline__ void aes_swreset( volatile avr32_aes_t *aes )
00164 {
00165 aes->cr = AVR32_AES_CR_SWRST_MASK;
00166 }
00167
00168
00177 extern void aes_set_key( volatile avr32_aes_t *aes, const unsigned int *pKey);
00178
00179
00186 extern void aes_set_initvector( volatile avr32_aes_t *aes, const unsigned int *pVector);
00187
00188
00195 extern void aes_write_inputdata( volatile avr32_aes_t *aes, const unsigned int *pIn);
00196
00197
00204 extern void aes_read_outputdata( volatile avr32_aes_t *aes, unsigned int *pOut);
00205
00206
00207
00213 #if __GNUC__
00214 __attribute__((__always_inline__))
00215 #endif
00216 extern __inline__ void aes_load_newseed(volatile avr32_aes_t *aes)
00217 {
00218 aes->cr = AVR32_AES_CR_LOADSEED_MASK;
00219 }
00220
00221 #endif // _AES_H_