00001
00085 #include "board.h"
00086 #include "gpio.h"
00087 #include "scif_uc3l.h"
00088 #include "power_clocks_lib.h"
00089
00092
00093 #if BOARD == STK600_RCUC3L0 || BOARD == UC3L_EK
00094 #define EXAMPLE_GCLK_ID AVR32_SCIF_GCLK_DFLL0_SSG // Do not use the AVR32_SCIF_GCLK_DFLL0_REF gc.
00095 #define EXAMPLE_GCLK_PIN AVR32_SCIF_GCLK_1_0_PIN // Mapped on STK600.PORTA.PA6; connector PA6 on AT32UC3L-EK
00096 #define EXAMPLE_GCLK_FUNCTION AVR32_SCIF_GCLK_1_0_FUNCTION
00097 #endif
00098
00099 #if !defined(EXAMPLE_GCLK_ID) || \
00100 !defined(EXAMPLE_GCLK_PIN) || \
00101 !defined(EXAMPLE_GCLK_FUNCTION)
00102 # error The generic clock configuration to use in this example is missing.
00103 #endif
00104
00106 #define EXAMPLE_FDFLL_KHZ 24000
00107 #define EXAMPLE_FDFLL_HZ 24000000
00108
00110 #define EXAMPLE_GCLK_FREQ_HZ 12000000
00111
00113
00117 static void local_start_dfll_clock()
00118 {
00119 scif_dfll_closedloop_conf_t DfllConfig;
00120 scif_gclk_opt_t GcConf;
00121
00122
00123
00124
00125
00126 GcConf.clock_source = SCIF_GCCTRL_SLOWCLOCK;
00127 GcConf.diven = OFF;
00128
00129
00130 scif_dfll0_closedloop_mainref_gc_enable(&GcConf);
00131
00132
00133
00134 DfllConfig.coarse = ((unsigned long long)(EXAMPLE_FDFLL_HZ - SCIF_DFLL_MINFREQ_HZ)*255)/(SCIF_DFLL_MAXFREQ_HZ - SCIF_DFLL_MINFREQ_HZ);
00135
00136
00137 DfllConfig.fmul = ((unsigned long long)EXAMPLE_FDFLL_HZ<<16)/SCIF_SLOWCLOCK_FREQ_HZ;
00138
00139 #if (defined(__GNUC__) \
00140 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00141 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00142 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00143
00144 DfllConfig.finemaxstep = 0x0000004;
00145 DfllConfig.coarsemaxstep = 0x0000004;
00146 #else
00147
00148
00149
00150
00151
00152
00153 DfllConfig.maxstep = 0x0040004;
00154 #endif
00155 scif_dfll0_closedloop_start(&DfllConfig);
00156 }
00157
00158
00163 static void local_start_gc()
00164 {
00165
00166
00167 scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_DFLL0, AVR32_GC_DIV_CLOCK,
00168 EXAMPLE_FDFLL_HZ/EXAMPLE_GCLK_FREQ_HZ);
00169
00170
00171 scif_gc_enable(EXAMPLE_GCLK_ID);
00172
00173
00174 gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION);
00175
00176 }
00177
00178
00179
00180
00181
00182
00183
00184
00185
00186
00187 int main(void)
00188 {
00189
00190 local_start_dfll_clock();
00191
00192
00193
00194 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_2);
00195 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_2);
00196 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_2);
00197
00198 pm_set_mclk_source(PM_CLK_SRC_DFLL0);
00199
00200
00201 local_start_gc();
00202
00203
00204
00205
00206
00207 AVR32_INTC.ipr[0];
00208
00209
00210 SLEEP(AVR32_PM_SMODE_FROZEN);
00211
00212 while(1);
00213 }
00214