Definition in file ram_aes_ram_example.c.
#include <string.h>
#include "board.h"
#include "print_funcs.h"
#include "gpio.h"
#include "pm.h"
#include "intc.h"
#include "usart.h"
#include "aes.h"
Go to the source code of this file.
Defines | |
#define | DMACA_AES_EVAL_BUF_SIZE 256 |
#define | DMACA_AES_EVAL_REFBUF_SIZE 16 |
Board-Related Example Settings | |
#define | DMACA_AES_EVAL_LED1 LED0_GPIO |
#define | DMACA_AES_EVAL_LED2 LED1_GPIO |
#define | DMACA_AES_EVAL_LED3 LED2_GPIO |
#define | DMACA_AES_EVAL_USART (&AVR32_USART1) |
#define | DMACA_AES_EVAL_USART_BAUDRATE 57600 |
#define | DMACA_AES_EVAL_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION |
#define | DMACA_AES_EVAL_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN |
#define | DMACA_AES_EVAL_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION |
#define | DMACA_AES_EVAL_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN |
Functions | |
static void | init_hmatrix (void) |
Initializes the HSB bus matrix. | |
int | main (void) |
The main function. | |
void | test_ram_aes_ram (unsigned short int u16BufferSize, unsigned int *pSrcBuf, unsigned int *pDstBuf) |
1) Configure two DMACA channels:
| |
Variables | |
volatile unsigned int | ccountt0 |
volatile unsigned int | ccountt1 |
const unsigned int | CipherKey [8] |
const unsigned int | InitVector [4] |
unsigned int | InputData [DMACA_AES_EVAL_BUF_SIZE] |
volatile unsigned int | OutputData [DMACA_AES_EVAL_BUF_SIZE] |
volatile unsigned int * | pDstData_HsbSram |
pm_freq_param_t | pm_freq_param |
unsigned int * | pSrcData_HsbSram |
const unsigned int | RefInputData [DMACA_AES_EVAL_REFBUF_SIZE] |
const unsigned int | RefOutputData [DMACA_AES_EVAL_REFBUF_SIZE] |
#define DMACA_AES_EVAL_BUF_SIZE 256 |
#define DMACA_AES_EVAL_LED1 LED0_GPIO |
#define DMACA_AES_EVAL_LED2 LED1_GPIO |
#define DMACA_AES_EVAL_LED3 LED2_GPIO |
#define DMACA_AES_EVAL_REFBUF_SIZE 16 |
#define DMACA_AES_EVAL_USART (&AVR32_USART1) |
#define DMACA_AES_EVAL_USART_BAUDRATE 57600 |
#define DMACA_AES_EVAL_USART_RX_FUNCTION AVR32_USART1_RXD_0_0_FUNCTION |
#define DMACA_AES_EVAL_USART_RX_PIN AVR32_USART1_RXD_0_0_PIN |
#define DMACA_AES_EVAL_USART_TX_FUNCTION AVR32_USART1_TXD_0_0_FUNCTION |
#define DMACA_AES_EVAL_USART_TX_PIN AVR32_USART1_TXD_0_0_PIN |
static void init_hmatrix | ( | void | ) | [static] |
Initializes the HSB bus matrix.
Definition at line 387 of file ram_aes_ram_example.c.
Referenced by main().
00388 { 00389 // Set flashc master type to last default to save one cycle for 00390 // each branch. 00391 avr32_hmatrix_scfg_t scfg; 00392 00393 scfg = AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_FLASH]; 00394 scfg.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT; 00395 AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_FLASH] = scfg; 00396 00397 scfg = AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_AES]; 00398 scfg.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT; 00399 AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_AES] = scfg; 00400 00401 scfg = AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_SRAM]; 00402 scfg.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT; 00403 AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_SRAM] = scfg; 00404 00405 scfg = AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_EMBEDDED_SYS_SRAM_0]; 00406 scfg.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT; 00407 AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_EMBEDDED_SYS_SRAM_0] = scfg; 00408 00409 scfg = AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_EMBEDDED_SYS_SRAM_1]; 00410 scfg.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT; 00411 AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_EMBEDDED_SYS_SRAM_1] = scfg; 00412 }
int main | ( | void | ) |
The main function.
It sets up the USART module on EXAMPLE_USART. The terminal settings are 57600 8N1. Then it sets up the interrupt handler and waits for a USART interrupt to trigger.
Definition at line 422 of file ram_aes_ram_example.c.
References DMACA_AES_EVAL_BUF_SIZE, DMACA_AES_EVAL_LED1, DMACA_AES_EVAL_LED2, DMACA_AES_EVAL_LED3, DMACA_AES_EVAL_REFBUF_SIZE, DMACA_AES_EVAL_USART, DMACA_AES_EVAL_USART_BAUDRATE, DMACA_AES_EVAL_USART_RX_FUNCTION, DMACA_AES_EVAL_USART_RX_PIN, DMACA_AES_EVAL_USART_TX_FUNCTION, DMACA_AES_EVAL_USART_TX_PIN, init_hmatrix(), InputData, OutputData, pDstData_HsbSram, pm_freq_param, pSrcData_HsbSram, RefInputData, and test_ram_aes_ram().
00423 { 00424 aes_config_t AesConf; // AES config structure 00425 int i; 00426 static const gpio_map_t USART_GPIO_MAP = // USART GPIO map 00427 { 00428 {DMACA_AES_EVAL_USART_RX_PIN, DMACA_AES_EVAL_USART_RX_FUNCTION}, 00429 {DMACA_AES_EVAL_USART_TX_PIN, DMACA_AES_EVAL_USART_TX_FUNCTION} 00430 }; 00431 static const usart_options_t USART_OPTIONS = // USART options. 00432 { 00433 .baudrate = DMACA_AES_EVAL_USART_BAUDRATE, 00434 .charlength = 8, 00435 .paritytype = USART_NO_PARITY, 00436 .stopbits = USART_1_STOPBIT, 00437 .channelmode = USART_NORMAL_CHMODE 00438 }; 00439 00440 00441 #if BOARD == EVK1104 00442 if( PM_FREQ_STATUS_FAIL==pm_configure_clocks(&pm_freq_param) ) 00443 while(1); 00444 #endif 00445 00446 init_hmatrix(); 00447 00448 // Assign GPIO to USART. 00449 gpio_enable_module(USART_GPIO_MAP, 00450 sizeof(USART_GPIO_MAP) / sizeof(USART_GPIO_MAP[0])); 00451 00452 // Initialize USART in RS232 mode. 00453 usart_init_rs232(DMACA_AES_EVAL_USART, &USART_OPTIONS, DMACA_AES_EVAL_CPU_FREQ); 00454 print(DMACA_AES_EVAL_USART, "\x1B[2J\x1B[H.: Using the AES with the DMACA at "); 00455 print_ulong(DMACA_AES_EVAL_USART, DMACA_AES_EVAL_CPU_FREQ); 00456 print(DMACA_AES_EVAL_USART, "Hz :.\n\n"); 00457 00458 //**************************************************************************** 00459 // CIPHER IN DMA MODE: RAM -> AES -> RAM 00460 // - 256bit cryptographic key 00461 // - CBC cipher mode 00462 // - No counter measures 00463 //**************************************************************************** 00464 00465 // Init the input array. 00466 for(i=0; i<DMACA_AES_EVAL_BUF_SIZE; i+=DMACA_AES_EVAL_REFBUF_SIZE) 00467 { 00468 memcpy(InputData+i, RefInputData, DMACA_AES_EVAL_REFBUF_SIZE*sizeof(unsigned int)); 00469 } 00470 00471 //==================== 00472 // Configure the AES. 00473 //==================== 00474 AesConf.ProcessingMode = AES_PMODE_CIPHER; // Cipher 00475 AesConf.ProcessingDelay = 0; // No delay: best performance 00476 AesConf.StartMode = AES_START_MODE_DMA; // DMA mode 00477 AesConf.KeySize = AES_KEY_SIZE_256; // 256bit cryptographic key 00478 AesConf.OpMode = AES_CBC_MODE; // CBC cipher mode 00479 AesConf.LodMode = 0; // LODMODE == 0 : the end of the 00480 // encryption is notified by the DMACA transfer complete interrupt. The output 00481 // is available in the OutputData[] buffer. 00482 AesConf.CFBSize = 0; // Don't-care because we're using the CBC mode. 00483 AesConf.CounterMeasureMask = 0; // Disable all counter measures. 00484 aes_configure(&AVR32_AES, &AesConf); 00485 00486 00487 //**************************************************************************** 00488 // - input of 16 32bit words in CPUSRAM 00489 // - output of 16 32bit words in CPUSRAM 00490 //**************************************************************************** 00491 print(DMACA_AES_EVAL_USART, "\n---------------------------------------------------\n"); 00492 print(DMACA_AES_EVAL_USART, "------ Cipher in DMA Mode: CPUSRAM -> AES -> CPUSRAM ------\n"); 00493 print(DMACA_AES_EVAL_USART, " - 256bit cryptographic key\n"); 00494 print(DMACA_AES_EVAL_USART, " - CBC cipher mode\n"); 00495 print(DMACA_AES_EVAL_USART, " - No counter measures\n"); 00496 print(DMACA_AES_EVAL_USART, " - input of 16 32bit words in CPUSRAM\n"); 00497 print(DMACA_AES_EVAL_USART, " - output of 16 32bit words in CPUSRAM\n"); 00498 print(DMACA_AES_EVAL_USART, "---------------------------------------------------\n"); 00499 00500 test_ram_aes_ram(16, (unsigned int *)InputData, (unsigned int *)OutputData); 00501 gpio_clr_gpio_pin(DMACA_AES_EVAL_LED1); 00502 00503 //**************************************************************************** 00504 // - input of 256 32bit words in CPUSRAM 00505 // - output of 256 32bit words in CPUSRAM 00506 //**************************************************************************** 00507 print(DMACA_AES_EVAL_USART, "\n---------------------------------------------------\n"); 00508 print(DMACA_AES_EVAL_USART, "------ Cipher in DMA Mode: CPUSRAM -> AES -> CPUSRAM ------\n"); 00509 print(DMACA_AES_EVAL_USART, " - 256bit cryptographic key\n"); 00510 print(DMACA_AES_EVAL_USART, " - CBC cipher mode\n"); 00511 print(DMACA_AES_EVAL_USART, " - No counter measures\n"); 00512 print(DMACA_AES_EVAL_USART, " - input of 256 32bit words in CPUSRAM\n"); 00513 print(DMACA_AES_EVAL_USART, " - output of 256 32bit words in CPUSRAM\n"); 00514 print(DMACA_AES_EVAL_USART, "---------------------------------------------------\n"); 00515 00516 test_ram_aes_ram(256, (unsigned int *)InputData, (unsigned int *)OutputData); 00517 gpio_clr_gpio_pin(DMACA_AES_EVAL_LED2); 00518 00519 //**************************************************************************** 00520 // - input of 256 32bit words in HSBSRAM0 00521 // - output of 256 32bit words in HSBSRAM1 00522 //**************************************************************************** 00523 print(DMACA_AES_EVAL_USART, "\n---------------------------------------------------\n"); 00524 print(DMACA_AES_EVAL_USART, "------ Cipher in DMA Mode: HSBSRAM0 -> AES -> HSBSRAM1 ------\n"); 00525 print(DMACA_AES_EVAL_USART, " - 256bit cryptographic key\n"); 00526 print(DMACA_AES_EVAL_USART, " - CBC cipher mode\n"); 00527 print(DMACA_AES_EVAL_USART, " - No counter measures\n"); 00528 print(DMACA_AES_EVAL_USART, " - input of 256 32bit words in HSBSRAM0\n"); 00529 print(DMACA_AES_EVAL_USART, " - output of 256 32bit words in HSBSRAM1\n"); 00530 print(DMACA_AES_EVAL_USART, "---------------------------------------------------\n"); 00531 00532 // Set the Src and Dst array addresses to respectively HSBSRAM0 & HSBRAM1. 00533 pSrcData_HsbSram = (unsigned int *)AVR32_INTRAM0_ADDRESS; 00534 pDstData_HsbSram = (unsigned int *)AVR32_INTRAM1_ADDRESS; 00535 // Init the input array. 00536 for(i=0; i<DMACA_AES_EVAL_BUF_SIZE; i+=DMACA_AES_EVAL_REFBUF_SIZE) 00537 { 00538 memcpy(pSrcData_HsbSram+i, RefInputData, DMACA_AES_EVAL_REFBUF_SIZE*sizeof(unsigned int)); 00539 } 00540 00541 test_ram_aes_ram(256, pSrcData_HsbSram, (unsigned int *)pDstData_HsbSram); 00542 gpio_clr_gpio_pin(DMACA_AES_EVAL_LED3); 00543 print(DMACA_AES_EVAL_USART, "\r\nDone!"); 00544 00545 // End of tests: go to sleep. 00546 SLEEP(AVR32_PM_SMODE_STATIC); 00547 while (TRUE); 00548 }
void test_ram_aes_ram | ( | unsigned short int | u16BufferSize, | |
unsigned int * | pSrcBuf, | |||
unsigned int * | pDstBuf | |||
) |
1) Configure two DMACA channels:
3) Start the process 4) Check the result on the first 16 Words.
Definition at line 214 of file ram_aes_ram_example.c.
References ccountt0, ccountt1, CipherKey, DMACA_AES_EVAL_REFBUF_SIZE, DMACA_AES_EVAL_USART, InitVector, OutputData, and RefOutputData.
Referenced by main().
00215 { 00216 unsigned int i; 00217 unsigned char TestResult = TRUE; 00218 00219 00220 //==================== 00221 // Configure the DMACA. 00222 //==================== 00223 // Enable the DMACA 00224 AVR32_DMACA.dmacfgreg = 1 << AVR32_DMACA_DMACFGREG_DMA_EN_OFFSET; 00225 00226 //* 00227 //* Configure the DMA RAM -> AES channel. 00228 //* 00229 // ------------+--------+------+------------+--------+-------+---------------- 00230 // Transfer | Source | Dest | Flow | Width | Chunk | Buffer 00231 // type | | | controller | (bits) | size | Size 00232 // ------------+--------+------+------------+--------+-------+---------------- 00233 // | | | | | | 00234 // Mem-to-Per | RAM | AES | DMACA | 32 | 4 | u16BufferSize 00235 // | | | | | | 00236 // ------------+--------+------+------------+--------+-------+---------------- 00237 // NOTE: We arbitrarily choose to use channel 0 for this datapath 00238 00239 // Src Address: the InputData[] array 00240 AVR32_DMACA.sar0 = (unsigned long)pSrcBuf; 00241 00242 // Dst Address: the AES_IDATAXR registers. 00243 AVR32_DMACA.dar0 = (AVR32_AES_ADDRESS | AVR32_AES_IDATA1R); 00244 00245 // Linked list ptrs: not used. 00246 AVR32_DMACA.llp0 = 0x00000000; 00247 00248 // Channel 0 Ctrl register low 00249 AVR32_DMACA.ctl0l = 00250 (0 << AVR32_DMACA_CTL0L_INT_EN_OFFSET) | // Do not enable interrupts 00251 (2 << AVR32_DMACA_CTL0L_DST_TR_WIDTH_OFFSET) | // Dst transfer width: 32 bits 00252 (2 << AVR32_DMACA_CTL0L_SRC_TR_WIDTH_OFFSET) | // Src transfer width: 32 bits 00253 (2 << AVR32_DMACA_CTL0L_DINC_OFFSET) | // Dst address increment: none 00254 (0 << AVR32_DMACA_CTL0L_SINC_OFFSET) | // Src address increment: increment 00255 (1 << AVR32_DMACA_CTL0L_DST_MSIZE_OFFSET) | // Dst burst transaction len: 4 data items 00256 (1 << AVR32_DMACA_CTL0L_SRC_MSIZE_OFFSET) | // Src burst transaction len: 4 data items 00257 (0 << AVR32_DMACA_CTL0L_S_GATH_EN_OFFSET) | // Source gather: disabled 00258 (0 << AVR32_DMACA_CTL0L_D_SCAT_EN_OFFSET) | // Destination scatter: disabled 00259 (1 << AVR32_DMACA_CTL0L_TT_FC_OFFSET) | // transfer type:M2P, flow controller: DMACA 00260 (0 << AVR32_DMACA_CTL0L_DMS_OFFSET) | // Dest master: HSB master 1 00261 (1 << AVR32_DMACA_CTL0L_SMS_OFFSET) | // Source master: HSB master 2 00262 (0 << AVR32_DMACA_CTL0L_LLP_D_EN_OFFSET) | // Not used 00263 (0 << AVR32_DMACA_CTL0L_LLP_S_EN_OFFSET) // Not used 00264 ; 00265 00266 // Channel 0 Ctrl register high 00267 AVR32_DMACA.ctl0h = 00268 (u16BufferSize << AVR32_DMACA_CTL0H_BLOCK_TS_OFFSET) | // Block transfer size 00269 (0 << AVR32_DMACA_CTL0H_DONE_OFFSET) // Not done 00270 ; 00271 00272 // Channel 0 Config register low 00273 AVR32_DMACA.cfg0l = 00274 (0 << AVR32_DMACA_CFG0L_HS_SEL_DST_OFFSET) | // Destination handshaking: hw handshaking 00275 (0 << AVR32_DMACA_CFG0L_HS_SEL_SRC_OFFSET) // Source handshaking: ignored because the src is memory. 00276 ; // All other bits set to 0. 00277 00278 // Channel 0 Config register high 00279 AVR32_DMACA.cfg0h = 00280 (AVR32_DMACA_CH_AES_TX << AVR32_DMACA_CFG0H_DEST_PER_OFFSET) | // Dest hw handshaking itf: 00281 (0 << AVR32_DMACA_CFG0H_SRC_PER_OFFSET) // Source hw handshaking itf: ignored because the src is memory. 00282 ; // All other bits set to 0. 00283 00284 00285 //* 00286 //* Configure the DMA AES -> RAM channel. 00287 //* 00288 // ------------+--------+------+------------+--------+-------+---------------- 00289 // Transfer | Source | Dest | Flow | Width | Chunk | Buffer 00290 // type | | | controller | (bits) | size | Size 00291 // ------------+--------+------+------------+--------+-------+---------------- 00292 // | | | | | | 00293 // Per-to-Mem | AES | RAM | DMACA | 32 | 4 | u16BufferSize 00294 // | | | | | | 00295 // ------------+--------+------+------------+--------+-------+---------------- 00296 // NOTE: We arbitrarily choose to use channel 1 for this datapath 00297 00298 // Src Address: the AES_ODATAXR registers. 00299 AVR32_DMACA.sar1 = (AVR32_AES_ADDRESS | AVR32_AES_ODATA1R); 00300 00301 // Dst Address: the OutputData[] array. 00302 AVR32_DMACA.dar1 = (unsigned long)pDstBuf; 00303 00304 // Linked list ptrs: not used. 00305 AVR32_DMACA.llp1 = 0x00000000; 00306 00307 // Channel 1 Ctrl register low 00308 AVR32_DMACA.ctl1l = 00309 (0 << AVR32_DMACA_CTL1L_INT_EN_OFFSET) | // Do not enable interrupts 00310 (2 << AVR32_DMACA_CTL1L_DST_TR_WIDTH_OFFSET) | // Dst transfer width: 32 bits 00311 (2 << AVR32_DMACA_CTL1L_SRC_TR_WIDTH_OFFSET) | // Src transfer width: 32 bits 00312 (0 << AVR32_DMACA_CTL1L_DINC_OFFSET) | // Dst address increment: increment 00313 (2 << AVR32_DMACA_CTL1L_SINC_OFFSET) | // Src address increment: none 00314 (1 << AVR32_DMACA_CTL1L_DST_MSIZE_OFFSET) | // Dst burst transaction len: 4 data items 00315 (1 << AVR32_DMACA_CTL1L_SRC_MSIZE_OFFSET) | // Src burst transaction len: 4 data items 00316 (0 << AVR32_DMACA_CTL1L_S_GATH_EN_OFFSET) | // Source gather: disabled 00317 (0 << AVR32_DMACA_CTL1L_D_SCAT_EN_OFFSET) | // Destination scatter: disabled 00318 (2 << AVR32_DMACA_CTL1L_TT_FC_OFFSET) | // transfer type:P2M, flow controller: DMACA 00319 (1 << AVR32_DMACA_CTL1L_DMS_OFFSET) | // Dest master: HSB master 2 00320 (0 << AVR32_DMACA_CTL1L_SMS_OFFSET) | // Source master: HSB master 1 00321 (0 << AVR32_DMACA_CTL1L_LLP_D_EN_OFFSET) | // Not used 00322 (0 << AVR32_DMACA_CTL1L_LLP_S_EN_OFFSET) // Not used 00323 ; 00324 00325 // Channel 1 Ctrl register high 00326 AVR32_DMACA.ctl1h = 00327 (u16BufferSize << AVR32_DMACA_CTL1H_BLOCK_TS_OFFSET) | // Block transfer size 00328 (0 << AVR32_DMACA_CTL1H_DONE_OFFSET) // Not done 00329 ; 00330 00331 // Channel 1 Config register low 00332 AVR32_DMACA.cfg1l = 00333 (0 << AVR32_DMACA_CFG1L_HS_SEL_DST_OFFSET) | // Destination handshaking: hw handshaking 00334 (0 << AVR32_DMACA_CFG1L_HS_SEL_SRC_OFFSET) // Source handshaking: ignored because the src is memory. 00335 ; // All other bits set to 0. 00336 00337 // Channel 1 Config register high 00338 AVR32_DMACA.cfg1h = 00339 (0 << AVR32_DMACA_CFG1H_DEST_PER_OFFSET) | // Dest hw handshaking itf: ignored because the dst is memory. 00340 (AVR32_DMACA_CH_AES_RX << AVR32_DMACA_CFG1H_SRC_PER_OFFSET) // Source hw handshaking itf: 00341 ; // All other bits set to 0. 00342 00343 00344 //* 00345 //* Set the AES cryptographic key and init vector. 00346 //* 00347 // Set the cryptographic key. 00348 aes_set_key(&AVR32_AES, CipherKey); 00349 00350 // Set the initialization vector. 00351 aes_set_initvector(&AVR32_AES, InitVector); 00352 00353 //* 00354 //* Start the process 00355 //* 00356 ccountt0 = Get_system_register(AVR32_COUNT); 00357 00358 // Enable Channel 0 & 1 : start the process. 00359 AVR32_DMACA.chenreg = ((3<<AVR32_DMACA_CHENREG_CH_EN_OFFSET) | (3<<AVR32_DMACA_CHENREG_CH_EN_WE_OFFSET)); 00360 00361 // Wait for the end of the AES->RAM transfer (channel 1). 00362 while(AVR32_DMACA.chenreg & (2<<AVR32_DMACA_CHENREG_CH_EN_OFFSET)); 00363 00364 ccountt1 = Get_system_register(AVR32_COUNT); 00365 00366 // Check the results of the encryption. 00367 for(i=0; i<DMACA_AES_EVAL_REFBUF_SIZE; i++) 00368 { 00369 if(OutputData[i] != RefOutputData[i]) 00370 { 00371 TestResult = FALSE; 00372 break; 00373 } 00374 } 00375 if(FALSE == TestResult) 00376 print(DMACA_AES_EVAL_USART, "KO!!!\n"); 00377 else 00378 { 00379 print(DMACA_AES_EVAL_USART, "OK!!! Nb cycles: "); 00380 print_ulong(DMACA_AES_EVAL_USART, ccountt1 - ccountt0); 00381 } 00382 }
volatile unsigned int ccountt0 |
Definition at line 196 of file ram_aes_ram_example.c.
Referenced by test_ram_aes_ram(), and test_ram_to_ram().
volatile unsigned int ccountt1 |
Definition at line 196 of file ram_aes_ram_example.c.
Referenced by test_ram_aes_ram(), and test_ram_to_ram().
const unsigned int CipherKey[8] |
Initial value:
{ 0x603deb10, 0x15ca71be, 0x2b73aef0, 0x857d7781, 0x1f352c07, 0x3b6108d7, 0x2d9810a3, 0x0914dff4 }
Definition at line 151 of file ram_aes_ram_example.c.
Referenced by test_ram_aes_ram().
const unsigned int InitVector[4] |
Initial value:
{ 0x00010203, 0x04050607, 0x08090a0b, 0x0c0d0e0f }
Definition at line 164 of file ram_aes_ram_example.c.
Referenced by test_ram_aes_ram().
unsigned int InputData[DMACA_AES_EVAL_BUF_SIZE] |
volatile unsigned int OutputData[DMACA_AES_EVAL_BUF_SIZE] |
volatile unsigned int* pDstData_HsbSram |
pm_freq_param_t pm_freq_param |
Initial value:
{ .cpu_f = DMACA_AES_EVAL_CPU_FREQ, .pba_f = DMACA_AES_EVAL_CPU_FREQ, .osc0_f = FOSC0, .osc0_startup = OSC0_STARTUP }
Definition at line 198 of file ram_aes_ram_example.c.
Referenced by main().
unsigned int* pSrcData_HsbSram |
const unsigned int RefInputData[DMACA_AES_EVAL_REFBUF_SIZE] |
Initial value:
{ 0x6bc1bee2, 0x2e409f96, 0xe93d7e11, 0x7393172a, 0xae2d8a57, 0x1e03ac9c, 0x9eb76fac, 0x45af8e51, 0x30c81c46, 0xa35ce411, 0xe5fbc119, 0x1a0a52ef, 0xf69f2445, 0xdf4f9b17, 0xad2b417b, 0xe66c3710 }
Definition at line 131 of file ram_aes_ram_example.c.
Referenced by main().
const unsigned int RefOutputData[DMACA_AES_EVAL_REFBUF_SIZE] |
Initial value:
{ 0xf58c4c04, 0xd6e5f1ba, 0x779eabfb, 0x5f7bfbd6, 0x9cfc4e96, 0x7edb808d, 0x679f777b, 0xc6702c7d, 0x39f23369, 0xa9d9bacf, 0xa530e263, 0x04231461, 0xb2eb05e2, 0xc39be9fc, 0xda6c1907, 0x8c6a9d1b }
Definition at line 172 of file ram_aes_ram_example.c.
Referenced by test_ram_aes_ram().