ram_to_ram_example.c File Reference


Detailed Description

DMACA RAM -> RAM evaluation for AVR32 UC3.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file ram_to_ram_example.c.

#include <string.h>
#include "board.h"
#include "print_funcs.h"
#include "gpio.h"
#include "pm.h"
#include "intc.h"
#include "usart.h"

Go to the source code of this file.

Defines

#define DMACA_RAM2RAM_EVAL_BUF_SIZE   256
Board-Related Example Settings
#define DMACA_RAM2RAM_EVAL_LED1   LED0_GPIO
#define DMACA_RAM2RAM_EVAL_LED2   LED1_GPIO
#define DMACA_RAM2RAM_EVAL_LED3   LED2_GPIO
#define DMACA_RAM2RAM_EVAL_LED4   LED3_GPIO
#define DMACA_RAM2RAM_EVAL_USART   (&AVR32_USART1)
#define DMACA_RAM2RAM_EVAL_USART_BAUDRATE   57600
#define DMACA_RAM2RAM_EVAL_USART_RX_FUNCTION   AVR32_USART1_RXD_0_0_FUNCTION
#define DMACA_RAM2RAM_EVAL_USART_RX_PIN   AVR32_USART1_RXD_0_0_PIN
#define DMACA_RAM2RAM_EVAL_USART_TX_FUNCTION   AVR32_USART1_TXD_0_0_FUNCTION
#define DMACA_RAM2RAM_EVAL_USART_TX_PIN   AVR32_USART1_TXD_0_0_PIN
Example internal states
#define DMACA_RAM2RAM_EVAL_STATE_1   0
#define DMACA_RAM2RAM_EVAL_STATE_2   1
#define DMACA_RAM2RAM_EVAL_STATE_3   2
#define DMACA_RAM2RAM_EVAL_STATE_4   3

Functions

static void dmaca_errint_handler (void)
 The DMACA Error interrupt handler.
static void dmaca_tfrint_handler (void)
 The DMACA Transfer Complete interrupt handler.
static void init_hmatrix (void)
 Initializes the HSB bus matrix.
int main (void)
 The main function.
void test_ram_to_ram (unsigned short int u16BufferSize, unsigned int *pSrcBuf, unsigned int *pDstBuf)
 1) Configure one DMACA channel:
  • SrcRAM -> DstRAM 3) Start the process 4) Check the result (dst == src)


Variables

volatile unsigned int ccountt0
volatile unsigned int ccountt1 = 0
volatile unsigned int DstData_CpuSram [DMACA_RAM2RAM_EVAL_BUF_SIZE]
volatile unsigned int * pDstData_HsbSram
pm_freq_param_t pm_freq_param
unsigned int * pSrcData_HsbSram
unsigned int SrcData_CpuSram [DMACA_RAM2RAM_EVAL_BUF_SIZE]
volatile unsigned char state = 0
volatile unsigned long Tempo


Define Documentation

#define DMACA_RAM2RAM_EVAL_BUF_SIZE   256

Definition at line 138 of file ram_to_ram_example.c.

Referenced by main(), and test_ram_to_ram().

#define DMACA_RAM2RAM_EVAL_LED1   LED0_GPIO

Definition at line 109 of file ram_to_ram_example.c.

Referenced by dmaca_tfrint_handler().

#define DMACA_RAM2RAM_EVAL_LED2   LED1_GPIO

Definition at line 110 of file ram_to_ram_example.c.

Referenced by dmaca_errint_handler().

#define DMACA_RAM2RAM_EVAL_LED3   LED2_GPIO

Definition at line 111 of file ram_to_ram_example.c.

Referenced by dmaca_tfrint_handler().

#define DMACA_RAM2RAM_EVAL_LED4   LED3_GPIO

Definition at line 112 of file ram_to_ram_example.c.

Referenced by dmaca_errint_handler().

#define DMACA_RAM2RAM_EVAL_STATE_1   0

Definition at line 132 of file ram_to_ram_example.c.

#define DMACA_RAM2RAM_EVAL_STATE_2   1

Definition at line 133 of file ram_to_ram_example.c.

#define DMACA_RAM2RAM_EVAL_STATE_3   2

Definition at line 134 of file ram_to_ram_example.c.

#define DMACA_RAM2RAM_EVAL_STATE_4   3

Definition at line 135 of file ram_to_ram_example.c.

#define DMACA_RAM2RAM_EVAL_USART   (&AVR32_USART1)

Definition at line 103 of file ram_to_ram_example.c.

Referenced by main(), and test_ram_to_ram().

#define DMACA_RAM2RAM_EVAL_USART_BAUDRATE   57600

Definition at line 108 of file ram_to_ram_example.c.

Referenced by main().

#define DMACA_RAM2RAM_EVAL_USART_RX_FUNCTION   AVR32_USART1_RXD_0_0_FUNCTION

Definition at line 105 of file ram_to_ram_example.c.

Referenced by main().

#define DMACA_RAM2RAM_EVAL_USART_RX_PIN   AVR32_USART1_RXD_0_0_PIN

Definition at line 104 of file ram_to_ram_example.c.

Referenced by main().

#define DMACA_RAM2RAM_EVAL_USART_TX_FUNCTION   AVR32_USART1_TXD_0_0_FUNCTION

Definition at line 107 of file ram_to_ram_example.c.

Referenced by main().

#define DMACA_RAM2RAM_EVAL_USART_TX_PIN   AVR32_USART1_TXD_0_0_PIN

Definition at line 106 of file ram_to_ram_example.c.

Referenced by main().


Function Documentation

static void dmaca_errint_handler ( void   )  [static]

The DMACA Error interrupt handler.

Note:
The `__attribute__((__interrupt__))' (under GNU GCC for AVR32) and `__interrupt' (under IAR Embedded Workbench for Atmel AVR32) C function attributes are used to manage the `rete' instruction.

Definition at line 199 of file ram_to_ram_example.c.

References DMACA_RAM2RAM_EVAL_LED2, and DMACA_RAM2RAM_EVAL_LED4.

Referenced by main().

00200 {
00201   unsigned long int u32Status;
00202 
00203   // This interrupt should ideally not happen. If it does, the DMACA transfer is
00204   // cancelled and the channel is disabled.
00205 
00206   gpio_clr_gpio_pin(DMACA_RAM2RAM_EVAL_LED2); // Turn LED2 on.
00207   // Clear the DMACA Error interrupt for channel 2.
00208   AVR32_DMACA.clearerr = OK << AVR32_DMACA_CLEARERR_CLEAR2_OFFSET;
00209 
00210   // We can use the StatusInt register because we're using only one DMACA channel.
00211   u32Status = AVR32_DMACA.statusint;
00212   if(u32Status & (AVR32_DMACA_STATUSINT_DSTT_MASK | AVR32_DMACA_STATUSINT_SRCT_MASK | AVR32_DMACA_STATUSINT_BLOCK_MASK))
00213   { // Unexpected!!!
00214     gpio_clr_gpio_pin(DMACA_RAM2RAM_EVAL_LED4); // Turn LED4 on.
00215   }
00216 }

static void dmaca_tfrint_handler ( void   )  [static]

The DMACA Transfer Complete interrupt handler.

Note:
The `__attribute__((__interrupt__))' (under GNU GCC for AVR32) and `__interrupt' (under IAR Embedded Workbench for Atmel AVR32) C function attributes are used to manage the `rete' instruction.

Definition at line 171 of file ram_to_ram_example.c.

References DMACA_RAM2RAM_EVAL_LED1, and DMACA_RAM2RAM_EVAL_LED3.

Referenced by main().

00172 {
00173   unsigned long int u32Status;
00174 
00175   gpio_clr_gpio_pin(DMACA_RAM2RAM_EVAL_LED1); // Turn LED1 on.
00176   // Clear the DMA Transfer Complete interrupt for channel 2.
00177   AVR32_DMACA.cleartfr = OK << AVR32_DMACA_CLEARTFR_CLEAR2_OFFSET;
00178 
00179   // We can use the StatusInt register because we're using only one DMACA channel.
00180   u32Status = AVR32_DMACA.statusint;
00181   if(u32Status & (AVR32_DMACA_STATUSINT_DSTT_MASK | AVR32_DMACA_STATUSINT_SRCT_MASK | AVR32_DMACA_STATUSINT_BLOCK_MASK))
00182   { // Unexpected!!!
00183     gpio_clr_gpio_pin(DMACA_RAM2RAM_EVAL_LED3); // Turn LED3 on.
00184   }
00185 }

static void init_hmatrix ( void   )  [static]

Initializes the HSB bus matrix.

Definition at line 337 of file ram_to_ram_example.c.

00338 {
00339   // Set flashc master type to last default to save one cycle for
00340   // each branch.
00341   avr32_hmatrix_scfg_t scfg;
00342 
00343   scfg = AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_FLASH];
00344   scfg.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
00345   AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_FLASH] = scfg;
00346 
00347   scfg = AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_SRAM];
00348   scfg.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
00349   AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_SRAM] = scfg;
00350 
00351   scfg = AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_EMBEDDED_SYS_SRAM_0];
00352   scfg.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
00353   AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_EMBEDDED_SYS_SRAM_0] = scfg;
00354 
00355   scfg = AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_EMBEDDED_SYS_SRAM_1];
00356   scfg.defmstr_type = AVR32_HMATRIX_DEFMSTR_TYPE_LAST_DEFAULT;
00357   AVR32_HMATRIX.SCFG[AVR32_HMATRIX_SLAVE_EMBEDDED_SYS_SRAM_1] = scfg;
00358 }

int main ( void   ) 

The main function.

It sets up the USART module on EXAMPLE_USART. The terminal settings are 57600 8N1. Then it sets up the interrupt handler and waits for a USART interrupt to trigger.

Definition at line 368 of file ram_to_ram_example.c.

References dmaca_errint_handler(), DMACA_RAM2RAM_EVAL_BUF_SIZE, DMACA_RAM2RAM_EVAL_USART, DMACA_RAM2RAM_EVAL_USART_BAUDRATE, DMACA_RAM2RAM_EVAL_USART_RX_FUNCTION, DMACA_RAM2RAM_EVAL_USART_RX_PIN, DMACA_RAM2RAM_EVAL_USART_TX_FUNCTION, DMACA_RAM2RAM_EVAL_USART_TX_PIN, dmaca_tfrint_handler(), DstData_CpuSram, init_hmatrix(), pDstData_HsbSram, pm_freq_param, pSrcData_HsbSram, SrcData_CpuSram, and test_ram_to_ram().

00369 {
00370   int               i;
00371   static const gpio_map_t USART_GPIO_MAP =      // USART GPIO map
00372   {
00373     {DMACA_RAM2RAM_EVAL_USART_RX_PIN, DMACA_RAM2RAM_EVAL_USART_RX_FUNCTION},
00374     {DMACA_RAM2RAM_EVAL_USART_TX_PIN, DMACA_RAM2RAM_EVAL_USART_TX_FUNCTION}
00375   };
00376   static const usart_options_t USART_OPTIONS =  // USART options.
00377   {
00378     .baudrate     = DMACA_RAM2RAM_EVAL_USART_BAUDRATE,
00379     .charlength   = 8,
00380     .paritytype   = USART_NO_PARITY,
00381     .stopbits     = USART_1_STOPBIT,
00382     .channelmode  = USART_NORMAL_CHMODE
00383   };
00384 
00385 
00386 #if BOARD == EVK1104
00387   if( PM_FREQ_STATUS_FAIL==pm_configure_clocks(&pm_freq_param) )
00388     while(1);
00389 #endif
00390 
00391   init_hmatrix();
00392 
00393   // Assign GPIO to USART.
00394   gpio_enable_module(USART_GPIO_MAP,
00395                      sizeof(USART_GPIO_MAP) / sizeof(USART_GPIO_MAP[0]));
00396 
00397   // Initialize USART in RS232 mode.
00398   usart_init_rs232(DMACA_RAM2RAM_EVAL_USART, &USART_OPTIONS, DMACA_RAM2RAM_EVAL_CPU_FREQ);
00399   print(DMACA_RAM2RAM_EVAL_USART, "\x1B[2J\x1B[H.: RAM to RAM transfers with the DMACA at ");
00400   print_ulong(DMACA_RAM2RAM_EVAL_USART, DMACA_RAM2RAM_EVAL_CPU_FREQ);
00401   print(DMACA_RAM2RAM_EVAL_USART, "Hz :.\n\n");
00402 
00403   // Disable all interrupts.
00404   Disable_global_interrupt();
00405 
00406   // Initialize interrupt vectors.
00407   INTC_init_interrupts();
00408 
00409   // Register to two DMACA interrupts to the interrupt controller.
00410   // dmaca_tfrint_handler() is the interrupt handler for the Transfer Complete interrupt.
00411   // dmaca_errint_handler() is the interrupt handler for the Error interrupt.
00412   INTC_register_interrupt(&dmaca_tfrint_handler, AVR32_DMACA_TFR_IRQ, AVR32_INTC_INT0);
00413   INTC_register_interrupt(&dmaca_errint_handler, AVR32_DMACA_ERR_IRQ, AVR32_INTC_INT0);
00414 
00415   // Enable all interrupts.
00416   Enable_global_interrupt();
00417 
00418   // Init the input array.
00419   for(i=0; i<DMACA_RAM2RAM_EVAL_BUF_SIZE; i++)
00420     SrcData_CpuSram[i] = i;
00421 
00422   //****************************************************************************
00423   // DMACA transfer : CPUSRAM -> CPUSRAM
00424   //  - input of 256 32bit words in CPUSRAM
00425   //  - output of 256 32bit words in CPUSRAM
00426   //****************************************************************************
00427   print(DMACA_RAM2RAM_EVAL_USART, "\n---------------------------------------------------\n");
00428   print(DMACA_RAM2RAM_EVAL_USART, "------ DMACA transfer: CPUSRAM -> CPUSRAM ------\n");
00429   print(DMACA_RAM2RAM_EVAL_USART, "       - input of 256 32bit words in CPUSRAM\n");
00430   print(DMACA_RAM2RAM_EVAL_USART, "       - output of 256 32bit words in CPUSRAM\n");
00431   print(DMACA_RAM2RAM_EVAL_USART, "---------------------------------------------------\n");
00432 
00433   test_ram_to_ram(256, (unsigned int *)SrcData_CpuSram, (unsigned int *)DstData_CpuSram);
00434 
00435 
00436   //****************************************************************************
00437   // DMACA transfer : HSBSRAM0 -> HSBSRAM1
00438   //  - input of 256 32bit words in HSBSRAM0
00439   //  - output of 256 32bit words in HSBSRAM1
00440   //****************************************************************************
00441   print(DMACA_RAM2RAM_EVAL_USART, "\n---------------------------------------------------\n");
00442   print(DMACA_RAM2RAM_EVAL_USART, "------ DMACA transfer: HSBSRAM0 -> HSBSRAM1 ------\n");
00443   print(DMACA_RAM2RAM_EVAL_USART, "       - input of 256 32bit words in HSBSRAM0\n");
00444   print(DMACA_RAM2RAM_EVAL_USART, "       - output of 256 32bit words in HSBSRAM1\n");
00445   print(DMACA_RAM2RAM_EVAL_USART, "---------------------------------------------------\n");
00446 
00447   // Set the Src and Dst array addresses to respectively HSBSRAM0 & HSBRAM1.
00448   pSrcData_HsbSram = (unsigned int *)AVR32_INTRAM0_ADDRESS;
00449   pDstData_HsbSram = (unsigned int *)AVR32_INTRAM1_ADDRESS;
00450 
00451   // Init the input array.
00452   for(i=0; i<DMACA_RAM2RAM_EVAL_BUF_SIZE; i++)
00453     *(pSrcData_HsbSram+i) = i;
00454 
00455   test_ram_to_ram(256, (unsigned int *)pSrcData_HsbSram, (unsigned int *)pDstData_HsbSram);
00456 
00457 
00458   //****************************************************************************
00459   // DMACA transfer : CPUSRAM -> HSBSRAM1
00460   //  - input of 256 32bit words in CPUSRAM
00461   //  - output of 256 32bit words in HSBSRAM1
00462   //****************************************************************************
00463   print(DMACA_RAM2RAM_EVAL_USART, "\n---------------------------------------------------\n");
00464   print(DMACA_RAM2RAM_EVAL_USART, "------ DMACA transfer: CPUSRAM -> HSBSRAM1 ------\n");
00465   print(DMACA_RAM2RAM_EVAL_USART, "       - input of 256 32bit words in CPUSRAM\n");
00466   print(DMACA_RAM2RAM_EVAL_USART, "       - output of 256 32bit words in HSBSRAM1\n");
00467   print(DMACA_RAM2RAM_EVAL_USART, "---------------------------------------------------\n");
00468 
00469   // Clear the Dst array.
00470   memset((unsigned int *)pDstData_HsbSram, 0, DMACA_RAM2RAM_EVAL_BUF_SIZE*sizeof(unsigned int));
00471 
00472   test_ram_to_ram(256, (unsigned int *)SrcData_CpuSram, (unsigned int *)pDstData_HsbSram);
00473 
00474 
00475   //****************************************************************************
00476   // DMACA transfer : HSBSRAM0 -> CPUSRAM
00477   //  - input of 256 32bit words in HSBSRAM0
00478   //  - output of 256 32bit words in CPUSRAM
00479   //****************************************************************************
00480   print(DMACA_RAM2RAM_EVAL_USART, "\n---------------------------------------------------\n");
00481   print(DMACA_RAM2RAM_EVAL_USART, "------ DMACA transfer: HSBSRAM0 -> CPUSRAM ------\n");
00482   print(DMACA_RAM2RAM_EVAL_USART, "       - input of 256 32bit words in HSBSRAM0\n");
00483   print(DMACA_RAM2RAM_EVAL_USART, "       - output of 256 32bit words in CPUSRAM\n");
00484   print(DMACA_RAM2RAM_EVAL_USART, "---------------------------------------------------\n");
00485 
00486   // Clear the Dst array.
00487   memset((unsigned int *)DstData_CpuSram, 0, DMACA_RAM2RAM_EVAL_BUF_SIZE*sizeof(unsigned int));
00488 
00489   test_ram_to_ram(256, pSrcData_HsbSram, (unsigned int *)DstData_CpuSram);
00490 
00491   // End of test: go to sleep.
00492   SLEEP(AVR32_PM_SMODE_STATIC);
00493   while (TRUE);
00494 }

void test_ram_to_ram ( unsigned short int  u16BufferSize,
unsigned int *  pSrcBuf,
unsigned int *  pDstBuf 
)

1) Configure one DMACA channel:

  • SrcRAM -> DstRAM 3) Start the process 4) Check the result (dst == src)

Definition at line 223 of file ram_to_ram_example.c.

References ccountt0, ccountt1, DMACA_RAM2RAM_EVAL_BUF_SIZE, and DMACA_RAM2RAM_EVAL_USART.

Referenced by main().

00224 {
00225   unsigned int    i;
00226   unsigned char   TestResult = TRUE;
00227 
00228 
00229   //====================
00230   // Configure the DMACA.
00231   //====================
00232   // Enable the DMACA
00233   AVR32_DMACA.dmacfgreg = 1 << AVR32_DMACA_DMACFGREG_DMA_EN_OFFSET;
00234 
00235   //*
00236   //* Configure the DMA RAM -> RAM channel.
00237   //*
00238   // ------------+--------+--------+------------+--------+-------+----------------
00239   //  Transfer   | Source | Dest   | Flow       | Width  | Chunk | Buffer
00240   //  type       |        |        | controller | (bits) | size  | Size
00241   // ------------+--------+--------+------------+--------+-------+----------------
00242   //             |        |        |            |        |       |
00243   //  Mem-to-Mem | RamMem | RamMem |   DMACA    |   32   |   4   | u16BufferSize
00244   //             |        |        |            |        |       |
00245   // ------------+--------+--------+------------+--------+-------+----------------
00246   // NOTE: We'll use the DMACA channel 2.
00247 
00248   // Src Address: the pSrcBuf address
00249   AVR32_DMACA.sar2 = (unsigned long)pSrcBuf;
00250 
00251   // Dst Address: the pDstBuf address
00252   AVR32_DMACA.dar2 = (unsigned long)pDstBuf;
00253 
00254   // Linked list ptrs: not used.
00255   AVR32_DMACA.llp2 = 0x00000000;
00256 
00257   // Channel 2 Ctrl register low
00258   AVR32_DMACA.ctl2l =
00259     (1 << AVR32_DMACA_CTL2L_INT_EN_OFFSET)     |  // Enable interrupts
00260     (2<<AVR32_DMACA_CTL2L_DST_TR_WIDTH_OFFSET) |  // Dst transfer width: 32bit
00261     (2<<AVR32_DMACA_CTL2L_SRC_TR_WIDTH_OFFSET) |  // Src transfer width: 32bit
00262     (0<<AVR32_DMACA_CTL2L_DINC_OFFSET)         |  // Dst address increment: increment
00263     (0<<AVR32_DMACA_CTL2L_SINC_OFFSET)         |  // Src address increment: increment
00264     (1<<AVR32_DMACA_CTL2L_DST_MSIZE_OFFSET)    |  // Dst burst transaction len: 4 data items (each of size DST_TR_WIDTH)
00265     (1<<AVR32_DMACA_CTL2L_SRC_MSIZE_OFFSET)    |  // Src burst transaction len: 4 data items (each of size DST_TR_WIDTH)
00266     (0<<AVR32_DMACA_CTL2L_TT_FC_OFFSET)        |  // transfer type:M2M, flow controller: DMACA
00267     (1<<AVR32_DMACA_CTL2L_DMS_OFFSET)          |  // Destination master: HSB master 2
00268     (0<<AVR32_DMACA_CTL2L_SMS_OFFSET)          |  // Source master: HSB master 1
00269     (0<<AVR32_DMACA_CTL2L_LLP_D_EN_OFFSET)     |  // Not used
00270     (0<<AVR32_DMACA_CTL2L_LLP_S_EN_OFFSET)        // Not used
00271     ;
00272 
00273   // Channel 2 Ctrl register high
00274   AVR32_DMACA.ctl2h =
00275     (u16BufferSize << AVR32_DMACA_CTL2H_BLOCK_TS_OFFSET) | // Block transfer size
00276     (0             << AVR32_DMACA_CTL2H_DONE_OFFSET)       // Not done
00277     ;
00278 
00279   // Channel 2 Config register low
00280   AVR32_DMACA.cfg2l =
00281     (0 << AVR32_DMACA_CFG2L_HS_SEL_DST_OFFSET) | // Destination handshaking: ignored because the dst is memory
00282     (0 << AVR32_DMACA_CFG2L_HS_SEL_SRC_OFFSET)   // Source handshaking: ignored because the src is memory.
00283     ; // All other bits set to 0.
00284 
00285   // Channel 2 Config register high
00286   AVR32_DMACA.cfg2h =
00287     (0 << AVR32_DMACA_CFG2H_DEST_PER_OFFSET) | // Dest hw handshaking itf: ignored because the dst is memory.
00288     (0 << AVR32_DMACA_CFG2H_SRC_PER_OFFSET)    // Source hw handshaking itf: ignored because the src is memory.
00289     ; // All other bits set to 0.
00290 
00291   // Unmask the DMA Transfer Complete interrupt and the DMA Error for channel 2.
00292 #if DMACA_RAM2RAM_EVAL_TEST_INTERRUPTS
00293   AVR32_DMACA.masktfr =
00294     ( SET << AVR32_DMACA_MASKTFR_INT_M_WE2_OFFSET )   | // Set the Write-enable bit
00295     ( SET << AVR32_DMACA_MASKTFR_INT_MASK2_OFFSET)      // Unmask the Transfer Complete interrupt.
00296     ; // All other bits left unchanged.
00297   AVR32_DMACA.maskerr =
00298     ( SET << AVR32_DMACA_MASKERR_INT_M_WE2_OFFSET )   | // Set the Write-enable bit
00299     ( SET << AVR32_DMACA_MASKERR_INT_MASK2_OFFSET)      // Unmask the Error interrupt.
00300     ; // All other bits left unchanged.
00301 #endif
00302 
00303   //*
00304   //* Start the process
00305   //*
00306   ccountt0 = Get_system_register(AVR32_COUNT);
00307 
00308   // Enable Channel 2 : start the process.
00309   AVR32_DMACA.chenreg = ((4<<AVR32_DMACA_CHENREG_CH_EN_OFFSET) | (4<<AVR32_DMACA_CHENREG_CH_EN_WE_OFFSET));
00310 
00311   // Wait for the end of the RAM->RAM transfer (channel 2).
00312   while(AVR32_DMACA.chenreg & (4<<AVR32_DMACA_CHENREG_CH_EN_OFFSET));
00313 
00314   ccountt1 = Get_system_register(AVR32_COUNT);
00315 
00316   // Check the result (Dst == Src)
00317   for(i=0; i<DMACA_RAM2RAM_EVAL_BUF_SIZE; i++)
00318   {
00319     if(pDstBuf[i] != pSrcBuf[i])
00320     {
00321       TestResult = FALSE;
00322       break;
00323     }
00324   }
00325   if(FALSE == TestResult)
00326     print(DMACA_RAM2RAM_EVAL_USART, "KO!!!\n");
00327   else
00328   {
00329     print(DMACA_RAM2RAM_EVAL_USART, "OK!!! Nb cycles: ");
00330     print_ulong(DMACA_RAM2RAM_EVAL_USART, ccountt1 - ccountt0);
00331   }
00332 }


Variable Documentation

volatile unsigned int ccountt0

Definition at line 148 of file ram_to_ram_example.c.

volatile unsigned int ccountt1 = 0

Definition at line 148 of file ram_to_ram_example.c.

volatile unsigned int DstData_CpuSram[DMACA_RAM2RAM_EVAL_BUF_SIZE]

Definition at line 142 of file ram_to_ram_example.c.

Referenced by main().

volatile unsigned int* pDstData_HsbSram

Definition at line 144 of file ram_to_ram_example.c.

pm_freq_param_t pm_freq_param

Initial value:

{
  .cpu_f        = DMACA_RAM2RAM_EVAL_CPU_FREQ,
  .pba_f        = DMACA_RAM2RAM_EVAL_CPU_FREQ,
  .osc0_f       = FOSC0,
  .osc0_startup = OSC0_STARTUP
}

Definition at line 152 of file ram_to_ram_example.c.

unsigned int* pSrcData_HsbSram

Definition at line 143 of file ram_to_ram_example.c.

unsigned int SrcData_CpuSram[DMACA_RAM2RAM_EVAL_BUF_SIZE]

Definition at line 141 of file ram_to_ram_example.c.

Referenced by main().

volatile unsigned char state = 0

Definition at line 146 of file ram_to_ram_example.c.

volatile unsigned long Tempo

Definition at line 150 of file ram_to_ram_example.c.


Generated on Fri Feb 19 02:24:33 2010 for AVR32 UC3 - DMACA - RAM To RAM Example by  doxygen 1.5.5