00001
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046 #ifndef _SCIF_UC3C_H_
00047 #define _SCIF_UC3C_H_
00048
00049 #ifdef __cplusplus
00050 extern "C" {
00051 #endif
00052
00053 #include "compiler.h"
00054
00055
00056
00057 #ifdef AVR32_SCIF_101_H_INCLUDED
00058 #define AVR32_SCIF_OSCCTRL0_STARTUP_0_RCOSC 0x00000000
00059 #define AVR32_SCIF_OSCCTRL0_STARTUP_128_RCOSC 0x00000002
00060 #define AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC 0x00000006
00061 #define AVR32_SCIF_OSCCTRL0_STARTUP_2048_RCOSC 0x00000003
00062 #define AVR32_SCIF_OSCCTRL0_STARTUP_4096_RCOSC 0x00000004
00063 #define AVR32_SCIF_OSCCTRL0_STARTUP_64_RCOSC 0x00000001
00064 #define AVR32_SCIF_OSCCTRL0_STARTUP_8192_RCOSC 0x00000005
00065 #define AVR32_SCIF_OSCCTRL1_STARTUP_0_RCOSC 0x00000000
00066 #define AVR32_SCIF_OSCCTRL1_STARTUP_128_RCOSC 0x00000002
00067 #define AVR32_SCIF_OSCCTRL1_STARTUP_16384_RCOSC 0x00000006
00068 #define AVR32_SCIF_OSCCTRL1_STARTUP_2048_RCOSC 0x00000003
00069 #define AVR32_SCIF_OSCCTRL1_STARTUP_4096_RCOSC 0x00000004
00070 #define AVR32_SCIF_OSCCTRL1_STARTUP_64_RCOSC 0x00000001
00071 #define AVR32_SCIF_OSCCTRL1_STARTUP_8192_RCOSC 0x00000005
00072 #define AVR32_SCIF_OSCCTRL32_STARTUP_0_RCOSC 0x00000000
00073 #define AVR32_SCIF_OSCCTRL32_STARTUP_128_RCOSC 0x00000001
00074 #define AVR32_SCIF_OSCCTRL32_STARTUP_131072_RCOSC 0x00000005
00075 #define AVR32_SCIF_OSCCTRL32_STARTUP_16384_RCOSC 0x00000003
00076 #define AVR32_SCIF_OSCCTRL32_STARTUP_262144_RCOSC 0x00000006
00077 #define AVR32_SCIF_OSCCTRL32_STARTUP_524288_RCOSC 0x00000007
00078 #define AVR32_SCIF_OSCCTRL32_STARTUP_65536_RCOSC 0x00000004
00079 #define AVR32_SCIF_OSCCTRL32_STARTUP_8192_RCOSC 0x00000002
00080 #define AVR32_SCIF_OSCCTRL0_MODE_CRYSTAL 0x00000001
00081 #define AVR32_SCIF_OSCCTRL0_MODE_EXTCLK 0x00000000
00082 #define AVR32_SCIF_OSCCTRL0_GAIN_G0 0x00000000
00083 #define AVR32_SCIF_OSCCTRL0_GAIN_G1 0x00000001
00084 #define AVR32_SCIF_OSCCTRL0_GAIN_G2 0x00000002
00085 #define AVR32_SCIF_OSCCTRL0_GAIN_G3 0x00000003
00086 #define AVR32_SCIF_OSCCTRL1_GAIN_G0 0x00000000
00087 #define AVR32_SCIF_OSCCTRL1_GAIN_G1 0x00000001
00088 #define AVR32_SCIF_OSCCTRL1_GAIN_G2 0x00000002
00089 #define AVR32_SCIF_OSCCTRL1_GAIN_G3 0x00000003
00090 #define AVR32_SCIF_UNLOCK_KEY_VALUE 0x000000AA
00091 #define AVR32_SCIF_OSCCTRL_OSCEN_ENABLE 0x00000001
00092 #define AVR32_SCIF_OSCCTRL_OSCEN_DISABLE 0x00000000
00093 #define AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE 0x00000001
00094 #define AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE 0x00000000
00095 #endif
00096
00097
00099
00101 #define SCIF_EXT_CRYSTAL_MIN_FREQ_HZ 4000000
00103 #define SCIF_EXT_CRYSTAL_MAX_FREQ_HZ 20000000
00104
00106 typedef enum
00107 {
00108 SCIF_GCCTRL_SLOWCLOCK = AVR32_SCIF_GC_USES_CLK_SLOW,
00109 SCIF_GCCTRL_OSC32K = AVR32_SCIF_GC_USES_CLK_32,
00110 SCIF_GCCTRL_OSC0 = AVR32_SCIF_GC_USES_OSC0,
00111 SCIF_GCCTRL_OSC1 = AVR32_SCIF_GC_USES_OSC1,
00112 SCIF_GCCTRL_PLL0 = AVR32_SCIF_GC_USES_PLL0,
00113 SCIF_GCCTRL_PLL1 = AVR32_SCIF_GC_USES_PLL1,
00114 SCIF_GCCTRL_RC8M = AVR32_SCIF_GC_USES_RCOSC8,
00115 SCIF_GCCTRL_CPUCLOCK = AVR32_SCIF_GC_USES_CLK_CPU,
00116 SCIF_GCCTRL_HSBCLOCK = AVR32_SCIF_GC_USES_CLK_HSB,
00117 SCIF_GCCTRL_PBACLOCK = AVR32_SCIF_GC_USES_CLK_PBA,
00118 SCIF_GCCTRL_PBBCLOCK = AVR32_SCIF_GC_USES_CLK_PBB,
00119 SCIF_GCCTRL_OSCSEL_INVALID
00120 } scif_gcctrl_oscsel_t;
00121
00122
00123
00125 #define SCIF_POLL_TIMEOUT 100000
00126
00128 #define SCIF_NOT_SUPPORTED (-10000)
00129
00130
00132 typedef enum
00133 {
00134 SCIF_OSC0 = 0,
00135 SCIF_OSC1 = 1
00136 } scif_osc_t;
00137
00139 typedef enum
00140 {
00141 SCIF_PLL0 = 0,
00142 SCIF_PLL1 = 1
00143 } scif_pll_t;
00144
00146 typedef enum
00147 {
00148 SCIF_OSC_MODE_EXT_CLK = 0,
00149 SCIF_OSC_MODE_2PIN_CRYSTAL = 1,
00150 SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR = 2,
00151 } scif_osc_mode_t;
00152
00154 typedef struct
00155 {
00157 unsigned long freq_hz;
00159 scif_osc_mode_t mode;
00161 unsigned char startup;
00163 unsigned char gain;
00164 } scif_osc_opt_t;
00165
00167 typedef struct
00168 {
00170 unsigned char pll_freq;
00172 unsigned char pll_wbwdisable;
00174 unsigned char pll_div2;
00176 unsigned int mul;
00178 unsigned int div;
00180 unsigned int lockcount;
00182 unsigned char osc;
00183 } scif_pll_opt_t;
00184
00186 typedef struct
00187 {
00189 unsigned long freq_hz;
00191 scif_osc_mode_t mode;
00193 unsigned char startup;
00194 } scif_osc32_opt_t;
00195
00196
00198 typedef struct
00199 {
00201 scif_gcctrl_oscsel_t clock_source;
00203 unsigned int divider;
00205 unsigned int diven;
00206 } scif_gclk_opt_t;
00207
00208
00210 #define SCIF_UNLOCK(reg) (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg))
00211
00214
00215
00220 #if defined (__GNUC__)
00221 __attribute__((__always_inline__))
00222 #endif
00223 extern __inline__ void scif_enable_interrupts(unsigned long mask)
00224 {
00225 AVR32_SCIF.ier = mask;
00226 }
00227
00232 #if defined (__GNUC__)
00233 __attribute__((__always_inline__))
00234 #endif
00235 extern __inline__ void scif_disable_interrupts(unsigned long mask)
00236 {
00237 AVR32_SCIF.idr = mask;
00238 }
00239
00244 #if defined (__GNUC__)
00245 __attribute__((__always_inline__))
00246 #endif
00247 extern __inline__ unsigned long scif_get_enabled_interrupts(void)
00248 {
00249 return(AVR32_SCIF.imr);
00250 }
00251
00256 #if defined (__GNUC__)
00257 __attribute__((__always_inline__))
00258 #endif
00259 extern __inline__ unsigned long scif_get_interrupts_status(void)
00260 {
00261 return(AVR32_SCIF.isr);
00262 }
00263
00268 #if defined (__GNUC__)
00269 __attribute__((__always_inline__))
00270 #endif
00271 extern __inline__ void scif_clear_interrupts_status(unsigned long mask)
00272 {
00273 AVR32_SCIF.icr = mask;
00274 }
00275
00277
00278
00281
00282
00287 #if defined (__GNUC__)
00288 __attribute__((__always_inline__))
00289 #endif
00290 extern __inline__ unsigned long scif_get_pclk_status(void)
00291 {
00292 return(AVR32_SCIF.pclksr);
00293 }
00294
00296
00297
00300
00301
00315 extern long int scif_start_osc(scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready);
00316
00325 extern bool scif_is_osc_ready(scif_osc_t osc);
00326
00335 extern long int scif_stop_osc(scif_osc_t osc);
00336
00346 extern long int scif_configure_osc_crystalmode(scif_osc_t osc, unsigned int fcrystal);
00347
00356 extern long int scif_configure_osc_extmode(scif_osc_t osc);
00357
00368 extern long int scif_enable_osc(scif_osc_t osc, unsigned int startup, bool wait_for_ready);
00369
00378 extern long int scif_enable_extosc(scif_osc_t osc);
00379
00381
00382
00385
00386
00395 extern long int scif_pll_setup(scif_pll_t pll, const scif_pll_opt_t opt);
00396
00404 extern long int scif_pll_enable(scif_pll_t pll);
00405
00406
00414 extern long int scif_pll_disable(scif_pll_t pll);
00415
00416
00424 extern long int scif_wait_for_pll_locked(scif_pll_t pll);
00425
00427
00430
00431
00444 extern long int scif_start_osc32(const scif_osc32_opt_t *opt, bool wait_for_ready);
00445
00452 #if defined (__GNUC__)
00453 __attribute__((__always_inline__))
00454 #endif
00455 extern __inline__ bool scif_is_osc32_ready()
00456 {
00457 return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC32RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC32RDY_OFFSET);
00458 }
00459
00460
00467 extern long int scif_stop_osc32();
00468
00470
00471
00474
00475
00479 extern void scif_bod18_enable_irq(void);
00480
00481
00485 extern void scif_bod18_disable_irq(void);
00486
00487
00491 extern void scif_bod18_clear_irq(void);
00492
00493
00500 extern unsigned long scif_bod18_get_irq_status(void);
00501
00502
00509 extern unsigned long scif_bod18_get_irq_enable_bit(void);
00510
00511
00515 extern unsigned long scif_bod18_get_level(void);
00516
00517
00521 extern void scif_bod33_enable_irq(void);
00522
00523
00527 extern void scif_bod33_disable_irq(void);
00528
00529
00533 extern void scif_bod33_clear_irq(void);
00534
00535
00542 extern unsigned long scif_bod33_get_irq_status(void);
00543
00544
00551 extern unsigned long scif_bod33_get_irq_enable_bit(void);
00552
00553
00557 extern unsigned long scif_bod33_get_level(void);
00558
00562 extern void scif_bod50_enable_irq(void);
00563
00564
00568 extern void scif_bod50_disable_irq(void);
00569
00570
00574 extern void scif_bod50_clear_irq(void);
00575
00576
00583 extern unsigned long scif_bod50_get_irq_status(void);
00584
00585
00592 extern unsigned long scif_bod50_get_irq_enable_bit(void);
00593
00594
00598 extern unsigned long scif_bod50_get_level(void);
00599
00601
00602
00605
00606
00607
00609
00612
00613
00616 extern void scif_start_rc8M(void);
00617
00620 extern void scif_stop_rc8M(void);
00621
00622
00625
00626
00629 extern void scif_start_rc120M(void);
00630
00633 extern void scif_stop_rc120M(void);
00634
00636
00637
00640
00641
00651 extern long int scif_start_gclk(unsigned int gclk, const scif_gclk_opt_t *opt);
00652
00664 extern long int scif_stop_gclk(unsigned int gclk);
00665
00680 extern long int scif_gc_setup(unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor);
00681
00690 extern long int scif_gc_enable(unsigned int gclk);
00691
00693
00694
00697
00698
00704 extern unsigned long scif_read_gplp(unsigned long gplp);
00705
00706
00712 extern void scif_write_gplp(int gplp, unsigned long value);
00713
00715
00716
00719
00720
00721
00728 #if defined (__GNUC__)
00729 __attribute__((__always_inline__))
00730 #endif
00731 extern __inline__ void scif_temperature_sensor_enable()
00732 {
00733
00734 SCIF_UNLOCK(AVR32_SCIF_TSENS);
00735 AVR32_SCIF.tsens = AVR32_SCIF_TSENS_EN_MASK;
00736 }
00737
00744 #if defined (__GNUC__)
00745 __attribute__((__always_inline__))
00746 #endif
00747 extern __inline__ void scif_temperature_sensor_disable()
00748 {
00749
00750 SCIF_UNLOCK(AVR32_SCIF_TSENS);
00751 AVR32_SCIF.tsens = ~AVR32_SCIF_TSENS_EN_MASK;
00752 }
00753
00755
00756
00757 #ifdef __cplusplus
00758 }
00759 #endif
00760
00761 #endif // _SCIF_UC3C_H_