sdramc.h File Reference


Detailed Description

SDRAMC on EBI driver for AVR32 UC3.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file sdramc.h.

#include <avr32/io.h>
#include "board.h"
#include "MT48LC16M16A2TG7E/mt48lc16m16a2tg7e.h"

Go to the source code of this file.

Defines

#define SDRAM   ((void *)AVR32_EBI_CS1_ADDRESS)
 Pointer to SDRAM.
#define SDRAM_SIZE
 SDRAM size.

Functions

void sdramc_init (unsigned long hsb_hz)
 Initializes the AVR32 SDRAM Controller and the connected SDRAM(s).


Define Documentation

#define SDRAM   ((void *)AVR32_EBI_CS1_ADDRESS)

Pointer to SDRAM.

Definition at line 62 of file sdramc.h.

Referenced by main(), and sdramc_init().

#define SDRAM_SIZE

Value:

(1 << (SDRAM_BANK_BITS + \
                               SDRAM_ROW_BITS  + \
                               SDRAM_COL_BITS  + \
                               (SDRAM_DBW >> 4)))
SDRAM size.

Definition at line 66 of file sdramc.h.

Referenced by main().


Function Documentation

void sdramc_init ( unsigned long  hsb_hz  ) 

Initializes the AVR32 SDRAM Controller and the connected SDRAM(s).

Parameters:
hsb_hz HSB frequency in Hz (the HSB frequency is applied to the SDRAMC and to the SDRAM).
Note:
HMATRIX and SDRAMC registers are always read with a dummy load operation after having been written to, in order to force write-back before executing the following accesses, which depend on the values set in these registers.

Each access to the SDRAM address space validates the mode of the SDRAMC and generates an operation corresponding to this mode.

Definition at line 242 of file sdramc.c.

References SDRAM, SDRAM_BANK_BITS, SDRAM_CAS, SDRAM_COL_BITS, SDRAM_INIT_AUTO_REFRESH_COUNT, SDRAM_ROW_BITS, SDRAM_STABLE_CLOCK_INIT_DELAY, SDRAM_TMRD, SDRAM_TR, SDRAM_TRAS, SDRAM_TRC, SDRAM_TRCD, SDRAM_TRFC, SDRAM_TRP, SDRAM_TWR, SDRAM_TXSR, sdramc_enable_muxed_pins(), sdramc_ns_delay, and sdramc_us_delay.

Referenced by main().

00243 {
00244   unsigned long hsb_mhz_dn = hsb_hz / 1000000;
00245   unsigned long hsb_mhz_up = (hsb_hz + 999999) / 1000000;
00246   volatile ATPASTE2(U, SDRAM_DBW) *sdram = SDRAM;
00247   unsigned int i;
00248 
00249   // Put the multiplexed MCU pins used for the SDRAM under control of the SDRAMC.
00250   sdramc_enable_muxed_pins();
00251 
00252   // Enable SDRAM mode for CS1.
00253   AVR32_HMATRIX.sfr[AVR32_EBI_HMATRIX_NR] |= 1 << AVR32_EBI_SDRAM_CS;
00254   AVR32_HMATRIX.sfr[AVR32_EBI_HMATRIX_NR];
00255 
00256   // Configure the SDRAM Controller with SDRAM setup and timing information.
00257   // All timings below are rounded up because they are minimal values.
00258   AVR32_SDRAMC.cr =
00259       ((( SDRAM_COL_BITS                 -    8) << AVR32_SDRAMC_CR_NC_OFFSET  ) & AVR32_SDRAMC_CR_NC_MASK  ) |
00260       ((( SDRAM_ROW_BITS                 -   11) << AVR32_SDRAMC_CR_NR_OFFSET  ) & AVR32_SDRAMC_CR_NR_MASK  ) |
00261       ((( SDRAM_BANK_BITS                -    1) << AVR32_SDRAMC_CR_NB_OFFSET  ) & AVR32_SDRAMC_CR_NB_MASK  ) |
00262       ((  SDRAM_CAS                              << AVR32_SDRAMC_CR_CAS_OFFSET ) & AVR32_SDRAMC_CR_CAS_MASK ) |
00263       ((( SDRAM_DBW                      >>   4) << AVR32_SDRAMC_CR_DBW_OFFSET ) & AVR32_SDRAMC_CR_DBW_MASK ) |
00264       ((((SDRAM_TWR  * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TWR_OFFSET ) & AVR32_SDRAMC_CR_TWR_MASK ) |
00265       ((((SDRAM_TRC  * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRC_OFFSET ) & AVR32_SDRAMC_CR_TRC_MASK ) |
00266       ((((SDRAM_TRP  * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRP_OFFSET ) & AVR32_SDRAMC_CR_TRP_MASK ) |
00267       ((((SDRAM_TRCD * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRCD_OFFSET) & AVR32_SDRAMC_CR_TRCD_MASK) |
00268       ((((SDRAM_TRAS * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TRAS_OFFSET) & AVR32_SDRAMC_CR_TRAS_MASK) |
00269       ((((SDRAM_TXSR * hsb_mhz_up + 999) / 1000) << AVR32_SDRAMC_CR_TXSR_OFFSET) & AVR32_SDRAMC_CR_TXSR_MASK);
00270   AVR32_SDRAMC.cr;
00271 
00272   // Issue a NOP command to the SDRAM in order to start the generation of SDRAMC signals.
00273   AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_NOP;
00274   AVR32_SDRAMC.mr;
00275   sdram[0];
00276 
00277   // Wait during the SDRAM stable-clock initialization delay.
00278   sdramc_us_delay(SDRAM_STABLE_CLOCK_INIT_DELAY, hsb_mhz_up);
00279 
00280   // Issue a PRECHARGE ALL command to the SDRAM.
00281   AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_BANKS_PRECHARGE;
00282   AVR32_SDRAMC.mr;
00283   sdram[0];
00284   sdramc_ns_delay(SDRAM_TRP, hsb_mhz_up);
00285 
00286   // Issue initialization AUTO REFRESH commands to the SDRAM.
00287   AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_AUTO_REFRESH;
00288   AVR32_SDRAMC.mr;
00289   for (i = 0; i < SDRAM_INIT_AUTO_REFRESH_COUNT; i++)
00290   {
00291     sdram[0];
00292     sdramc_ns_delay(SDRAM_TRFC, hsb_mhz_up);
00293   }
00294 
00295   // Issue a LOAD MODE REGISTER command to the SDRAM.
00296   // This configures the SDRAM with the following parameters in the mode register:
00297   //  - bits 0 to 2: burst length: 1 (000b);
00298   //  - bit 3: burst type: sequential (0b);
00299   //  - bits 4 to 6: CAS latency: AVR32_SDRAMC.CR.cas;
00300   //  - bits 7 to 8: operating mode: standard operation (00b);
00301   //  - bit 9: write burst mode: programmed burst length (0b);
00302   //  - all other bits: reserved: 0b.
00303   AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_LOAD_MODE;
00304   AVR32_SDRAMC.mr;
00305   sdram[0];
00306   sdramc_ns_delay(SDRAM_TMRD, hsb_mhz_up);
00307 
00308   // Switch the SDRAM Controller to normal mode.
00309   AVR32_SDRAMC.mr = AVR32_SDRAMC_MR_MODE_NORMAL;
00310   AVR32_SDRAMC.mr;
00311   sdram[0];
00312 
00313   // Write the refresh period into the SDRAMC Refresh Timer Register.
00314   // tR is rounded down because it is a maximal value.
00315   AVR32_SDRAMC.tr = (SDRAM_TR * hsb_mhz_dn) / 1000;
00316   AVR32_SDRAMC.tr;
00317 }


Generated on Fri Feb 19 02:23:52 2010 for AVR32 - MT48LC16M16A2TG-7E SDRAM Driver by  doxygen 1.5.5