This file contains definitions and services for the AVR32 WatchDog Timer.
Definition in file wdt4.c.
#include <avr32/io.h>
#include "compiler.h"
#include "board.h"
#include "wdt4.h"
Go to the source code of this file.
Defines | |
#define | MAX_US_TIMEBAN_PERIOD_OSC32K (((1ULL << (1 << AVR32_WDT_CTRL_TBAN_SIZE)) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) |
#define | MAX_US_TIMEBAN_PERIOD_RCSYS (((1ULL << (1 << AVR32_WDT_CTRL_TBAN_SIZE)) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) |
#define | MAX_US_TIMEOUT_PERIOD_OSC32K (((1ULL << (1 << AVR32_WDT_CTRL_PSEL_SIZE)) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) |
#define | MAX_US_TIMEOUT_PERIOD_RCSYS (((1ULL << (1 << AVR32_WDT_CTRL_PSEL_SIZE)) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) |
#define | MIN_US_TIMEBAN_PERIOD_OSC32K (((1ULL << 1 ) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) |
#define | MIN_US_TIMEBAN_PERIOD_RCSYS (((1ULL << 1 ) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) |
#define | MIN_US_TIMEOUT_PERIOD_OSC32K (((1ULL << 1 ) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) |
#define | MIN_US_TIMEOUT_PERIOD_RCSYS (((1ULL << 1 ) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) |
Functions | |
void | wdt_clear (void) |
Clears the WatchDog Timer. | |
void | wdt_disable (void) |
Disables the WatchDog Timer. | |
unsigned long long | wdt_enable (wdt_opt_t *opt) |
Enables the WatchDog Timer with the us_timeout_period time-out period saturated to the supported range and rounded up to the nearest supported greater time-out period. | |
long long | wdt_get_us_timeban_period (wdt_opt_t *opt) |
Gets the timeban period of the WatchDog Timer in microseconds. | |
long long | wdt_get_us_timeout_period (wdt_opt_t *opt) |
Gets the time-out period of the WatchDog Timer in microseconds. | |
void | wdt_reenable (void) |
Re-enables the WatchDog Timer with the last time-out period configured. | |
void | wdt_reset_mcu (void) |
Resets the MCU with the WatchDog Timer as fast as possible. | |
static void | wdt_set_ctrl (unsigned long ctrl) |
Sets the WatchDog Timer Control register to the ctrl value thanks to the WatchDog Timer key. |
#define MAX_US_TIMEBAN_PERIOD_OSC32K (((1ULL << (1 << AVR32_WDT_CTRL_TBAN_SIZE)) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) |
Referenced by wdt_enable().
#define MAX_US_TIMEBAN_PERIOD_RCSYS (((1ULL << (1 << AVR32_WDT_CTRL_TBAN_SIZE)) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) |
Referenced by wdt_enable().
#define MAX_US_TIMEOUT_PERIOD_OSC32K (((1ULL << (1 << AVR32_WDT_CTRL_PSEL_SIZE)) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) |
Referenced by wdt_enable().
#define MAX_US_TIMEOUT_PERIOD_RCSYS (((1ULL << (1 << AVR32_WDT_CTRL_PSEL_SIZE)) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) |
Referenced by wdt_enable().
#define MIN_US_TIMEBAN_PERIOD_OSC32K (((1ULL << 1 ) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) |
Referenced by wdt_enable().
#define MIN_US_TIMEBAN_PERIOD_RCSYS (((1ULL << 1 ) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) |
Referenced by wdt_enable().
#define MIN_US_TIMEOUT_PERIOD_OSC32K (((1ULL << 1 ) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) |
Referenced by wdt_enable().
#define MIN_US_TIMEOUT_PERIOD_RCSYS (((1ULL << 1 ) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) |
Referenced by wdt_enable().
void wdt_clear | ( | void | ) |
void wdt_disable | ( | void | ) |
Disables the WatchDog Timer.
Definition at line 108 of file wdt4.c.
References wdt_set_ctrl().
00109 { 00110 wdt_set_ctrl(AVR32_WDT.ctrl & ~AVR32_WDT_CTRL_EN_MASK); 00111 }
unsigned long long wdt_enable | ( | wdt_opt_t * | opt | ) |
Enables the WatchDog Timer with the us_timeout_period time-out period saturated to the supported range and rounded up to the nearest supported greater time-out period.
opt | Structure for settings of WDT. |
Definition at line 113 of file wdt4.c.
References wdt_opt_t::cssel, wdt_opt_t::dar, wdt_opt_t::fcd, MAX_US_TIMEBAN_PERIOD_OSC32K, MAX_US_TIMEBAN_PERIOD_RCSYS, MAX_US_TIMEOUT_PERIOD_OSC32K, MAX_US_TIMEOUT_PERIOD_RCSYS, MIN_US_TIMEBAN_PERIOD_OSC32K, MIN_US_TIMEBAN_PERIOD_RCSYS, MIN_US_TIMEOUT_PERIOD_OSC32K, MIN_US_TIMEOUT_PERIOD_RCSYS, wdt_opt_t::mode, wdt_opt_t::sfv, wdt_opt_t::us_timeban_period, wdt_opt_t::us_timeout_period, WDT_CLOCK_SOURCE_SELECT_RCSYS, wdt_get_us_timeout_period(), and wdt_set_ctrl().
Referenced by wdt_reset_mcu(), and wdt_scheduler().
00114 { 00115 00116 #define MIN_US_TIMEOUT_PERIOD_RCSYS (((1ULL << 1 ) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) 00117 #define MAX_US_TIMEOUT_PERIOD_RCSYS (((1ULL << (1 << AVR32_WDT_CTRL_PSEL_SIZE)) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) 00118 #define MIN_US_TIMEOUT_PERIOD_OSC32K (((1ULL << 1 ) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) 00119 #define MAX_US_TIMEOUT_PERIOD_OSC32K (((1ULL << (1 << AVR32_WDT_CTRL_PSEL_SIZE)) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) 00120 00121 #define MIN_US_TIMEBAN_PERIOD_RCSYS (((1ULL << 1 ) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) 00122 #define MAX_US_TIMEBAN_PERIOD_RCSYS (((1ULL << (1 << AVR32_WDT_CTRL_TBAN_SIZE)) * 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY) 00123 #define MIN_US_TIMEBAN_PERIOD_OSC32K (((1ULL << 1 ) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) 00124 #define MAX_US_TIMEBAN_PERIOD_OSC32K (((1ULL << (1 << AVR32_WDT_CTRL_TBAN_SIZE)) * 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY) 00125 00126 00127 // RCOSC 00128 if (opt->cssel == WDT_CLOCK_SOURCE_SELECT_RCSYS) 00129 { 00130 // Set the CTRL.EN bit 00131 // Translate the us timeout to fit in CTRL.PSEL using the formula Twdt = 2pow(PSEL+1) / fRCosc 00132 // Translate the us timeban to fit in CTRL.PSEL using the formula Twdt = 2pow(PSEL+1) / fRCosc 00133 wdt_set_ctrl(AVR32_WDT_CTRL_EN_MASK | AVR32_WDT_CTRL_CEN_MASK | 00134 (opt->dar << AVR32_WDT_CTRL_DAR_OFFSET) | 00135 (opt->mode << AVR32_WDT_CTRL_MODE_OFFSET) | 00136 (opt->sfv << AVR32_WDT_CTRL_SFV_OFFSET) | 00137 (opt->fcd << AVR32_WDT_CTRL_FCD_OFFSET) | 00138 (opt->cssel << AVR32_WDT_CTRL_CSSEL_OFFSET) | 00139 ((32 - clz(((((Min(Max(opt->us_timeout_period, MIN_US_TIMEOUT_PERIOD_RCSYS), MAX_US_TIMEOUT_PERIOD_RCSYS) * 00140 AVR32_SCIF_RCOSC_FREQUENCY + 500000) / 1000000) << 1) - 1) >> 1) - 1) << 00141 AVR32_WDT_CTRL_PSEL_OFFSET) | 00142 ((32 - clz(((((Min(Max(opt->us_timeban_period, MIN_US_TIMEBAN_PERIOD_RCSYS), MAX_US_TIMEBAN_PERIOD_RCSYS) * 00143 AVR32_SCIF_RCOSC_FREQUENCY + 500000) / 1000000) << 1) - 1) >> 1) - 1) << 00144 AVR32_WDT_CTRL_TBAN_OFFSET)); 00145 } 00146 else 00147 { 00148 // Set the CTRL.EN bit 00149 // Translate the us timeout to fit in CTRL.PSEL using the formula Twdt = 2pow(PSEL+1) / fROSC32K 00150 // Translate the us timeban to fit in CTRL.PSEL using the formula Twdt = 2pow(PSEL+1) / fROSC32K 00151 wdt_set_ctrl(AVR32_WDT_CTRL_EN_MASK | AVR32_WDT_CTRL_CEN_MASK | 00152 (opt->dar << AVR32_WDT_CTRL_DAR_OFFSET) | 00153 (opt->mode << AVR32_WDT_CTRL_MODE_OFFSET) | 00154 (opt->sfv << AVR32_WDT_CTRL_SFV_OFFSET) | 00155 (opt->fcd << AVR32_WDT_CTRL_FCD_OFFSET) | 00156 (opt->cssel << AVR32_WDT_CTRL_CSSEL_OFFSET) | 00157 ((32 - clz(((((Min(Max(opt->us_timeout_period, MIN_US_TIMEOUT_PERIOD_OSC32K), MAX_US_TIMEOUT_PERIOD_OSC32K) * 00158 AVR32_SCIF_OSC32_FREQUENCY + 500000) / 1000000) << 1) - 1) >> 1) - 1) << 00159 AVR32_WDT_CTRL_PSEL_OFFSET) | 00160 ((32 - clz(((((Min(Max(opt->us_timeout_period, MIN_US_TIMEBAN_PERIOD_OSC32K), MAX_US_TIMEBAN_PERIOD_OSC32K) * 00161 AVR32_SCIF_OSC32_FREQUENCY + 500000) / 1000000) << 1) - 1) >> 1) - 1) << 00162 AVR32_WDT_CTRL_TBAN_OFFSET)); 00163 } 00164 // Return the actual wdt period in us. 00165 return wdt_get_us_timeout_period(opt); 00166 }
long long wdt_get_us_timeban_period | ( | wdt_opt_t * | opt | ) |
Gets the timeban period of the WatchDog Timer in microseconds.
opt | Structure for settings of WDT. |
<0 | The WatchDog Timer is disabled. | |
>=0 | Active timeban period of the WatchDog Timer in microseconds. |
Definition at line 87 of file wdt4.c.
References wdt_opt_t::cssel, and WDT_CLOCK_SOURCE_SELECT_RCSYS.
00088 { 00089 // RCOSC 00090 if (opt->cssel == WDT_CLOCK_SOURCE_SELECT_RCSYS) 00091 { 00092 // Read CTRL.PSEL and translate it into us. 00093 return (AVR32_WDT.ctrl & AVR32_WDT_CTRL_EN_MASK) ? 00094 ((1ULL << (((AVR32_WDT.ctrl & AVR32_WDT_CTRL_TBAN_MASK) >> AVR32_WDT_CTRL_TBAN_OFFSET) + 1)) * 00095 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY : 00096 -1ULL; 00097 } 00098 else 00099 { 00100 // Read CTRL.PSEL and translate it into us. 00101 return (AVR32_WDT.ctrl & AVR32_WDT_CTRL_EN_MASK) ? 00102 ((1ULL << (((AVR32_WDT.ctrl & AVR32_WDT_CTRL_TBAN_MASK) >> AVR32_WDT_CTRL_TBAN_OFFSET) + 1)) * 00103 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY : 00104 -1ULL; 00105 } 00106 }
long long wdt_get_us_timeout_period | ( | wdt_opt_t * | opt | ) |
Gets the time-out period of the WatchDog Timer in microseconds.
opt | Structure for settings of WDT. |
<0 | The WatchDog Timer is disabled. | |
>=0 | Active time-out period of the WatchDog Timer in microseconds. |
Definition at line 66 of file wdt4.c.
References wdt_opt_t::cssel, and WDT_CLOCK_SOURCE_SELECT_RCSYS.
Referenced by wdt_enable().
00067 { 00068 // RCOSC 00069 if (opt->cssel == WDT_CLOCK_SOURCE_SELECT_RCSYS) 00070 { 00071 // Read CTRL.PSEL and translate it into us. 00072 return (AVR32_WDT.ctrl & AVR32_WDT_CTRL_EN_MASK) ? 00073 ((1ULL << (((AVR32_WDT.ctrl & AVR32_WDT_CTRL_PSEL_MASK) >> AVR32_WDT_CTRL_PSEL_OFFSET) + 1)) * 00074 1000000 + AVR32_SCIF_RCOSC_FREQUENCY / 2) / AVR32_SCIF_RCOSC_FREQUENCY : 00075 -1ULL; 00076 } 00077 else 00078 { 00079 // Read CTRL.PSEL and translate it into us. 00080 return (AVR32_WDT.ctrl & AVR32_WDT_CTRL_EN_MASK) ? 00081 ((1ULL << (((AVR32_WDT.ctrl & AVR32_WDT_CTRL_PSEL_MASK) >> AVR32_WDT_CTRL_PSEL_OFFSET) + 1)) * 00082 1000000 + AVR32_SCIF_OSC32_FREQUENCY / 2) / AVR32_SCIF_OSC32_FREQUENCY : 00083 -1ULL; 00084 } 00085 }
void wdt_reenable | ( | void | ) |
Re-enables the WatchDog Timer with the last time-out period configured.
Definition at line 168 of file wdt4.c.
References wdt_set_ctrl().
Referenced by wdt_scheduler().
00169 { 00170 wdt_set_ctrl(AVR32_WDT.ctrl | AVR32_WDT_CTRL_EN_MASK | AVR32_WDT_CTRL_CEN_MASK ); 00171 }
void wdt_reset_mcu | ( | void | ) |
Resets the MCU with the WatchDog Timer as fast as possible.
Definition at line 178 of file wdt4.c.
References wdt_enable().
00179 { 00180 Disable_global_interrupt(); 00181 // Enable the WDT with a 0s period (fastest way to get a Watchdog reset). 00182 wdt_enable(0); 00183 while (1); 00184 }
static void wdt_set_ctrl | ( | unsigned long | ctrl | ) | [static] |
Sets the WatchDog Timer Control register to the ctrl value thanks to the WatchDog Timer key.
ctrl | Value to set the WatchDog Timer Control register to. |
Definition at line 60 of file wdt4.c.
Referenced by wdt_disable(), wdt_enable(), and wdt_reenable().
00061 { 00062 AVR32_WDT.ctrl = ctrl | (AVR32_WDT_KEY_VALUE << AVR32_WDT_CTRL_KEY_OFFSET); 00063 AVR32_WDT.ctrl = ctrl | ((unsigned long) (~AVR32_WDT_KEY_VALUE << AVR32_WDT_CTRL_KEY_OFFSET) & AVR32_WDT_CTRL_KEY_MASK); 00064 }