This file contains the USBB low-level driver definitions.
Definition in file usb_drv.h.
#include "compiler.h"
#include "preprocessor.h"
#include "usbb.h"
#include "conf_usb.h"
Go to the source code of this file.
Defines | |
#define | AWAITVRISE_TIMER AVR32_USBB_USBCON_TIMPAGE_A_WAIT_VRISE |
#define | AWAITVRISE_TMOUT_100_MS AVR32_USBB_USBCON_TIMVALUE_A_WAIT_VRISE_100_MS |
#define | AWAITVRISE_TMOUT_20_MS AVR32_USBB_USBCON_TIMVALUE_A_WAIT_VRISE_20_MS |
#define | AWAITVRISE_TMOUT_50_MS AVR32_USBB_USBCON_TIMVALUE_A_WAIT_VRISE_50_MS |
#define | AWAITVRISE_TMOUT_70_MS AVR32_USBB_USBCON_TIMVALUE_A_WAIT_VRISE_70_MS |
#define | BANK_PID_DATA0 0 |
#define | BANK_PID_DATA1 1 |
#define | DIRECTION_IN AVR32_USBB_UECFGX_EPDIR_IN |
#define | DIRECTION_OUT AVR32_USBB_UECFGX_EPDIR_OUT |
#define | DMA_BUFFER_SIZE_16_BITS AVR32_USBB_UFEATURES_DMA_BUFFER_SIZE_16_BITS |
#define | DMA_BUFFER_SIZE_24_BITS AVR32_USBB_UFEATURES_DMA_BUFFER_SIZE_24_BITS |
#define | DOUBLE_BANK AVR32_USBB_UECFGX_EPBK_DOUBLE |
#define | EP_0 0 |
#define | EP_1 1 |
#define | EP_2 2 |
#define | EP_3 3 |
#define | EP_4 4 |
#define | EP_5 5 |
#define | EP_6 6 |
#define | EP_CONTROL 0 |
#define | Host_ack_all_errors(p) |
acks all pipe error | |
#define | Host_ack_bad_data_toggle(p) (Clr_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_DATATGL_MASK)) |
acks bad data toggle | |
#define | Host_ack_control_in_received() (AVR32_USBB_upstaxclr(P_CONTROL) = AVR32_USBB_UPSTAXCLR_RXINIC_MASK) |
acks control IN | |
#define | Host_ack_control_in_received_free() (Host_ack_control_in_received(), Host_free_control_in()) |
acks control IN and frees current bank | |
#define | Host_ack_control_out_ready() (AVR32_USBB_upstaxclr(P_CONTROL) = AVR32_USBB_UPSTAXCLR_TXOUTIC_MASK) |
acks control OUT | |
#define | Host_ack_control_out_ready_send() (Host_ack_control_out_ready(), Host_send_control_out()) |
acks control OUT and sends current bank | |
#define | Host_ack_crc16_error(p) (Clr_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_CRC16_MASK)) |
acks CRC16 error | |
#define | Host_ack_crc_error(p) (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_RXSTALLDIC_MASK) |
acks CRC ERROR ISO IN detected | |
#define | Host_ack_data_pid_error(p) (Clr_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_DATAPID_MASK)) |
acks data PID error | |
#define | Host_ack_device_connection() (AVR32_USBB_uhintclr = AVR32_USBB_UHINTCLR_DCONNIC_MASK) |
acks device connection | |
#define | Host_ack_device_disconnection() (AVR32_USBB_uhintclr = AVR32_USBB_UHINTCLR_DDISCIC_MASK) |
acks device disconnection | |
#define | Host_ack_down_stream_resume() (AVR32_USBB_uhintclr = AVR32_USBB_UHINTCLR_RSMEDIC_MASK) |
acks host down stream resume sent | |
#define | Host_ack_fifocon(p) (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_FIFOCONC_MASK) |
clears FIFOCON bit | |
#define | Host_ack_hwup() (AVR32_USBB_uhintclr = AVR32_USBB_UHINTCLR_HWUPIC_MASK) |
acks host wake-up detection | |
#define | Host_ack_in_received(p) (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_RXINIC_MASK) |
acks IN reception | |
#define | Host_ack_in_received_free(p) (Host_ack_in_received(p), Host_free_in(p)) |
acks IN reception and frees current bank | |
#define | Host_ack_nak_received(p) (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_NAKEDIC_MASK) |
acks NAK received | |
#define | Host_ack_out_ready(p) (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_TXOUTIC_MASK) |
acks OUT sent | |
#define | Host_ack_out_ready_send(p) (Host_ack_out_ready(p), Host_send_out(p)) |
acks OUT sent and sends current bank | |
#define | Host_ack_overflow_interrupt(p) (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_OVERFIC_MASK) |
acks pipe overflow interrupt | |
#define | Host_ack_pid_error(p) (Clr_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_PID_MASK)) |
acks PID error | |
#define | Host_ack_pipe_error(p) (AVR32_USBB_upstaxset(p) = (Is_host_pipe_error(p)) ? AVR32_USBB_UPSTAXSET_PERRIS_MASK : 0) |
acks pipe error | |
#define | Host_ack_remote_wakeup() (AVR32_USBB_uhintclr = AVR32_USBB_UHINTCLR_RXRSMIC_MASK) |
acks host remote wake-up detection | |
#define | Host_ack_reset_sent() (AVR32_USBB_uhintclr = AVR32_USBB_UHINTCLR_RSTIC_MASK) |
acks host USB reset sent | |
#define | Host_ack_setup_ready() (AVR32_USBB_upstaxclr(P_CONTROL) = AVR32_USBB_UPSTAXCLR_TXSTPIC_MASK) |
acks setup | |
#define | Host_ack_setup_ready_send() (Host_ack_setup_ready(), Host_send_setup()) |
acks setup and sends current bank | |
#define | Host_ack_short_packet(p) (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_SHORTPACKETIC_MASK) |
acks SHORT PACKET received | |
#define | Host_ack_sof() (AVR32_USBB_uhintclr = AVR32_USBB_UHINTCLR_HSOFIC_MASK) |
acks SOF detection | |
#define | Host_ack_stall(p) (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_RXSTALLDIC_MASK) |
acks STALL reception | |
#define | Host_ack_timeout_error(p) (Clr_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_TIMEOUT_MASK)) |
acks time-out error | |
#define | Host_ack_underflow_interrupt(p) (AVR32_USBB_upstaxclr(p) = AVR32_USBB_UPSTAXCLR_TXSTPIC_MASK) |
acks pipe underflow interrupt | |
#define | Host_allocate_memory(p) (Set_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_ALLOC_MASK)) |
allocates the configuration x in DPRAM memory | |
#define | Host_byte_count(p) (Rd_bitfield(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_PBYCT_MASK)) |
returns the byte count | |
#define | Host_clear_error_counter(p) (Clr_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_COUNTER_MASK)) |
clears the error counter | |
#define | Host_configure_address(p, addr) (Wr_bitfield(AVR32_USBB_uhaddrx(1 + ((p) >> 2)), AVR32_USBB_UHADDR1_UHADDR_P0_MASK << (((p) & 0x03) << 3), addr)) |
configures the USB device address associated with the selected pipe | |
#define | Host_configure_pipe(p, freq, ep_num, type, token, size, bank) |
configures selected pipe in one step | |
#define | Host_configure_pipe_bank(p, bank) (Wr_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PBK_MASK, bank)) |
configures the selected pipe number of banks | |
#define | Host_configure_pipe_endpoint_number(p, ep_num) (Wr_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PEPNUM_MASK, ep_num)) |
configures the selected pipe endpoint number | |
#define | Host_configure_pipe_int_req_freq(p, freq) (Wr_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_INTFRQ_MASK, freq)) |
configures the interrupt pipe request frequency (period in ms) for the selected pipe | |
#define | Host_configure_pipe_size(p, size) (Wr_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PSIZE_MASK, Host_format_pipe_size(size))) |
configures the selected pipe size | |
#define | Host_configure_pipe_token(p, token) (Wr_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PTOKEN_MASK, token)) |
configures the selected pipe token | |
#define | Host_configure_pipe_type(p, type) (Wr_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PTYPE_MASK, type)) |
configures the selected pipe type | |
#define | Host_current_bank(p) (Rd_bitfield(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_CURRBK_MASK)) |
returns the number of the current bank | |
#define | Host_data_toggle(p) (Rd_bitfield(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_DTSEQ_MASK)) |
returns data toggle | |
#define | Host_disable_bank_interrupt(p) (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_NBUSYBKEC_MASK) |
disables all banks full (IN) or free (OUT) interrupt | |
#define | Host_disable_continuous_in_mode(p) (Clr_bits(AVR32_USBB_upinrqx(p), AVR32_USBB_UPINRQX_INMODE_MASK)) |
disables continuous IN mode | |
#define | Host_disable_control_in_received_interrupt() (AVR32_USBB_upconxclr(P_CONTROL) = AVR32_USBB_UPCONXCLR_RXINEC_MASK) |
disables IN control pipe reception interrupt | |
#define | Host_disable_control_out_ready_interrupt() (AVR32_USBB_upconxclr(P_CONTROL) = AVR32_USBB_UPCONXCLR_TXOUTEC_MASK) |
disables OUT control pipe ready interrupt | |
#define | Host_disable_crc_error_interrupt(p) (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_RXSTALLDEC_MASK) |
disables CRC ERROR ISO IN detected interrupt | |
#define | Host_disable_device_connection_interrupt() (AVR32_USBB_uhinteclr = AVR32_USBB_UHINTECLR_DCONNIEC_MASK) |
disables USB device connection interrupt | |
#define | Host_disable_device_disconnection_interrupt() (AVR32_USBB_uhinteclr = AVR32_USBB_UHINTECLR_DDISCIEC_MASK) |
disables USB device connection interrupt | |
#define | Host_disable_down_stream_resume_interrupt() (AVR32_USBB_uhinteclr = AVR32_USBB_UHINTECLR_RSMEDIEC_MASK) |
disables host down stream rsm sent interrupt detection | |
#define | Host_disable_hwup_interrupt() (AVR32_USBB_uhinteclr = AVR32_USBB_UHINTECLR_HWUPIEC_MASK) |
disables host wake-up interrupt detection | |
#define | Host_disable_in_received_interrupt(p) (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_RXINEC_MASK) |
disables IN pipe reception interrupt | |
#define | Host_disable_nak_received_interrupt(p) (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_NAKEDEC_MASK) |
disables NAK received interrupt | |
#define | Host_disable_out_ready_interrupt(p) (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_TXOUTEC_MASK) |
disables OUT pipe ready interrupt | |
#define | Host_disable_overflow_interrupt(p) (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_OVERFIEC_MASK) |
disables overflow interrupt | |
#define | Host_disable_pipe(p) (Clr_bits(AVR32_USBB_uprst, AVR32_USBB_UPRST_PEN0_MASK << (p))) |
disables the selected pipe | |
#define | Host_disable_pipe_bank_autoswitch(p) (Clr_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_AUTOSW_MASK)) |
disables the bank autoswitch for the selected pipe | |
#define | Host_disable_pipe_dma_interrupt(pdma) (AVR32_USBB_uhinteclr = AVR32_USBB_UHINTECLR_DMA1INTEC_MASK << ((pdma) - 1)) |
disables the selected pipe DMA channel interrupt | |
#define | Host_disable_pipe_error_interrupt(p) (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_PERREC_MASK) |
disables pipe error interrupt | |
#define | Host_disable_pipe_int_dis_hdma_req(p) (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_PDISHDMAC_MASK) |
disables the disabling of HDMA requests by pipe interrupts | |
#define | Host_disable_pipe_interrupt(p) (AVR32_USBB_uhinteclr = AVR32_USBB_UHINTECLR_P0INTEC_MASK << (p)) |
disables the selected pipe interrupt | |
#define | Host_disable_remote_wakeup_interrupt() (AVR32_USBB_uhinteclr = AVR32_USBB_UHINTECLR_RXRSMIEC_MASK) |
disables host remote wake-up interrupt detection | |
#define | Host_disable_reset_sent_interrupt() (AVR32_USBB_uhinteclr = AVR32_USBB_UHINTECLR_RSTIEC_MASK) |
disables host USB reset sent interrupt | |
#define | Host_disable_setup_ready_interrupt() (AVR32_USBB_upconxclr(P_CONTROL) = AVR32_USBB_UPCONXCLR_TXSTPEC_MASK) |
disables SETUP pipe ready interrupt | |
#define | Host_disable_short_packet_interrupt(p) (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_SHORTPACKETIEC_MASK) |
disables SHORT PACKET received interrupt | |
#define | Host_disable_sof() (Clr_bits(AVR32_USBB_uhcon, AVR32_USBB_UHCON_SOFE_MASK)) |
disables SOF generation | |
#define | Host_disable_sof_interrupt() (AVR32_USBB_uhinteclr = AVR32_USBB_UHINTECLR_HSOFIEC_MASK) |
enables host Start-of-Frame interrupt | |
#define | Host_disable_stall_interrupt(p) (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_RXSTALLDEC_MASK) |
disables STALL received interrupt | |
#define | Host_disable_underflow_interrupt(p) (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_TXSTPEC_MASK) |
disables underflow interrupt | |
#define | Host_enable_bank_interrupt(p) (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_NBUSYBKES_MASK) |
enables all banks full (IN) or free (OUT) interrupt | |
#define | Host_enable_continuous_in_mode(p) (Set_bits(AVR32_USBB_upinrqx(p), AVR32_USBB_UPINRQX_INMODE_MASK)) |
enables continuous IN mode | |
#define | Host_enable_control_in_received_interrupt() (AVR32_USBB_upconxset(P_CONTROL) = AVR32_USBB_UPCONXSET_RXINES_MASK) |
enables IN control pipe reception interrupt | |
#define | Host_enable_control_out_ready_interrupt() (AVR32_USBB_upconxset(P_CONTROL) = AVR32_USBB_UPCONXSET_TXOUTES_MASK) |
enables OUT control pipe ready interrupt | |
#define | Host_enable_crc_error_interrupt(p) (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_RXSTALLDES_MASK) |
enables CRC ERROR ISO IN detected interrupt | |
#define | Host_enable_device_connection_interrupt() (AVR32_USBB_uhinteset = AVR32_USBB_UHINTESET_DCONNIES_MASK) |
enables host device connection interrupt | |
#define | Host_enable_device_disconnection_interrupt() (AVR32_USBB_uhinteset = AVR32_USBB_UHINTESET_DDISCIES_MASK) |
enables host device disconnection interrupt | |
#define | Host_enable_down_stream_resume_interrupt() (AVR32_USBB_uhinteset = AVR32_USBB_UHINTESET_RSMEDIES_MASK) |
enables host down stream rsm sent interrupt detection | |
#define | Host_enable_hwup_interrupt() (AVR32_USBB_uhinteset = AVR32_USBB_UHINTESET_HWUPIES_MASK) |
enables host wake-up interrupt detection | |
#define | Host_enable_in_received_interrupt(p) (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_RXINES_MASK) |
enables IN pipe reception interrupt | |
#define | Host_enable_nak_received_interrupt(p) (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_NAKEDES_MASK) |
enables NAK received interrupt | |
#define | Host_enable_out_ready_interrupt(p) (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_TXOUTES_MASK) |
enables OUT pipe ready interrupt | |
#define | Host_enable_overflow_interrupt(p) (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_OVERFIES_MASK) |
enables overflow interrupt | |
#define | Host_enable_ping(p) (Set_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PINGEN_MASK)) |
Enable PING management for the endpoint p. | |
#define | Host_enable_pipe(p) (Set_bits(AVR32_USBB_uprst, AVR32_USBB_UPRST_PEN0_MASK << (p))) |
enables the selected pipe | |
#define | Host_enable_pipe_bank_autoswitch(p) (Set_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_AUTOSW_MASK)) |
enables the bank autoswitch for the selected pipe | |
#define | Host_enable_pipe_dma_interrupt(pdma) (AVR32_USBB_uhinteset = AVR32_USBB_UHINTESET_DMA1INTES_MASK << ((pdma) - 1)) |
enables the selected pipe DMA channel interrupt | |
#define | Host_enable_pipe_error_interrupt(p) (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_PERRES_MASK) |
enables pipe error interrupt | |
#define | Host_enable_pipe_int_dis_hdma_req(p) (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_PDISHDMAS_MASK) |
enables the disabling of HDMA requests by pipe interrupts | |
#define | Host_enable_pipe_interrupt(p) (AVR32_USBB_uhinteset = AVR32_USBB_UHINTESET_P0INTES_MASK << (p)) |
enables the selected pipe interrupt | |
#define | Host_enable_remote_wakeup_interrupt() (AVR32_USBB_uhinteset = AVR32_USBB_UHINTESET_RXRSMIES_MASK) |
enables host remote wake-up interrupt detection | |
#define | Host_enable_reset_sent_interrupt() (AVR32_USBB_uhinteset = AVR32_USBB_UHINTESET_RSTIES_MASK) |
enables host USB reset sent interrupt | |
#define | Host_enable_setup_ready_interrupt() (AVR32_USBB_upconxset(P_CONTROL) = AVR32_USBB_UPCONXSET_TXSTPES_MASK) |
enables SETUP pipe ready interrupt | |
#define | Host_enable_short_packet_interrupt(p) (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_SHORTPACKETIES_MASK) |
enables SHORT PACKET received interrupt | |
#define | Host_enable_sof() (Set_bits(AVR32_USBB_uhcon, AVR32_USBB_UHCON_SOFE_MASK)) |
enables SOF generation | |
#define | Host_enable_sof_interrupt() (AVR32_USBB_uhinteset = AVR32_USBB_UHINTESET_HSOFIES_MASK) |
enables host Start-of-Frame interrupt | |
#define | Host_enable_stall_interrupt(p) (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_RXSTALLDES_MASK) |
enables STALL received interrupt | |
#define | Host_enable_underflow_interrupt(p) (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_TXSTPES_MASK) |
enables underflow interrupt | |
#define | Host_error_status(p) |
tests if error occurs on pipe | |
#define | Host_force_bank_interrupt(p) (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_NBUSYBKS_MASK) |
forces all banks full (OUT) or free (IN) interrupt | |
#define | Host_format_pipe_size(size) (32 - clz(((U32)min(max(size, 8), 1024) << 1) - 1) - 1 - 3) |
Bounds given integer size to allowed range and rounds it up to the nearest available greater size, then applies register format of USBB controller for pipe size bit-field. | |
#define | Host_frame_length() (Rd_bitfield(AVR32_USBB_uhfnum, AVR32_USBB_UHFNUM_FLENHIGH_MASK)) |
returns the current frame length | |
#define | Host_frame_number() (Rd_bitfield(AVR32_USBB_uhfnum, AVR32_USBB_UHFNUM_FNUM_MASK)) |
returns the current frame number | |
#define | Host_free_control_in() (Host_ack_fifocon(P_CONTROL)) |
frees current bank for IN control pipe | |
#define | Host_free_in(p) (Host_ack_fifocon(p)) |
frees current bank for IN pipe | |
#define | Host_freeze_pipe(p) (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_PFREEZES_MASK) |
freezes the pipe | |
#define | Host_get_configured_address(p) (Rd_bitfield(AVR32_USBB_uhaddrx(1 + ((p) >> 2)), AVR32_USBB_UHADDR1_UHADDR_P0_MASK << (((p) & 0x03) << 3))) |
gets the currently configured USB device address associated with the selected pipe | |
#define | Host_get_error_counter(p) (Rd_bitfield(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_COUNTER_MASK)) |
#define | Host_get_in_request_number(p) (Rd_bitfield(AVR32_USBB_upinrqx(p), AVR32_USBB_UPINRQX_INRQ_MASK) + 1) |
returns number of remaining IN requests | |
#define | Host_get_interrupt_pipe_number() |
returns the lowest pipe number generating a pipe interrupt or MAX_PEP_NB if none | |
#define | Host_get_pipe_bank(p) (Rd_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PBK_MASK)) |
gets the configured selected pipe number of banks | |
#define | Host_get_pipe_endpoint_number(p) (Rd_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PEPNUM_MASK)) |
gets the configured selected pipe endpoint number | |
#define | Host_get_pipe_fifo_access(p, scale) (AVR32_USBB_FIFOX_DATA(p, scale)) |
Get 64-, 32-, 16- or 8-bit access to FIFO data register of selected pipe. | |
#define | Host_get_pipe_int_req_freq(p) (Rd_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_INTFRQ_MASK)) |
gets the configured interrupt pipe request frequency (period in ms) for the selected pipe | |
#define | Host_get_pipe_size(p) (8 << Rd_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PSIZE_MASK)) |
gets the configured selected pipe size | |
#define | Host_get_pipe_token(p) (Rd_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PTOKEN_MASK)) |
gets the configured selected pipe token | |
#define | Host_get_pipe_type(p) (Rd_bitfield(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_PTYPE_MASK)) |
gets the configured selected pipe type | |
#define | Host_in_request_number(p, in_num) (Wr_bitfield(AVR32_USBB_upinrqx(p), AVR32_USBB_UPINRQX_INRQ_MASK, (in_num) - 1)) |
sets number of IN requests to perform before freeze | |
#define | Host_nb_busy_bank(p) (Rd_bitfield(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_NBUSYBK_MASK)) |
returns the number of busy banks | |
#define | Host_raise_control_in_received() (AVR32_USBB_upstaxset(P_CONTROL) = AVR32_USBB_UPSTAXSET_RXINIS_MASK) |
raises control IN | |
#define | Host_raise_control_out_ready() (AVR32_USBB_upstaxset(P_CONTROL) = AVR32_USBB_UPSTAXSET_TXOUTIS_MASK) |
raises control OUT | |
#define | Host_raise_crc_error(p) (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_RXSTALLDIS_MASK) |
raises CRC ERROR ISO IN detected | |
#define | Host_raise_device_connection() (AVR32_USBB_uhintset = AVR32_USBB_UHINTSET_DCONNIS_MASK) |
raises device connection | |
#define | Host_raise_device_disconnection() (AVR32_USBB_uhintset = AVR32_USBB_UHINTSET_DDISCIS_MASK) |
raises device disconnection | |
#define | Host_raise_down_stream_resume() (AVR32_USBB_uhintset = AVR32_USBB_UHINTSET_RSMEDIS_MASK) |
raises host down stream resume sent | |
#define | Host_raise_hwup() (AVR32_USBB_uhintset = AVR32_USBB_UHINTSET_HWUPIS_MASK) |
raises host wake-up detection | |
#define | Host_raise_in_received(p) (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_RXINIS_MASK) |
raises IN reception | |
#define | Host_raise_nak_received(p) (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_NAKEDIS_MASK) |
raises NAK received | |
#define | Host_raise_out_ready(p) (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_TXOUTIS_MASK) |
raises OUT sent | |
#define | Host_raise_overflow_interrupt(p) (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_OVERFIS_MASK) |
raises pipe overflow interrupt | |
#define | Host_raise_pipe_dma_interrupt(pdma) (AVR32_USBB_uhintset = AVR32_USBB_UHINTSET_DMA1INTS_MASK << ((pdma) - 1)) |
raises the selected pipe DMA channel interrupt | |
#define | Host_raise_pipe_error(p) (AVR32_USBB_upstaxset(p) = (Is_host_pipe_error(p)) ? 0 : AVR32_USBB_UPSTAXSET_PERRIS_MASK) |
raises pipe error | |
#define | Host_raise_remote_wakeup() (AVR32_USBB_uhintset = AVR32_USBB_UHINTSET_RXRSMIS_MASK) |
raises host remote wake-up detection | |
#define | Host_raise_reset_sent() (AVR32_USBB_uhintset = AVR32_USBB_UHINTSET_RSTIS_MASK) |
raises host USB reset sent | |
#define | Host_raise_setup_ready() (AVR32_USBB_upstaxset(P_CONTROL) = AVR32_USBB_UPSTAXSET_TXSTPIS_MASK) |
raises setup | |
#define | Host_raise_short_packet(p) (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_SHORTPACKETIS_MASK) |
raises SHORT PACKET received | |
#define | Host_raise_sof() (AVR32_USBB_uhintset = AVR32_USBB_UHINTSET_HSOFIS_MASK) |
raises SOF detection | |
#define | Host_raise_stall(p) (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_RXSTALLDIS_MASK) |
raises STALL reception | |
#define | Host_raise_underflow_interrupt(p) (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_TXSTPIS_MASK) |
raises pipe underflow interrupt | |
#define | Host_read_pipe_data(p, scale) |
Read 64-, 32-, 16- or 8-bit data from FIFO data register of selected pipe. | |
#define | Host_read_pipe_indexed_data(p, scale, index) (AVR32_USBB_FIFOX_DATA(p, scale)[(index)]) |
Read 64-, 32-, 16- or 8-bit indexed data from FIFO data register of selected pipe. | |
#define | Host_reset_data_toggle(p) (AVR32_USBB_upconxset(p) = AVR32_USBB_UPCONXSET_RSTDTS_MASK) |
resets the data toggle sequence | |
#define | Host_reset_pipe(p) |
resets the selected pipe | |
#define | Host_reset_pipe_fifo_access(p) (pep_fifo[(p)].u64ptr = Host_get_pipe_fifo_access(p, 64)) |
Reset known position inside FIFO data register of selected pipe. | |
#define | Host_send_control_out() (Host_ack_fifocon(P_CONTROL)) |
sends current bank for OUT control pipe | |
#define | Host_send_out(p) (Host_ack_fifocon(p)) |
sends current bank for OUT pipe | |
#define | Host_send_reset() (Set_bits(AVR32_USBB_uhcon, AVR32_USBB_UHCON_RESET_MASK)) |
sends a USB Reset to the device | |
#define | Host_send_resume() (Set_bits(AVR32_USBB_uhcon, AVR32_USBB_UHCON_RESUME_MASK)) |
sends a USB Resume to the device | |
#define | Host_send_setup() (Host_ack_fifocon(P_CONTROL)) |
sends current bank for SETUP pipe | |
#define | Host_set_frame_number(fnum) (Wr_bitfield(AVR32_USBB_uhfnum, AVR32_USBB_UHFNUM_FNUM_MASK, fnum)) |
sets the current frame number | |
#define | Host_stop_sending_reset() (Clr_bits(AVR32_USBB_uhcon, AVR32_USBB_UHCON_RESET_MASK)) |
stops sending a USB Reset to the device | |
#define | Host_unallocate_memory(p) (Clr_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_ALLOC_MASK)) |
un-allocates the configuration x in DPRAM memory | |
#define | Host_unforce_bank_interrupt(p) (AVR32_USBB_upstaxset(p) = AVR32_USBB_UPSTAXSET_NBUSYBKS_MASK) |
unforces all banks full (OUT) or free (IN) interrupt | |
#define | Host_unfreeze_pipe(p) (AVR32_USBB_upconxclr(p) = AVR32_USBB_UPCONXCLR_PFREEZEC_MASK) |
unfreezees the pipe | |
#define | Host_write_pipe_data(p, scale, data) |
Write 64-, 32-, 16- or 8-bit data to FIFO data register of selected pipe. | |
#define | Host_write_pipe_indexed_data(p, scale, index, data) (AVR32_USBB_FIFOX_DATA(p, scale)[(index)] = (data)) |
Write 64-, 32-, 16- or 8-bit indexed data to FIFO data register of selected pipe. | |
#define | IP_NAME_PART_1 1 |
#define | IP_NAME_PART_2 2 |
#define | Is_host_bad_data_toggle(p) (Tst_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_DATATGL_MASK)) |
#define | Is_host_bank_interrupt_enabled(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_NBUSYBKE_MASK)) |
tests if all banks full (IN) or free (OUT) interrupt is enabled | |
#define | Is_host_continuous_in_mode_enabled(p) (Tst_bits(AVR32_USBB_upinrqx(p), AVR32_USBB_UPINRQX_INMODE_MASK)) |
tests if continuous IN mode is enabled | |
#define | Is_host_control_in_filled() (Is_host_fifocon(P_CONTROL)) |
tests if IN received in current bank for control pipe | |
#define | Is_host_control_in_received() (Tst_bits(AVR32_USBB_upstax(P_CONTROL), AVR32_USBB_UPSTAX_RXINI_MASK)) |
tests if control IN has been received | |
#define | Is_host_control_in_received_interrupt_enabled() (Tst_bits(AVR32_USBB_upconx(P_CONTROL), AVR32_USBB_UPCONX_RXINE_MASK)) |
tests if IN control pipe reception interrupt is enabled | |
#define | Is_host_control_out_ready() (Tst_bits(AVR32_USBB_upstax(P_CONTROL), AVR32_USBB_UPSTAX_TXOUTI_MASK)) |
tests if control OUT has been sent | |
#define | Is_host_control_out_ready_interrupt_enabled() (Tst_bits(AVR32_USBB_upconx(P_CONTROL), AVR32_USBB_UPCONX_TXOUTE_MASK)) |
tests if OUT control pipe ready interrupt is enabled | |
#define | Is_host_control_out_sent() (Is_host_fifocon(P_CONTROL)) |
tests if current bank sent for OUT control pipe | |
#define | Is_host_crc16_error(p) (Tst_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_CRC16_MASK)) |
#define | Is_host_crc_error(p) (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_RXSTALLDI_MASK)) |
tests if CRC ERROR ISO IN detected | |
#define | Is_host_crc_error_interrupt_enabled(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_RXSTALLDE_MASK)) |
tests if CRC ERROR ISO IN detected interrupt is enabled | |
#define | Is_host_data_pid_error(p) (Tst_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_DATAPID_MASK)) |
#define | Is_host_data_toggle_reset(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_RSTDT_MASK)) |
tests if the data toggle sequence is being reset | |
#define | Is_host_device_connection() (Tst_bits(AVR32_USBB_uhint, AVR32_USBB_UHINT_DCONNI_MASK)) |
tests if a USB device has been detected | |
#define | Is_host_device_connection_interrupt_enabled() (Tst_bits(AVR32_USBB_uhinte, AVR32_USBB_UHINTE_DCONNIE_MASK)) |
#define | Is_host_device_disconnection() (Tst_bits(AVR32_USBB_uhint, AVR32_USBB_UHINT_DDISCI_MASK)) |
tests if a USB device has been removed | |
#define | Is_host_device_disconnection_interrupt_enabled() (Tst_bits(AVR32_USBB_uhinte, AVR32_USBB_UHINTE_DDISCIE_MASK)) |
#define | Is_host_down_stream_resume() (Tst_bits(AVR32_USBB_uhint, AVR32_USBB_UHINT_RSMEDI_MASK)) |
#define | Is_host_down_stream_resume_interrupt_enabled() (Tst_bits(AVR32_USBB_uhinte, AVR32_USBB_UHINTE_RSMEDIE_MASK)) |
#define | Is_host_fifocon(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_FIFOCON_MASK)) |
tests if FIFOCON bit set | |
#define | Is_host_hwup() (Tst_bits(AVR32_USBB_uhint, AVR32_USBB_UHINT_HWUPI_MASK)) |
tests if host wake-up detected | |
#define | Is_host_hwup_interrupt_enabled() (Tst_bits(AVR32_USBB_uhinte, AVR32_USBB_UHINTE_HWUPIE_MASK)) |
#define | Is_host_in_filled(p) (Is_host_fifocon(p)) |
tests if IN received in current bank | |
#define | Is_host_in_received(p) (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_RXINI_MASK)) |
tests if IN received | |
#define | Is_host_in_received_interrupt_enabled(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_RXINE_MASK)) |
tests if IN pipe reception interrupt is enabled | |
#define | Is_host_memory_allocated(p) (Tst_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_ALLOC_MASK)) |
#define | Is_host_nak_received(p) (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_NAKEDI_MASK)) |
tests if NAK handshake has been received | |
#define | Is_host_nak_received_interrupt_enabled(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_NAKEDE_MASK)) |
tests if NAK received interrupt is enabled | |
#define | Is_host_out_ready(p) (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_TXOUTI_MASK)) |
tests if OUT has been sent | |
#define | Is_host_out_ready_interrupt_enabled(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_TXOUTE_MASK)) |
tests if OUT pipe ready interrupt is enabled | |
#define | Is_host_out_sent(p) (Is_host_fifocon(p)) |
tests if current bank sent for OUT pipe | |
#define | Is_host_overflow(p) (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_OVERFI_MASK)) |
tests if an overflow occurs | |
#define | Is_host_overflow_interrupt_enabled(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_OVERFIE_MASK)) |
tests if overflow interrupt is enabled | |
#define | Is_host_pid_error(p) (Tst_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_PID_MASK)) |
#define | Is_host_pipe_bank_autoswitch_enabled(p) (Tst_bits(AVR32_USBB_upcfgx(p), AVR32_USBB_UPCFGX_AUTOSW_MASK)) |
#define | Is_host_pipe_configured(p) (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_CFGOK_MASK)) |
tests if current pipe is configured | |
#define | Is_host_pipe_dma_interrupt(pdma) (Tst_bits(AVR32_USBB_uhint, AVR32_USBB_UHINT_DMA1INT_MASK << ((pdma) - 1))) |
tests if an interrupt is triggered by the selected pipe DMA channel | |
#define | Is_host_pipe_dma_interrupt_enabled(pdma) (Tst_bits(AVR32_USBB_uhinte, AVR32_USBB_UHINTE_DMA1INTE_MASK << ((pdma) - 1))) |
tests if the selected pipe DMA channel interrupt is enabled | |
#define | Is_host_pipe_enabled(p) (Tst_bits(AVR32_USBB_uprst, AVR32_USBB_UPRST_PEN0_MASK << (p))) |
tests if the selected pipe is enabled | |
#define | Is_host_pipe_error(p) (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_PERRI_MASK)) |
tests if an error occurs on current pipe | |
#define | Is_host_pipe_error_interrupt_enabled(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_PERRE_MASK)) |
tests if pipe error interrupt is enabled | |
#define | Is_host_pipe_frozen(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_PFREEZE_MASK)) |
tests if the current pipe is frozen | |
#define | Is_host_pipe_int_dis_hdma_req_enabled(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_PDISHDMA_MASK)) |
tests if the disabling of HDMA requests by pipe interrupts si enabled | |
#define | Is_host_pipe_interrupt(p) (Tst_bits(AVR32_USBB_uhint, AVR32_USBB_UHINT_P0INT_MASK << (p))) |
tests if an interrupt is triggered by the selected pipe | |
#define | Is_host_pipe_interrupt_enabled(p) (Tst_bits(AVR32_USBB_uhinte, AVR32_USBB_UHINTE_P0INTE_MASK << (p))) |
tests if the selected pipe interrupt is enabled | |
#define | Is_host_read_enabled(p) (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_RWALL_MASK)) |
tests if pipe read allowed | |
#define | Is_host_remote_wakeup() (Tst_bits(AVR32_USBB_uhint, AVR32_USBB_UHINT_RXRSMI_MASK)) |
tests if host remote wake-up detected | |
#define | Is_host_remote_wakeup_interrupt_enabled() (Tst_bits(AVR32_USBB_uhinte, AVR32_USBB_UHINTE_RXRSMIE_MASK)) |
#define | Is_host_reset_sent() (Tst_bits(AVR32_USBB_uhint, AVR32_USBB_UHINT_RSTI_MASK)) |
tests if host USB reset sent | |
#define | Is_host_reset_sent_interrupt_enabled() (Tst_bits(AVR32_USBB_uhinte, AVR32_USBB_UHINTE_RSTIE_MASK)) |
#define | Is_host_resetting_pipe(p) (Tst_bits(AVR32_USBB_uprst, AVR32_USBB_UPRST_PRST0_MASK << (p))) |
tests if the selected pipe is being reset | |
#define | Is_host_sending_reset() (Tst_bits(AVR32_USBB_uhcon, AVR32_USBB_UHCON_RESET_MASK)) |
tests if USB Reset running | |
#define | Is_host_sending_resume() (Tst_bits(AVR32_USBB_uhcon, AVR32_USBB_UHCON_RESUME_MASK)) |
tests if USB Resume running | |
#define | Is_host_setup_ready() (Tst_bits(AVR32_USBB_upstax(P_CONTROL), AVR32_USBB_UPSTAX_TXSTPI_MASK)) |
tests if SETUP has been sent | |
#define | Is_host_setup_ready_interrupt_enabled() (Tst_bits(AVR32_USBB_upconx(P_CONTROL), AVR32_USBB_UPCONX_TXSTPE_MASK)) |
tests if SETUP pipe ready interrupt is enabled | |
#define | Is_host_setup_sent() (Is_host_fifocon(P_CONTROL)) |
tests if current bank sent for SETUP pipe | |
#define | Is_host_short_packet(p) (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_SHORTPACKETI_MASK)) |
tests if SHORT PACKET received | |
#define | Is_host_short_packet_interrupt_enabled(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_SHORTPACKETIE_MASK)) |
tests if SHORT PACKET received interrupt is enabled | |
#define | Is_host_sof() (Tst_bits(AVR32_USBB_uhint, AVR32_USBB_UHINT_HSOFI_MASK)) |
tests if SOF detected | |
#define | Is_host_sof_enabled() (Tst_bits(AVR32_USBB_uhcon, AVR32_USBB_UHCON_SOFE_MASK)) |
tests if SOF generation enabled | |
#define | Is_host_sof_interrupt_enabled() (Tst_bits(AVR32_USBB_uhinte, AVR32_USBB_UHINTE_HSOFIE_MASK)) |
#define | Is_host_stall(p) (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_RXSTALLDI_MASK)) |
tests if a STALL has been received | |
#define | Is_host_stall_interrupt_enabled(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_RXSTALLDE_MASK)) |
tests if STALL received interrupt is enabled | |
#define | Is_host_timeout_error(p) (Tst_bits(AVR32_USBB_uperrx(p), AVR32_USBB_UPERRX_TIMEOUT_MASK)) |
#define | Is_host_underflow(p) (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_TXSTPI_MASK)) |
tests if an underflow occurs | |
#define | Is_host_underflow_interrupt_enabled(p) (Tst_bits(AVR32_USBB_upconx(p), AVR32_USBB_UPCONX_TXSTPE_MASK)) |
tests if underflow interrupt is enabled | |
#define | Is_host_write_enabled(p) (Tst_bits(AVR32_USBB_upstax(p), AVR32_USBB_UPSTAX_RWALL_MASK)) |
tests if pipe write allowed | |
#define | Is_usb_address_enabled() (Tst_bits(AVR32_USBB_udcon, AVR32_USBB_UDCON_ADDEN_MASK)) |
#define | Is_usb_bank_interrupt_enabled(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_NBUSYBKE_MASK)) |
tests if all banks full (OUT) or free (IN) interrupt enabled | |
#define | Is_usb_bconnection_error_interrupt() (Tst_bits(AVR32_USBB_usbsta, AVR32_USBB_USBSTA_BCERRI_MASK)) |
tests if a B-device connection error occurs | |
#define | Is_usb_bconnection_error_interrupt_enabled() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_BCERRE_MASK)) |
#define | Is_usb_clock_frozen() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_FRZCLK_MASK)) |
#define | Is_usb_control_in_ready() (Tst_bits(AVR32_USBB_uestax(EP_CONTROL), AVR32_USBB_UESTAX_TXINI_MASK)) |
tests if IN ready on control endpoint | |
#define | Is_usb_control_in_ready_interrupt_enabled() (Tst_bits(AVR32_USBB_ueconx(EP_CONTROL), AVR32_USBB_UECONX_TXINE_MASK)) |
tests if IN ready on control endpoint interrupt is enabled | |
#define | Is_usb_control_out_received() (Tst_bits(AVR32_USBB_uestax(EP_CONTROL), AVR32_USBB_UESTAX_RXOUTI_MASK)) |
tests if OUT received on control endpoint | |
#define | Is_usb_control_out_received_interrupt_enabled() (Tst_bits(AVR32_USBB_ueconx(EP_CONTROL), AVR32_USBB_UECONX_RXOUTE_MASK)) |
tests if OUT received on control endpoint interrupt is enabled | |
#define | Is_usb_crc_error(ep) (Tst_bits(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_STALLEDI_MASK)) |
tests if CRC ERROR ISO OUT detected | |
#define | Is_usb_crc_error_interrupt_enabled(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_STALLEDE_MASK)) |
tests if CRC ERROR ISO OUT detected interrupt is enabled | |
#define | Is_usb_data_srp_method_selected() (!Is_usb_vbus_srp_method_selected()) |
#define | Is_usb_data_toggle_reset(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_RSTDT_MASK)) |
tests if the data toggle sequence is being reset | |
#define | Is_usb_detached() (Tst_bits(AVR32_USBB_udcon, AVR32_USBB_UDCON_DETACH_MASK)) |
test if the device is detached | |
#define | Is_usb_device_mode_forced() (!Is_usb_id_pin_enabled() && Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_UIMOD_MASK)) |
Test if device mode is forced. | |
#define | Is_usb_device_srp() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_SRPREQ_MASK)) |
tests if a SRP from device occurs | |
#define | Is_usb_dpram_byte_write_capable() (Tst_bits(AVR32_USBB_ufeatures, AVR32_USBB_UFEATURES_BYTE_WRITE_DPRAM_MASK)) |
Test if DPRAM is natively byte write capable. | |
#define | Is_usb_enabled() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_USBE_MASK)) |
#define | Is_usb_endpoint_bank_autoswitch_enabled(ep) (Tst_bits(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_AUTOSW_MASK)) |
#define | Is_usb_endpoint_configured(ep) (Tst_bits(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_CFGOK_MASK)) |
tests if current endpoint is configured | |
#define | Is_usb_endpoint_dma_interrupt(epdma) (Tst_bits(AVR32_USBB_udint, AVR32_USBB_UDINT_DMA1INT_MASK << ((epdma) - 1))) |
tests if an interrupt is triggered by the selected endpoint DMA channel | |
#define | Is_usb_endpoint_dma_interrupt_enabled(epdma) (Tst_bits(AVR32_USBB_udinte, AVR32_USBB_UDINTE_DMA1INTE_MASK << ((epdma) - 1))) |
tests if the selected endpoint DMA channel interrupt is enabled | |
#define | Is_usb_endpoint_enabled(ep) (Tst_bits(AVR32_USBB_uerst, AVR32_USBB_UERST_EPEN0_MASK << (ep))) |
tests if the selected endpoint is enabled | |
#define | Is_usb_endpoint_int_dis_hdma_req_enabled(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_EPDISHDMA_MASK)) |
tests if the disabling of HDMA requests by endpoint interrupts is enabled | |
#define | Is_usb_endpoint_interrupt(ep) (Tst_bits(AVR32_USBB_udint, AVR32_USBB_UDINT_EP0INT_MASK << (ep))) |
tests if an interrupt is triggered by the selected endpoint | |
#define | Is_usb_endpoint_interrupt_enabled(ep) (Tst_bits(AVR32_USBB_udinte, AVR32_USBB_UDINTE_EP0INTE_MASK << (ep))) |
tests if the selected endpoint interrupt is enabled | |
#define | Is_usb_endpoint_stall_requested(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_STALLRQ_MASK)) |
tests if STALL handshake request is running | |
#define | Is_usb_fifocon(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_FIFOCON_MASK)) |
tests if FIFOCON bit set | |
#define | Is_usb_frame_number_crc_error() (Tst_bits(AVR32_USBB_udfnum, AVR32_USBB_UDFNUM_FNCERR_MASK)) |
tests if a crc error occurs in frame number | |
#define | Is_usb_full_speed_mode() (Rd_bitfield(AVR32_USBB_usbsta, AVR32_USBB_USBSTA_SPEED_MASK) == AVR32_USBB_USBSTA_SPEED_FULL) |
Test if controller is in full speed mode. | |
#define | Is_usb_full_speed_mode_used() (!Is_usb_low_speed_mode_forced()) |
Test if device full speed mode is used. | |
#define | Is_usb_hnp() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_HNPREQ_MASK)) |
tests if a HNP occurs | |
#define | Is_usb_hnp_error_interrupt() (Tst_bits(AVR32_USBB_usbsta, AVR32_USBB_USBSTA_HNPERRI_MASK)) |
tests if a HNP error occurs | |
#define | Is_usb_hnp_error_interrupt_enabled() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_HNPERRE_MASK)) |
#define | Is_usb_host_mode_forced() (!Is_usb_id_pin_enabled() && !Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_UIMOD_MASK)) |
Test if host mode is forced. | |
#define | Is_usb_id_device() (Tst_bits(AVR32_USBB_usbsta, AVR32_USBB_USBSTA_ID_MASK)) |
#define | Is_usb_id_interrupt_enabled() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_IDTE_MASK)) |
#define | Is_usb_id_pin_enabled() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_UIDE_MASK)) |
Test if external USB_ID pin enabled (listened to by USB). | |
#define | Is_usb_id_pin_input() |
Test if USB_ID is input from its pin. | |
#define | Is_usb_id_transition() (Tst_bits(AVR32_USBB_usbsta, AVR32_USBB_USBSTA_IDTI_MASK)) |
#define | Is_usb_in_ready(ep) (Tst_bits(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_TXINI_MASK)) |
tests if IN ready | |
#define | Is_usb_in_ready_interrupt_enabled(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_TXINE_MASK)) |
tests if IN ready interrupt is enabled | |
#define | Is_usb_in_sent(ep) (Is_usb_fifocon(ep)) |
tests if current bank sent for IN endpoint | |
#define | Is_usb_last_in_bank_killed(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_KILLBK_MASK)) |
tests if last bank killed | |
#define | Is_usb_low_speed_mode() (Rd_bitfield(AVR32_USBB_usbsta, AVR32_USBB_USBSTA_SPEED_MASK) == AVR32_USBB_USBSTA_SPEED_LOW) |
Test if controller is in low-speed mode. | |
#define | Is_usb_low_speed_mode_forced() (Tst_bits(AVR32_USBB_udcon, AVR32_USBB_UDCON_LS_MASK)) |
Test if device low-speed mode is forced. | |
#define | Is_usb_memory_allocated(ep) (Tst_bits(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_ALLOC_MASK)) |
#define | Is_usb_nak_in(ep) (Tst_bits(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_NAKINI_MASK)) |
tests if NAK IN received | |
#define | Is_usb_nak_in_interrupt_enabled(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_NAKINE_MASK)) |
tests if NAK IN interrupt is enabled | |
#define | Is_usb_nak_out(ep) (Tst_bits(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_NAKOUTI_MASK)) |
tests if NAK OUT received | |
#define | Is_usb_nak_out_interrupt_enabled(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_NAKOUTE_MASK)) |
tests if NAK OUT interrupt is enabled | |
#define | Is_usb_otg_pad_enabled() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_OTGPADE_MASK)) |
#define | Is_usb_out_filled(ep) (Is_usb_fifocon(ep)) |
tests if current bank filled for OUT endpoint | |
#define | Is_usb_out_received(ep) (Tst_bits(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_RXOUTI_MASK)) |
tests if OUT received | |
#define | Is_usb_out_received_interrupt_enabled(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_RXOUTE_MASK)) |
tests if OUT received interrupt is enabled | |
#define | Is_usb_overflow(ep) (Tst_bits(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_OVERFI_MASK)) |
tests if an overflow occurs | |
#define | Is_usb_overflow_interrupt_enabled(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_OVERFE_MASK)) |
tests if overflow interrupt is enabled | |
#define | Is_usb_pending_remote_wake_up() (Tst_bits(AVR32_USBB_udcon, AVR32_USBB_UDCON_RMWKUP_MASK)) |
test if remote wake-up still running | |
#define | Is_usb_read_enabled(ep) (Tst_bits(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_RWALL_MASK)) |
tests if endpoint read allowed | |
#define | Is_usb_remote_wake_up_interrupt_enabled() (Tst_bits(AVR32_USBB_udinte, AVR32_USBB_UDINTE_UPRSME_MASK)) |
#define | Is_usb_remote_wake_up_start() (Tst_bits(AVR32_USBB_udint, AVR32_USBB_UDINT_UPRSM_MASK)) |
tests if remote wake-up still running | |
#define | Is_usb_reset() (Tst_bits(AVR32_USBB_udint, AVR32_USBB_UDINT_EORST_MASK)) |
tests if USB reset occurs | |
#define | Is_usb_reset_interrupt_enabled() (Tst_bits(AVR32_USBB_udinte, AVR32_USBB_UDINTE_EORSTE_MASK)) |
#define | Is_usb_resetting_endpoint(ep) (Tst_bits(AVR32_USBB_uerst, AVR32_USBB_UERST_EPRST0_MASK << (ep))) |
tests if the selected endpoint is being reset | |
#define | Is_usb_resume() (Tst_bits(AVR32_USBB_udint, AVR32_USBB_UDINT_EORSM_MASK)) |
tests if resume occurs | |
#define | Is_usb_resume_interrupt_enabled() (Tst_bits(AVR32_USBB_udinte, AVR32_USBB_UDINTE_EORSME_MASK)) |
#define | Is_usb_role_exchange_interrupt() (Tst_bits(AVR32_USBB_usbsta, AVR32_USBB_USBSTA_ROLEEXI_MASK)) |
tests if a role exchange occurs | |
#define | Is_usb_role_exchange_interrupt_enabled() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_ROLEEXE_MASK)) |
#define | Is_usb_setup_received() (Tst_bits(AVR32_USBB_uestax(EP_CONTROL), AVR32_USBB_UESTAX_RXSTPI_MASK)) |
tests if SETUP received | |
#define | Is_usb_setup_received_interrupt_enabled() (Tst_bits(AVR32_USBB_ueconx(EP_CONTROL), AVR32_USBB_UECONX_RXSTPE_MASK)) |
tests if SETUP received interrupt is enabled | |
#define | Is_usb_short_packet(ep) (Tst_bits(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_SHORTPACKETI_MASK)) |
tests if SHORT PACKET received | |
#define | Is_usb_short_packet_interrupt_enabled(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_SHORTPACKETE_MASK)) |
tests if SHORT PACKET received interrupt is enabled | |
#define | Is_usb_sof() (Tst_bits(AVR32_USBB_udint, AVR32_USBB_UDINT_SOF_MASK)) |
tests if Start-of-Frame occurs | |
#define | Is_usb_sof_interrupt_enabled() (Tst_bits(AVR32_USBB_udinte, AVR32_USBB_UDINTE_SOFE_MASK)) |
#define | Is_usb_srp_interrupt() (Tst_bits(AVR32_USBB_usbsta, AVR32_USBB_USBSTA_SRPI_MASK)) |
tests if a SRP occurs | |
#define | Is_usb_srp_interrupt_enabled() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_SRPE_MASK)) |
#define | Is_usb_stall(ep) (Tst_bits(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_STALLEDI_MASK)) |
tests if STALL sent | |
#define | Is_usb_stall_interrupt_enabled(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_STALLEDE_MASK)) |
tests if STALL sent interrupt is enabled | |
#define | Is_usb_suspend() (Tst_bits(AVR32_USBB_udint, AVR32_USBB_UDINT_SUSP_MASK)) |
tests if Suspend state detected | |
#define | Is_usb_suspend_interrupt_enabled() (Tst_bits(AVR32_USBB_udinte, AVR32_USBB_UDINTE_SUSPE_MASK)) |
#define | Is_usb_suspend_time_out_interrupt() (Tst_bits(AVR32_USBB_usbsta, AVR32_USBB_USBSTA_STOI_MASK)) |
tests if a suspend time out occurs | |
#define | Is_usb_suspend_time_out_interrupt_enabled() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_STOE_MASK)) |
#define | Is_usb_underflow(ep) (Tst_bits(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_RXSTPI_MASK)) |
tests if an underflow occurs | |
#define | Is_usb_underflow_interrupt_enabled(ep) (Tst_bits(AVR32_USBB_ueconx(ep), AVR32_USBB_UECONX_RXSTPE_MASK)) |
tests if underflow interrupt is enabled | |
#define | Is_usb_vbof_active_high() (!Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_VBUSPO_MASK)) |
Get USB_VBOF output pin polarity. | |
#define | Is_usb_vbof_active_low() (!Is_usb_vbof_active_high()) |
#define | Is_usb_vbof_pin_output() |
Test if USB_VBOF is output onto its pin. | |
#define | Is_usb_vbus_enabled() (Tst_bits(AVR32_USBB_usbsta, AVR32_USBB_USBSTA_VBUSRQ_MASK)) |
tests if VBus activation has been requested | |
#define | Is_usb_vbus_error_interrupt() (Tst_bits(AVR32_USBB_usbsta, AVR32_USBB_USBSTA_VBERRI_MASK)) |
tests if a VBus error occurs | |
#define | Is_usb_vbus_error_interrupt_enabled() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_VBERRE_MASK)) |
#define | Is_usb_vbus_high() (Tst_bits(AVR32_USBB_usbsta, AVR32_USBB_USBSTA_VBUS_MASK)) |
#define | Is_usb_vbus_hw_control_enabled() (!Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_VBUSHWC_MASK)) |
#define | Is_usb_vbus_interrupt_enabled() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_VBUSTE_MASK)) |
#define | Is_usb_vbus_low() (!Is_usb_vbus_high()) |
#define | Is_usb_vbus_srp_method_selected() (Tst_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_SRPSEL_MASK)) |
#define | Is_usb_vbus_transition() (Tst_bits(AVR32_USBB_usbsta, AVR32_USBB_USBSTA_VBUSTI_MASK)) |
#define | Is_usb_wake_up() (Tst_bits(AVR32_USBB_udint, AVR32_USBB_UDINT_WAKEUP_MASK)) |
tests if wake-up occurs | |
#define | Is_usb_wake_up_interrupt_enabled() (Tst_bits(AVR32_USBB_udinte, AVR32_USBB_UDINTE_WAKEUPE_MASK)) |
#define | Is_usb_write_enabled(ep) (Tst_bits(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_RWALL_MASK)) |
tests if endpoint write allowed | |
#define | MAX_PEP_NB AVR32_USBB_EPT_NUM |
Maximal number of USBB pipes/endpoints. | |
#define | P_0 0 |
#define | P_1 1 |
#define | P_2 2 |
#define | P_3 3 |
#define | P_4 4 |
#define | P_5 5 |
#define | P_6 6 |
#define | P_CONTROL 0 |
#define | PDTMOUTCNT_TIMER AVR32_USBB_USBCON_TIMPAGE_PD_TMOUT_CNT |
#define | PDTMOUTCNT_TMOUT_105_MS AVR32_USBB_USBCON_TIMVALUE_PD_TMOUT_CNT_105_MS |
#define | PDTMOUTCNT_TMOUT_118_MS AVR32_USBB_USBCON_TIMVALUE_PD_TMOUT_CNT_118_MS |
#define | PDTMOUTCNT_TMOUT_131_MS AVR32_USBB_USBCON_TIMVALUE_PD_TMOUT_CNT_131_MS |
#define | PDTMOUTCNT_TMOUT_93_MS AVR32_USBB_USBCON_TIMVALUE_PD_TMOUT_CNT_93_MS |
#define | SINGLE_BANK AVR32_USBB_UECFGX_EPBK_SINGLE |
#define | SRPDETTMOUT_TIMER AVR32_USBB_USBCON_TIMPAGE_SRP_DET_TMOUT |
#define | SRPDETTMOUT_TMOUT_100_US AVR32_USBB_USBCON_TIMVALUE_SRP_DET_TMOUT_100_US |
#define | SRPDETTMOUT_TMOUT_10_US AVR32_USBB_USBCON_TIMVALUE_SRP_DET_TMOUT_10_US |
#define | SRPDETTMOUT_TMOUT_11_MS AVR32_USBB_USBCON_TIMVALUE_SRP_DET_TMOUT_11_MS |
#define | SRPDETTMOUT_TMOUT_1_MS AVR32_USBB_USBCON_TIMVALUE_SRP_DET_TMOUT_1_MS |
#define | TOKEN_IN AVR32_USBB_UPCFGX_PTOKEN_IN |
#define | TOKEN_OUT AVR32_USBB_UPCFGX_PTOKEN_OUT |
#define | TOKEN_SETUP AVR32_USBB_UPCFGX_PTOKEN_SETUP |
#define | TRIPLE_BANK AVR32_USBB_UECFGX_EPBK_TRIPLE |
#define | TYPE_BULK AVR32_USBB_UECFGX_EPTYPE_BULK |
#define | TYPE_CONTROL AVR32_USBB_UECFGX_EPTYPE_CONTROL |
#define | TYPE_INTERRUPT AVR32_USBB_UECFGX_EPTYPE_INTERRUPT |
#define | TYPE_ISOCHRONOUS AVR32_USBB_UECFGX_EPTYPE_ISOCHRONOUS |
#define | Usb_ack_bconnection_error_interrupt() (AVR32_USBB_usbstaclr = AVR32_USBB_USBSTACLR_BCERRIC_MASK) |
acks B-device connection error interrupt | |
#define | Usb_ack_control_in_ready_send() (AVR32_USBB_uestaxclr(EP_CONTROL) = AVR32_USBB_UESTAXCLR_TXINIC_MASK) |
acks IN ready on control endpoint and sends current bank | |
#define | Usb_ack_control_out_received_free() (AVR32_USBB_uestaxclr(EP_CONTROL) = AVR32_USBB_UESTAXCLR_RXOUTIC_MASK) |
acks OUT received on control endpoint and frees current bank | |
#define | Usb_ack_crc_error(ep) (AVR32_USBB_uestaxclr(ep) = AVR32_USBB_UESTAXCLR_STALLEDIC_MASK) |
acks CRC ERROR ISO OUT detected | |
#define | Usb_ack_fifocon(ep) (AVR32_USBB_ueconxclr(ep) = AVR32_USBB_UECONXCLR_FIFOCONC_MASK) |
clears FIFOCON bit | |
#define | Usb_ack_hnp_error_interrupt() (AVR32_USBB_usbstaclr = AVR32_USBB_USBSTACLR_HNPERRIC_MASK) |
acks HNP error interrupt | |
#define | Usb_ack_id_transition() (AVR32_USBB_usbstaclr = AVR32_USBB_USBSTACLR_IDTIC_MASK) |
#define | Usb_ack_in_ready(ep) (AVR32_USBB_uestaxclr(ep) = AVR32_USBB_UESTAXCLR_TXINIC_MASK) |
acks IN ready | |
#define | Usb_ack_in_ready_send(ep) (Usb_ack_in_ready(ep), Usb_send_in(ep)) |
acks IN ready and sends current bank | |
#define | Usb_ack_nak_in(ep) (AVR32_USBB_uestaxclr(ep) = AVR32_USBB_UESTAXCLR_NAKINIC_MASK) |
acks NAK IN received | |
#define | Usb_ack_nak_out(ep) (AVR32_USBB_uestaxclr(ep) = AVR32_USBB_UESTAXCLR_NAKOUTIC_MASK) |
acks NAK OUT received | |
#define | Usb_ack_out_received(ep) (AVR32_USBB_uestaxclr(ep) = AVR32_USBB_UESTAXCLR_RXOUTIC_MASK) |
acks OUT received | |
#define | Usb_ack_out_received_free(ep) (Usb_ack_out_received(ep), Usb_free_out(ep)) |
acks OUT received and frees current bank | |
#define | Usb_ack_overflow_interrupt(ep) (AVR32_USBB_uestaxclr(ep) = AVR32_USBB_UESTAXCLR_OVERFIC_MASK) |
acks endpoint overflow interrupt | |
#define | Usb_ack_remote_wake_up_start() (AVR32_USBB_udintclr = AVR32_USBB_UDINTCLR_UPRSMC_MASK) |
acks remote wake-up | |
#define | Usb_ack_reset() (AVR32_USBB_udintclr = AVR32_USBB_UDINTCLR_EORSTC_MASK) |
acks USB reset | |
#define | Usb_ack_resume() (AVR32_USBB_udintclr = AVR32_USBB_UDINTCLR_EORSMC_MASK) |
acks resume | |
#define | Usb_ack_role_exchange_interrupt() (AVR32_USBB_usbstaclr = AVR32_USBB_USBSTACLR_ROLEEXIC_MASK) |
acks role exchange interrupt | |
#define | Usb_ack_setup_received_free() (AVR32_USBB_uestaxclr(EP_CONTROL) = AVR32_USBB_UESTAXCLR_RXSTPIC_MASK) |
acks SETUP received | |
#define | Usb_ack_short_packet(ep) (AVR32_USBB_uestaxclr(ep) = AVR32_USBB_UESTAXCLR_SHORTPACKETIC_MASK) |
acks SHORT PACKET received | |
#define | Usb_ack_sof() (AVR32_USBB_udintclr = AVR32_USBB_UDINTCLR_SOFC_MASK) |
acks Start-of-Frame | |
#define | Usb_ack_srp_interrupt() (AVR32_USBB_usbstaclr = AVR32_USBB_USBSTACLR_SRPIC_MASK) |
acks SRP interrupt | |
#define | Usb_ack_stall(ep) (AVR32_USBB_uestaxclr(ep) = AVR32_USBB_UESTAXCLR_STALLEDIC_MASK) |
acks STALL sent | |
#define | Usb_ack_suspend() (AVR32_USBB_udintclr = AVR32_USBB_UDINTCLR_SUSPC_MASK) |
acks Suspend | |
#define | Usb_ack_suspend_time_out_interrupt() (AVR32_USBB_usbstaclr = AVR32_USBB_USBSTACLR_STOIC_MASK) |
acks suspend time out interrupt | |
#define | Usb_ack_underflow_interrupt(ep) (AVR32_USBB_uestaxclr(ep) = AVR32_USBB_UESTAXCLR_RXSTPIC_MASK) |
acks endpoint underflow interrupt | |
#define | Usb_ack_vbus_error_interrupt() (AVR32_USBB_usbstaclr = AVR32_USBB_USBSTACLR_VBERRIC_MASK) |
acks VBus error interrupt | |
#define | Usb_ack_vbus_transition() (AVR32_USBB_usbstaclr = AVR32_USBB_USBSTACLR_VBUSTIC_MASK) |
#define | Usb_ack_wake_up() (AVR32_USBB_udintclr = AVR32_USBB_UDINTCLR_WAKEUPC_MASK) |
acks wake-up | |
#define | Usb_allocate_memory(ep) (Set_bits(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_ALLOC_MASK)) |
allocates the configuration x in DPRAM memory | |
#define | Usb_attach() (Clr_bits(AVR32_USBB_udcon, AVR32_USBB_UDCON_DETACH_MASK)) |
attaches to USB bus | |
#define | Usb_byte_count(ep) (Rd_bitfield(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_BYCT_MASK)) |
returns the byte count | |
#define | Usb_configure_address(addr) (Wr_bitfield(AVR32_USBB_udcon, AVR32_USBB_UDCON_UADD_MASK, addr)) |
configures the USB device address | |
#define | Usb_configure_endpoint(ep, type, dir, size, bank) |
configures selected endpoint in one step | |
#define | Usb_configure_endpoint_bank(ep, bank) (Wr_bitfield(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_EPBK_MASK, bank)) |
configures the selected endpoint number of banks | |
#define | Usb_configure_endpoint_direction(ep, dir) (Wr_bitfield(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_EPDIR_MASK, dir)) |
configures the selected endpoint direction | |
#define | Usb_configure_endpoint_size(ep, size) (Wr_bitfield(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_EPSIZE_MASK, Usb_format_endpoint_size(size))) |
configures the selected endpoint size | |
#define | Usb_configure_endpoint_type(ep, type) (Wr_bitfield(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_EPTYPE_MASK, type)) |
configures the selected endpoint type | |
#define | Usb_configure_timeout(timer, timeout) |
Configure time-out of specified OTG timer. | |
#define | Usb_control_direction() (Rd_bitfield(AVR32_USBB_uestax(EP_CONTROL), AVR32_USBB_UESTAX_CTRLDIR_MASK)) |
returns the control direction | |
#define | Usb_current_bank(ep) (Rd_bitfield(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_CURRBK_MASK)) |
returns the number of the current bank | |
#define | Usb_data_toggle(ep) (Rd_bitfield(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_DTSEQ_MASK)) |
returns data toggle | |
#define | Usb_detach() (Set_bits(AVR32_USBB_udcon, AVR32_USBB_UDCON_DETACH_MASK)) |
detaches from USB bus | |
#define | Usb_device_initiate_hnp() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_HNPREQ_MASK)) |
initiates a Host Negociation Protocol | |
#define | Usb_device_initiate_srp() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_SRPREQ_MASK)) |
initiates a Session Request Protocol | |
#define | Usb_disable() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_USBE_MASK)) |
Disable USB macro. | |
#define | Usb_disable_address() (Clr_bits(AVR32_USBB_udcon, AVR32_USBB_UDCON_ADDEN_MASK)) |
disables USB device address | |
#define | Usb_disable_bank_interrupt(ep) (AVR32_USBB_ueconxclr(ep) = AVR32_USBB_UECONXCLR_NBUSYBKEC_MASK) |
disables all banks full (OUT) or free (IN) interrupt | |
#define | Usb_disable_bconnection_error_interrupt() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_BCERRE_MASK)) |
disables B-device connection error interrupt | |
#define | Usb_disable_control_in_ready_interrupt() (AVR32_USBB_ueconxclr(EP_CONTROL) = AVR32_USBB_UECONXCLR_TXINEC_MASK) |
disables IN ready on control endpoint interrupt | |
#define | Usb_disable_control_out_received_interrupt() (AVR32_USBB_ueconxclr(EP_CONTROL) = AVR32_USBB_UECONXCLR_RXOUTEC_MASK) |
disables OUT received on control endpoint interrupt | |
#define | Usb_disable_crc_error_interrupt(ep) (AVR32_USBB_ueconxclr(ep) = AVR32_USBB_UECONXCLR_STALLEDEC_MASK) |
disables CRC ERROR ISO OUT detected interrupt | |
#define | Usb_disable_endpoint(ep) (Clr_bits(AVR32_USBB_uerst, AVR32_USBB_UERST_EPEN0_MASK << (ep))) |
disables the selected endpoint | |
#define | Usb_disable_endpoint_bank_autoswitch(ep) (Clr_bits(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_AUTOSW_MASK)) |
disables the bank autoswitch for the selected endpoint | |
#define | Usb_disable_endpoint_dma_interrupt(epdma) (AVR32_USBB_udinteclr = AVR32_USBB_UDINTECLR_DMA1INTEC_MASK << ((epdma) - 1)) |
disables the selected endpoint DMA channel interrupt | |
#define | Usb_disable_endpoint_int_dis_hdma_req(ep) (AVR32_USBB_ueconxclr(ep) = AVR32_USBB_UECONXCLR_EPDISHDMAC_MASK) |
disables the disabling of HDMA requests by endpoint interrupts | |
#define | Usb_disable_endpoint_interrupt(ep) (AVR32_USBB_udinteclr = AVR32_USBB_UDINTECLR_EP0INTEC_MASK << (ep)) |
disables the selected endpoint interrupt | |
#define | Usb_disable_hnp_error_interrupt() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_HNPERRE_MASK)) |
disables HNP error interrupt | |
#define | Usb_disable_id_interrupt() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_IDTE_MASK)) |
#define | Usb_disable_id_pin() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_UIDE_MASK)) |
Disable external USB_ID pin (ignored by USB). | |
#define | Usb_disable_in_ready_interrupt(ep) (AVR32_USBB_ueconxclr(ep) = AVR32_USBB_UECONXCLR_TXINEC_MASK) |
disables IN ready interrupt | |
#define | Usb_disable_nak_in_interrupt(ep) (AVR32_USBB_ueconxclr(ep) = AVR32_USBB_UECONXCLR_NAKINEC_MASK) |
disables NAK IN interrupt | |
#define | Usb_disable_nak_out_interrupt(ep) (AVR32_USBB_ueconxclr(ep) = AVR32_USBB_UECONXCLR_NAKOUTEC_MASK) |
disables NAK OUT interrupt | |
#define | Usb_disable_otg_pad() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_OTGPADE_MASK)) |
Disable OTG pad. | |
#define | Usb_disable_out_received_interrupt(ep) (AVR32_USBB_ueconxclr(ep) = AVR32_USBB_UECONXCLR_RXOUTEC_MASK) |
disables OUT received interrupt | |
#define | Usb_disable_overflow_interrupt(ep) (AVR32_USBB_ueconxclr(ep) = AVR32_USBB_UECONXCLR_OVERFEC_MASK) |
disables overflow interrupt | |
#define | Usb_disable_remote_wake_up_interrupt() (AVR32_USBB_udinteclr = AVR32_USBB_UDINTECLR_UPRSMEC_MASK) |
disables remote wake-up interrupt | |
#define | Usb_disable_reset_interrupt() (AVR32_USBB_udinteclr = AVR32_USBB_UDINTECLR_EORSTEC_MASK) |
disables USB reset interrupt | |
#define | Usb_disable_resume_interrupt() (AVR32_USBB_udinteclr = AVR32_USBB_UDINTECLR_EORSMEC_MASK) |
disables resume interrupt | |
#define | Usb_disable_role_exchange_interrupt() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_ROLEEXE_MASK)) |
disables role exchange interrupt | |
#define | Usb_disable_setup_received_interrupt() (AVR32_USBB_ueconxclr(EP_CONTROL) = AVR32_USBB_UECONXCLR_RXSTPEC_MASK) |
disables SETUP received interrupt | |
#define | Usb_disable_short_packet_interrupt(ep) (AVR32_USBB_ueconxclr(ep) = AVR32_USBB_UECONXCLR_SHORTPACKETEC_MASK) |
disables SHORT PACKET received interrupt | |
#define | Usb_disable_sof_interrupt() (AVR32_USBB_udinteclr = AVR32_USBB_UDINTECLR_SOFEC_MASK) |
disables Start-of-Frame Interrupt | |
#define | Usb_disable_srp_interrupt() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_SRPE_MASK)) |
disables SRP interrupt | |
#define | Usb_disable_stall_handshake(ep) (AVR32_USBB_ueconxclr(ep) = AVR32_USBB_UECONXCLR_STALLRQC_MASK) |
disables the STALL handshake | |
#define | Usb_disable_stall_interrupt(ep) (AVR32_USBB_ueconxclr(ep) = AVR32_USBB_UECONXCLR_STALLEDEC_MASK) |
disables STALL sent interrupt | |
#define | Usb_disable_suspend_interrupt() (AVR32_USBB_udinteclr = AVR32_USBB_UDINTECLR_SUSPEC_MASK) |
disables suspend state interrupt | |
#define | Usb_disable_suspend_time_out_interrupt() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_STOE_MASK)) |
disables suspend time out interrupt | |
#define | Usb_disable_underflow_interrupt(ep) (AVR32_USBB_ueconxclr(ep) = AVR32_USBB_UECONXCLR_RXSTPEC_MASK) |
disables underflow interrupt | |
#define | Usb_disable_vbus() (AVR32_USBB_usbstaclr = AVR32_USBB_USBSTACLR_VBUSRQC_MASK) |
requests VBus deactivation | |
#define | Usb_disable_vbus_error_interrupt() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_VBERRE_MASK)) |
disables VBus error interrupt | |
#define | Usb_disable_vbus_hw_control() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_VBUSHWC_MASK)) |
disables hardware control over the USB_VBOF output pin | |
#define | Usb_disable_vbus_interrupt() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_VBUSTE_MASK)) |
#define | Usb_disable_wake_up_interrupt() (AVR32_USBB_udinteclr = AVR32_USBB_UDINTECLR_WAKEUPEC_MASK) |
disables wake-up interrupt | |
#define | Usb_enable() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_USBE_MASK)) |
Enable USB macro. | |
#define | Usb_enable_address() (Set_bits(AVR32_USBB_udcon, AVR32_USBB_UDCON_ADDEN_MASK)) |
enables USB device address | |
#define | Usb_enable_bank_interrupt(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_NBUSYBKES_MASK) |
enables all banks full (OUT) or free (IN) interrupt | |
#define | Usb_enable_bconnection_error_interrupt() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_BCERRE_MASK)) |
enables B-device connection error interrupt | |
#define | Usb_enable_control_in_ready_interrupt() (AVR32_USBB_ueconxset(EP_CONTROL) = AVR32_USBB_UECONXSET_TXINES_MASK) |
enables IN ready on control endpoint interrupt | |
#define | Usb_enable_control_out_received_interrupt() (AVR32_USBB_ueconxset(EP_CONTROL) = AVR32_USBB_UECONXSET_RXOUTES_MASK) |
enables OUT received on control endpoint interrupt | |
#define | Usb_enable_crc_error_interrupt(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_STALLEDES_MASK) |
enables CRC ERROR ISO OUT detected interrupt | |
#define | Usb_enable_endpoint(ep) (Set_bits(AVR32_USBB_uerst, AVR32_USBB_UERST_EPEN0_MASK << (ep))) |
enables the selected endpoint | |
#define | Usb_enable_endpoint_bank_autoswitch(ep) (Set_bits(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_AUTOSW_MASK)) |
enables the bank autoswitch for the selected endpoint | |
#define | Usb_enable_endpoint_dma_interrupt(epdma) (AVR32_USBB_udinteset = AVR32_USBB_UDINTESET_DMA1INTES_MASK << ((epdma) - 1)) |
enables the selected endpoint DMA channel interrupt | |
#define | Usb_enable_endpoint_int_dis_hdma_req(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_EPDISHDMAS_MASK) |
enables the disabling of HDMA requests by endpoint interrupts | |
#define | Usb_enable_endpoint_interrupt(ep) (AVR32_USBB_udinteset = AVR32_USBB_UDINTESET_EP0INTES_MASK << (ep)) |
enables the selected endpoint interrupt | |
#define | Usb_enable_hnp_error_interrupt() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_HNPERRE_MASK)) |
enables HNP error interrupt | |
#define | Usb_enable_id_interrupt() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_IDTE_MASK)) |
#define | Usb_enable_id_pin() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_UIDE_MASK)) |
Enable external USB_ID pin (listened to by USB). | |
#define | Usb_enable_in_ready_interrupt(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_TXINES_MASK) |
enables IN ready interrupt | |
#define | Usb_enable_nak_in_interrupt(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_NAKINES_MASK) |
enables NAK IN interrupt | |
#define | Usb_enable_nak_out_interrupt(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_NAKOUTES_MASK) |
enables NAK OUT interrupt | |
#define | Usb_enable_otg_pad() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_OTGPADE_MASK)) |
Enable OTG pad. | |
#define | Usb_enable_out_received_interrupt(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_RXOUTES_MASK) |
enables OUT received interrupt | |
#define | Usb_enable_overflow_interrupt(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_OVERFES_MASK) |
enables overflow interrupt | |
#define | Usb_enable_remote_wake_up_interrupt() (AVR32_USBB_udinteset = AVR32_USBB_UDINTESET_UPRSMES_MASK) |
enables remote wake-up interrupt | |
#define | Usb_enable_reset_interrupt() (AVR32_USBB_udinteset = AVR32_USBB_UDINTESET_EORSTES_MASK) |
enables USB reset interrupt | |
#define | Usb_enable_resume_interrupt() (AVR32_USBB_udinteset = AVR32_USBB_UDINTESET_EORSMES_MASK) |
enables resume interrupt | |
#define | Usb_enable_role_exchange_interrupt() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_ROLEEXE_MASK)) |
enables role exchange interrupt | |
#define | Usb_enable_setup_received_interrupt() (AVR32_USBB_ueconxset(EP_CONTROL) = AVR32_USBB_UECONXSET_RXSTPES_MASK) |
enables SETUP received interrupt | |
#define | Usb_enable_short_packet_interrupt(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_SHORTPACKETES_MASK) |
enables SHORT PACKET received interrupt | |
#define | Usb_enable_sof_interrupt() (AVR32_USBB_udinteset = AVR32_USBB_UDINTESET_SOFES_MASK) |
enables Start-of-Frame Interrupt | |
#define | Usb_enable_srp_interrupt() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_SRPE_MASK)) |
enables SRP interrupt | |
#define | Usb_enable_stall_handshake(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_STALLRQS_MASK) |
enables the STALL handshake | |
#define | Usb_enable_stall_interrupt(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_STALLEDES_MASK) |
enables STALL sent interrupt | |
#define | Usb_enable_suspend_interrupt() (AVR32_USBB_udinteset = AVR32_USBB_UDINTESET_SUSPES_MASK) |
enables suspend state interrupt | |
#define | Usb_enable_suspend_time_out_interrupt() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_STOE_MASK)) |
enables suspend time out interrupt | |
#define | Usb_enable_underflow_interrupt(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_RXSTPES_MASK) |
enables underflow interrupt | |
#define | Usb_enable_vbus() (AVR32_USBB_usbstaset = AVR32_USBB_USBSTASET_VBUSRQS_MASK) |
requests VBus activation | |
#define | Usb_enable_vbus_error_interrupt() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_VBERRE_MASK)) |
enables VBus error interrupt | |
#define | Usb_enable_vbus_hw_control() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_VBUSHWC_MASK)) |
enables hardware control over the USB_VBOF output pin | |
#define | Usb_enable_vbus_interrupt() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_VBUSTE_MASK)) |
#define | Usb_enable_wake_up_interrupt() (AVR32_USBB_udinteset = AVR32_USBB_UDINTESET_WAKEUPES_MASK) |
enables wake-up interrupt | |
#define | Usb_force_bank_interrupt(ep) (AVR32_USBB_uestaxset(ep) = AVR32_USBB_UESTAXSET_NBUSYBKS_MASK) |
forces all banks full (OUT) or free (IN) interrupt | |
#define | Usb_force_device_mode() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_UIMOD_MASK), Usb_disable_id_pin()) |
Disable external USB_ID pin and force device mode. | |
#define | Usb_force_full_speed_mode() do { } while (0) |
#define | Usb_force_host_mode() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_UIMOD_MASK), Usb_disable_id_pin()) |
Disable external USB_ID pin and force host mode. | |
#define | Usb_force_low_speed_mode() (Set_bits(AVR32_USBB_udcon, AVR32_USBB_UDCON_LS_MASK)) |
Force device low-speed mode. | |
#define | Usb_format_endpoint_size(size) (32 - clz(((U32)min(max(size, 8), 1024) << 1) - 1) - 1 - 3) |
Bounds given integer size to allowed range and rounds it up to the nearest available greater size, then applies register format of USBB controller for endpoint size bit-field. | |
#define | Usb_frame_number() (Rd_bitfield(AVR32_USBB_udfnum, AVR32_USBB_UDFNUM_FNUM_MASK)) |
returns the current frame number | |
#define | Usb_free_out(ep) (Usb_ack_fifocon(ep)) |
frees current bank for OUT endpoint | |
#define | Usb_freeze_clock() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_FRZCLK_MASK)) |
Stop (freeze) internal USB clock. | |
#define | Usb_get_configured_address() (Rd_bitfield(AVR32_USBB_udcon, AVR32_USBB_UDCON_UADD_MASK)) |
gets the currently configured USB device address | |
#define | Usb_get_dma_buffer_size() (Rd_bitfield(AVR32_USBB_ufeatures, AVR32_USBB_UFEATURES_DMA_BUFFER_SIZE_MASK)) |
Get DMA buffer size. | |
#define | Usb_get_dma_channel_nbr() (Rd_bitfield(AVR32_USBB_ufeatures, AVR32_USBB_UFEATURES_DMA_CHANNEL_NBR_MASK)) |
Get number of hardware-implemented DMA channels. | |
#define | Usb_get_dma_fifo_word_depth() (((Rd_bitfield(AVR32_USBB_ufeatures, AVR32_USBB_UFEATURES_DMA_FIFO_WORD_DEPTH_MASK) - 1) & ((1 << AVR32_USBB_UFEATURES_DMA_FIFO_WORD_DEPTH_SIZE) - 1)) + 1) |
Get DMA FIFO depth in words. | |
#define | Usb_get_dpram_size() (128 << Rd_bitfield(AVR32_USBB_ufeatures, AVR32_USBB_UFEATURES_FIFO_MAX_SIZE_MASK)) |
Get DPRAM size (FIFO maximal size) in bytes. | |
#define | Usb_get_endpoint_bank(ep) (Rd_bitfield(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_EPBK_MASK)) |
gets the configured selected endpoint number of banks | |
#define | Usb_get_endpoint_direction(ep) (Rd_bitfield(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_EPDIR_MASK)) |
gets the configured selected endpoint direction | |
#define | Usb_get_endpoint_fifo_access(ep, scale) (AVR32_USBB_FIFOX_DATA(ep, scale)) |
Get 64-, 32-, 16- or 8-bit access to FIFO data register of selected endpoint. | |
#define | Usb_get_endpoint_size(ep) (8 << Rd_bitfield(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_EPSIZE_MASK)) |
gets the configured selected endpoint size | |
#define | Usb_get_endpoint_type(ep) (Rd_bitfield(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_EPTYPE_MASK)) |
gets the configured selected endpoint type | |
#define | Usb_get_fsm_drd_state() (Rd_bitfield(AVR32_USBB_usbfsm, AVR32_USBB_USBFSM_DRDSTATE_MASK)) |
Get the dual-role device state of the internal USB finite state machine of the USBB controller. | |
#define | Usb_get_interrupt_endpoint_number() |
returns the lowest endpoint number generating an endpoint interrupt or MAX_PEP_NB if none | |
#define | Usb_get_ip_name(part) (AVR32_USBB_unamex(part)) |
Get IP name part 1 or 2. | |
#define | Usb_get_ip_paddress_size() (AVR32_USBB_uaddrsize) |
Get size of USBB PB address space. | |
#define | Usb_get_ip_version() (Rd_bitfield(AVR32_USBB_uvers, AVR32_USBB_UVERS_VERSION_NUM_MASK)) |
Get IP version. | |
#define | Usb_get_metal_fix_nbr() (Rd_bitfield(AVR32_USBB_uvers, AVR32_USBB_UVERS_METAL_FIX_NUM_MASK)) |
Get number of metal fixes. | |
#define | Usb_get_pipe_endpoint_max_nbr() (((Rd_bitfield(AVR32_USBB_ufeatures, AVR32_USBB_UFEATURES_EPT_NBR_MAX_MASK) - 1) & ((1 << AVR32_USBB_UFEATURES_EPT_NBR_MAX_SIZE) - 1)) + 1) |
Get maximal number of pipes/endpoints (number of hardware-implemented pipes/endpoints). | |
#define | Usb_get_timeout(timer) |
Get configured time-out of specified OTG timer. | |
#define | Usb_halt_endpoint(ep) (Usb_enable_stall_handshake(ep)) |
Sends a STALL handshake for the next host request. | |
#define | Usb_host_accept_hnp() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_HNPREQ_MASK)) |
accepts a Host Negociation Protocol | |
#define | Usb_host_reject_hnp() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_HNPREQ_MASK)) |
rejects a Host Negociation Protocol | |
#define | USB_ID_FUNCTION ATPASTE2(USB_ID, _FUNCTION) |
#define | USB_ID_PIN ATPASTE2(USB_ID, _PIN) |
Check that multiplexed pin used for USB_ID is defined. | |
#define | Usb_initiate_remote_wake_up() (Set_bits(AVR32_USBB_udcon, AVR32_USBB_UDCON_RMWKUP_MASK)) |
initiates a remote wake-up | |
#define | Usb_input_id_pin() |
Input USB_ID from its pin. | |
#define | Usb_kill_last_in_bank(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_KILLBKS_MASK) |
kills last bank | |
#define | Usb_nb_busy_bank(ep) (Rd_bitfield(AVR32_USBB_uestax(ep), AVR32_USBB_UESTAX_NBUSYBK_MASK)) |
returns the number of busy banks | |
#define | Usb_output_vbof_pin() |
Output USB_VBOF onto its pin. | |
#define | Usb_raise_bconnection_error_interrupt() (AVR32_USBB_usbstaset = AVR32_USBB_USBSTASET_BCERRIS_MASK) |
raises B-device connection error interrupt | |
#define | Usb_raise_control_in_ready() (AVR32_USBB_uestaxset(EP_CONTROL) = AVR32_USBB_UESTAXSET_TXINIS_MASK) |
raises IN ready on control endpoint | |
#define | Usb_raise_control_out_received() (AVR32_USBB_uestaxset(EP_CONTROL) = AVR32_USBB_UESTAXSET_RXOUTIS_MASK) |
raises OUT received on control endpoint | |
#define | Usb_raise_crc_error(ep) (AVR32_USBB_uestaxset(ep) = AVR32_USBB_UESTAXSET_STALLEDIS_MASK) |
raises CRC ERROR ISO OUT detected | |
#define | Usb_raise_endpoint_dma_interrupt(epdma) (AVR32_USBB_udintset = AVR32_USBB_UDINTSET_DMA1INTS_MASK << ((epdma) - 1)) |
raises the selected endpoint DMA channel interrupt | |
#define | Usb_raise_hnp_error_interrupt() (AVR32_USBB_usbstaset = AVR32_USBB_USBSTASET_HNPERRIS_MASK) |
raises HNP error interrupt | |
#define | Usb_raise_id_transition() (AVR32_USBB_usbstaset = AVR32_USBB_USBSTASET_IDTIS_MASK) |
#define | Usb_raise_in_ready(ep) (AVR32_USBB_uestaxset(ep) = AVR32_USBB_UESTAXSET_TXINIS_MASK) |
raises IN ready | |
#define | Usb_raise_nak_in(ep) (AVR32_USBB_uestaxset(ep) = AVR32_USBB_UESTAXSET_NAKINIS_MASK) |
raises NAK IN received | |
#define | Usb_raise_nak_out(ep) (AVR32_USBB_uestaxset(ep) = AVR32_USBB_UESTAXSET_NAKOUTIS_MASK) |
raises NAK OUT received | |
#define | Usb_raise_out_received(ep) (AVR32_USBB_uestaxset(ep) = AVR32_USBB_UESTAXSET_RXOUTIS_MASK) |
raises OUT received | |
#define | Usb_raise_overflow_interrupt(ep) (AVR32_USBB_uestaxset(ep) = AVR32_USBB_UESTAXSET_OVERFIS_MASK) |
raises endpoint overflow interrupt | |
#define | Usb_raise_remote_wake_up_start() (AVR32_USBB_udintset = AVR32_USBB_UDINTSET_UPRSMS_MASK) |
raises remote wake-up | |
#define | Usb_raise_reset() (AVR32_USBB_udintset = AVR32_USBB_UDINTSET_EORSTS_MASK) |
raises USB reset | |
#define | Usb_raise_resume() (AVR32_USBB_udintset = AVR32_USBB_UDINTSET_EORSMS_MASK) |
raises resume | |
#define | Usb_raise_role_exchange_interrupt() (AVR32_USBB_usbstaset = AVR32_USBB_USBSTASET_ROLEEXIS_MASK) |
raises role exchange interrupt | |
#define | Usb_raise_setup_received() (AVR32_USBB_uestaxset(EP_CONTROL) = AVR32_USBB_UESTAXSET_RXSTPIS_MASK) |
raises SETUP received | |
#define | Usb_raise_short_packet(ep) (AVR32_USBB_uestaxset(ep) = AVR32_USBB_UESTAXSET_SHORTPACKETIS_MASK) |
raises SHORT PACKET received | |
#define | Usb_raise_sof() (AVR32_USBB_udintset = AVR32_USBB_UDINTSET_SOFS_MASK) |
raises Start-of-Frame | |
#define | Usb_raise_srp_interrupt() (AVR32_USBB_usbstaset = AVR32_USBB_USBSTASET_SRPIS_MASK) |
raises SRP interrupt | |
#define | Usb_raise_stall(ep) (AVR32_USBB_uestaxset(ep) = AVR32_USBB_UESTAXSET_STALLEDIS_MASK) |
raises STALL sent | |
#define | Usb_raise_suspend() (AVR32_USBB_udintset = AVR32_USBB_UDINTSET_SUSPS_MASK) |
raises Suspend | |
#define | Usb_raise_suspend_time_out_interrupt() (AVR32_USBB_usbstaset = AVR32_USBB_USBSTASET_STOIS_MASK) |
raises suspend time out interrupt | |
#define | Usb_raise_underflow_interrupt(ep) (AVR32_USBB_uestaxset(ep) = AVR32_USBB_UESTAXSET_RXSTPIS_MASK) |
raises endpoint underflow interrupt | |
#define | Usb_raise_vbus_error_interrupt() (AVR32_USBB_usbstaset = AVR32_USBB_USBSTASET_VBERRIS_MASK) |
raises VBus error interrupt | |
#define | Usb_raise_vbus_transition() (AVR32_USBB_usbstaset = AVR32_USBB_USBSTASET_VBUSTIS_MASK) |
#define | Usb_raise_wake_up() (AVR32_USBB_udintset = AVR32_USBB_UDINTSET_WAKEUPS_MASK) |
raises wake-up | |
#define | Usb_read_endpoint_data(ep, scale) |
Read 64-, 32-, 16- or 8-bit data from FIFO data register of selected endpoint. | |
#define | Usb_read_endpoint_indexed_data(ep, scale, index) (AVR32_USBB_FIFOX_DATA(ep, scale)[(index)]) |
Read 64-, 32-, 16- or 8-bit indexed data from FIFO data register of selected endpoint. | |
#define | Usb_reset_data_toggle(ep) (AVR32_USBB_ueconxset(ep) = AVR32_USBB_UECONXSET_RSTDTS_MASK) |
resets the data toggle sequence | |
#define | Usb_reset_endpoint(ep) |
resets the selected endpoint | |
#define | Usb_reset_endpoint_fifo_access(ep) (pep_fifo[(ep)].u64ptr = Usb_get_endpoint_fifo_access(ep, 64)) |
Reset known position inside FIFO data register of selected endpoint. | |
#define | Usb_select_data_srp_method() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_SRPSEL_MASK)) |
selects data line as SRP method | |
#define | Usb_select_vbus_srp_method() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_SRPSEL_MASK)) |
selects VBus as SRP method | |
#define | Usb_send_in(ep) (Usb_ack_fifocon(ep)) |
sends current bank for IN endpoint | |
#define | Usb_set_vbof_active_high() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_VBUSPO_MASK)) |
Set USB_VBOF output pin polarity. | |
#define | Usb_set_vbof_active_low() (Set_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_VBUSPO_MASK)) |
#define | Usb_unallocate_memory(ep) (Clr_bits(AVR32_USBB_uecfgx(ep), AVR32_USBB_UECFGX_ALLOC_MASK)) |
un-allocates the configuration x in DPRAM memory | |
#define | Usb_unforce_bank_interrupt(ep) (AVR32_USBB_uestaxset(ep) = AVR32_USBB_UESTAXSET_NBUSYBKS_MASK) |
unforces all banks full (OUT) or free (IN) interrupt | |
#define | Usb_unfreeze_clock() (Clr_bits(AVR32_USBB_usbcon, AVR32_USBB_USBCON_FRZCLK_MASK)) |
#define | Usb_use_dual_speed_mode() do { } while (0) |
#define | Usb_use_full_speed_mode() (Clr_bits(AVR32_USBB_udcon, AVR32_USBB_UDCON_LS_MASK)) |
Use device full speed mode (default). | |
#define | USB_VBOF_FUNCTION ATPASTE2(USB_VBOF, _FUNCTION) |
#define | USB_VBOF_PIN ATPASTE2(USB_VBOF, _PIN) |
Check that multiplexed pin used for USB_VBOF is defined. | |
#define | Usb_write_endpoint_data(ep, scale, data) |
Write 64-, 32-, 16- or 8-bit data to FIFO data register of selected endpoint. | |
#define | Usb_write_endpoint_indexed_data(ep, scale, index, data) (AVR32_USBB_FIFOX_DATA(ep, scale)[(index)] = (data)) |
Write 64-, 32-, 16- or 8-bit indexed data to FIFO data register of selected endpoint. | |
#define | VBBUSPULSING_TIMER AVR32_USBB_USBCON_TIMPAGE_VB_BUS_PULSING |
#define | VBBUSPULSING_TMOUT_15_MS AVR32_USBB_USBCON_TIMVALUE_VB_BUS_PULSING_15_MS |
#define | VBBUSPULSING_TMOUT_23_MS AVR32_USBB_USBCON_TIMVALUE_VB_BUS_PULSING_23_MS |
#define | VBBUSPULSING_TMOUT_31_MS AVR32_USBB_USBCON_TIMVALUE_VB_BUS_PULSING_31_MS |
#define | VBBUSPULSING_TMOUT_40_MS AVR32_USBB_USBCON_TIMVALUE_VB_BUS_PULSING_40_MS |
#define | Pep_fifo_access_16_post_inc() ++ |
#define | Pep_fifo_access_32_post_inc() |
#define | Pep_fifo_access_64_post_inc() |
Post-increment operations associated with 64-, 32-, 16- and 8-bit accesses to the FIFO data registers of pipes/endpoints. | |
#define | Pep_fifo_access_8_post_inc() ++ |
Functions | |
void | host_disable_all_pipes (void) |
--------------------------------------------------------- ------------------ HOST --------------------------------- --------------------------------------------------------- | |
U32 | host_read_p_rxpacket (U8, void *, U32, void **) |
host_read_p_rxpacket | |
U32 | host_set_p_txpacket (U8, U8, U32) |
host_set_p_txpacket | |
U32 | host_write_p_txpacket (U8, const void *, U32, const void **) |
host_write_p_txpacket | |
Status_bool_t | usb_init_device (void) |
--------------------------------------------------------- ------------------ DEVICE ------------------------------- --------------------------------------------------------- | |
U32 | usb_read_ep_rxpacket (U8, void *, U32, void **) |
usb_read_ep_rxpacket | |
U32 | usb_set_ep_txpacket (U8, U8, U32) |
usb_set_ep_txpacket | |
U32 | usb_write_ep_txpacket (U8, const void *, U32, const void **) |
usb_write_ep_txpacket | |
Variables | |
UnionVPtr | pep_fifo [MAX_PEP_NB] |
Pointers to the FIFO data registers of pipes/endpoints Use aggregated pointers to have several alignments available for a same address. |
void host_disable_all_pipes | ( | void | ) |
--------------------------------------------------------- ------------------ HOST --------------------------------- ---------------------------------------------------------
host_disable_all_pipes This function disables all pipes for the host controller. Useful to execute upon disconnection.
Definition at line 468 of file usb_drv.c.
References Host_disable_pipe, Host_disable_pipe_interrupt, Host_reset_pipe, Host_unallocate_memory, Is_host_pipe_enabled, and MAX_PEP_NB.
Referenced by usb_general_interrupt_non_naked(), and usb_host_task().
00469 { 00470 #if USB_HOST_PIPE_INTERRUPT_TRANSFER == ENABLE 00471 Bool sav_glob_int_en; 00472 #endif 00473 U8 p; 00474 00475 #if USB_HOST_PIPE_INTERRUPT_TRANSFER == ENABLE 00476 // Disable global interrupts 00477 if ((sav_glob_int_en = Is_global_interrupt_enabled())) Disable_global_interrupt(); 00478 #endif 00479 for (p = 0; p < MAX_PEP_NB; p++) 00480 { // Disable the pipe <p> (disable interrupt, free memory, reset pipe, ...) 00481 Host_disable_pipe_interrupt(p); 00482 Host_reset_pipe(p); 00483 Host_unallocate_memory(p); 00484 Host_disable_pipe(p); 00485 } 00486 #if USB_HOST_PIPE_INTERRUPT_TRANSFER == ENABLE 00487 (void)Is_host_pipe_enabled(MAX_PEP_NB - 1); 00488 // Restore the global interrupts to the initial state 00489 if (sav_glob_int_en) Enable_global_interrupt(); 00490 #endif 00491 }
U32 host_read_p_rxpacket | ( | U8 | p, | |
void * | rxbuf, | |||
U32 | data_length, | |||
void ** | prxbuf | |||
) |
host_read_p_rxpacket
This function reads the selected pipe FIFO to the buffer pointed to by rxbuf, using as few accesses as possible.
p | Number of the addressed pipe | |
rxbuf | Address of buffer to write | |
data_length | Number of bytes to read | |
prxbuf | NULL or pointer to the buffer address to update |
Do not mix calls to this function with calls to indexed macros.
Definition at line 756 of file usb_drv.c.
References Host_byte_count, and pep_fifo.
Referenced by host_get_data(), host_transfer_control(), and usb_pipe_interrupt().
00757 { 00758 // Use aggregated pointers to have several alignments available for a same address 00759 UnionCVPtr p_fifo; 00760 UnionPtr rxbuf_cur; 00761 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00762 StructCPtr rxbuf_end; 00763 #else 00764 UnionCPtr rxbuf_end; 00765 #endif // !__OPTIMIZE_SIZE__ 00766 00767 // Initialize pointers for copy loops and limit the number of bytes to copy 00768 p_fifo.u8ptr = pep_fifo[p].u8ptr; 00769 rxbuf_cur.u8ptr = rxbuf; 00770 rxbuf_end.u8ptr = rxbuf_cur.u8ptr + min(data_length, Host_byte_count(p)); 00771 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00772 rxbuf_end.u16ptr = (U16 *)Align_down((U32)rxbuf_end.u8ptr, sizeof(U16)); 00773 rxbuf_end.u32ptr = (U32 *)Align_down((U32)rxbuf_end.u16ptr, sizeof(U32)); 00774 rxbuf_end.u64ptr = (U64 *)Align_down((U32)rxbuf_end.u32ptr, sizeof(U64)); 00775 00776 // If all addresses are aligned the same way with respect to 16-bit boundaries 00777 if (Get_align((U32)rxbuf_cur.u8ptr, sizeof(U16)) == Get_align((U32)p_fifo.u8ptr, sizeof(U16))) 00778 { 00779 // If pointer to reception buffer is not 16-bit aligned 00780 if (!Test_align((U32)rxbuf_cur.u8ptr, sizeof(U16))) 00781 { 00782 // Copy 8-bit data to reach 16-bit alignment 00783 if (rxbuf_cur.u8ptr < rxbuf_end.u8ptr) 00784 { 00785 // 8-bit accesses to FIFO data registers do require pointer post-increment 00786 *rxbuf_cur.u8ptr++ = *p_fifo.u8ptr++; 00787 } 00788 } 00789 00790 // If all addresses are aligned the same way with respect to 32-bit boundaries 00791 if (Get_align((U32)rxbuf_cur.u16ptr, sizeof(U32)) == Get_align((U32)p_fifo.u16ptr, sizeof(U32))) 00792 { 00793 // If pointer to reception buffer is not 32-bit aligned 00794 if (!Test_align((U32)rxbuf_cur.u16ptr, sizeof(U32))) 00795 { 00796 // Copy 16-bit data to reach 32-bit alignment 00797 if (rxbuf_cur.u16ptr < rxbuf_end.u16ptr) 00798 { 00799 // 16-bit accesses to FIFO data registers do require pointer post-increment 00800 *rxbuf_cur.u16ptr++ = *p_fifo.u16ptr++; 00801 } 00802 } 00803 00804 // If pointer to reception buffer is not 64-bit aligned 00805 if (!Test_align((U32)rxbuf_cur.u32ptr, sizeof(U64))) 00806 { 00807 // Copy 32-bit data to reach 64-bit alignment 00808 if (rxbuf_cur.u32ptr < rxbuf_end.u32ptr) 00809 { 00810 // 32-bit accesses to FIFO data registers do not require pointer post-increment 00811 *rxbuf_cur.u32ptr++ = *p_fifo.u32ptr; 00812 } 00813 } 00814 00815 // Copy 64-bit-aligned data 00816 while (rxbuf_cur.u64ptr < rxbuf_end.u64ptr) 00817 { 00818 // 64-bit accesses to FIFO data registers do not require pointer post-increment 00819 *rxbuf_cur.u64ptr++ = *p_fifo.u64ptr; 00820 } 00821 00822 // Copy 32-bit-aligned data 00823 if (rxbuf_cur.u32ptr < rxbuf_end.u32ptr) 00824 { 00825 // 32-bit accesses to FIFO data registers do not require pointer post-increment 00826 *rxbuf_cur.u32ptr++ = *p_fifo.u32ptr; 00827 } 00828 } 00829 00830 // Copy remaining 16-bit data if some 00831 while (rxbuf_cur.u16ptr < rxbuf_end.u16ptr) 00832 { 00833 // 16-bit accesses to FIFO data registers do require pointer post-increment 00834 *rxbuf_cur.u16ptr++ = *p_fifo.u16ptr++; 00835 } 00836 } 00837 00838 #endif // !__OPTIMIZE_SIZE__ 00839 00840 // Copy remaining 8-bit data if some 00841 while (rxbuf_cur.u8ptr < rxbuf_end.u8ptr) 00842 { 00843 // 8-bit accesses to FIFO data registers do require pointer post-increment 00844 *rxbuf_cur.u8ptr++ = *p_fifo.u8ptr++; 00845 } 00846 00847 // Save current position in FIFO data register 00848 pep_fifo[p].u8ptr = (volatile U8 *)p_fifo.u8ptr; 00849 00850 // Return the updated buffer address and the number of non-copied bytes 00851 if (prxbuf) *prxbuf = rxbuf_cur.u8ptr; 00852 return data_length - (rxbuf_cur.u8ptr - (U8 *)rxbuf); 00853 }
U32 host_set_p_txpacket | ( | U8 | p, | |
U8 | txbyte, | |||
U32 | data_length | |||
) |
host_set_p_txpacket
This function fills the selected pipe FIFO with a constant byte, using as few accesses as possible.
p | Number of the addressed pipe | |
txbyte | Byte to fill the pipe with | |
data_length | Number of bytes to write |
Do not mix calls to this function with calls to indexed macros.
Definition at line 512 of file usb_drv.c.
References Host_byte_count, Host_get_pipe_size, and pep_fifo.
00513 { 00514 // Use aggregated pointers to have several alignments available for a same address 00515 UnionVPtr p_fifo_cur; 00516 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00517 StructCVPtr p_fifo_end; 00518 Union64 txval; 00519 #else 00520 UnionCVPtr p_fifo_end; 00521 union 00522 { 00523 U8 u8[1]; 00524 } txval; 00525 #endif // !__OPTIMIZE_SIZE__ 00526 00527 // Initialize pointers for write loops and limit the number of bytes to write 00528 p_fifo_cur.u8ptr = pep_fifo[p].u8ptr; 00529 p_fifo_end.u8ptr = p_fifo_cur.u8ptr + 00530 min(data_length, Host_get_pipe_size(p) - Host_byte_count(p)); 00531 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00532 p_fifo_end.u16ptr = (U16 *)Align_down((U32)p_fifo_end.u8ptr, sizeof(U16)); 00533 p_fifo_end.u32ptr = (U32 *)Align_down((U32)p_fifo_end.u16ptr, sizeof(U32)); 00534 p_fifo_end.u64ptr = (U64 *)Align_down((U32)p_fifo_end.u32ptr, sizeof(U64)); 00535 #endif // !__OPTIMIZE_SIZE__ 00536 txval.u8[0] = txbyte; 00537 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00538 txval.u8[1] = txval.u8[0]; 00539 txval.u16[1] = txval.u16[0]; 00540 txval.u32[1] = txval.u32[0]; 00541 00542 // If pointer to FIFO data register is not 16-bit aligned 00543 if (!Test_align((U32)p_fifo_cur.u8ptr, sizeof(U16))) 00544 { 00545 // Write 8-bit data to reach 16-bit alignment 00546 if (p_fifo_cur.u8ptr < p_fifo_end.u8ptr) 00547 { 00548 *p_fifo_cur.u8ptr++ = txval.u8[0]; 00549 } 00550 } 00551 00552 // If pointer to FIFO data register is not 32-bit aligned 00553 if (!Test_align((U32)p_fifo_cur.u16ptr, sizeof(U32))) 00554 { 00555 // Write 16-bit data to reach 32-bit alignment 00556 if (p_fifo_cur.u16ptr < p_fifo_end.u16ptr) 00557 { 00558 *p_fifo_cur.u16ptr++ = txval.u16[0]; 00559 } 00560 } 00561 00562 // If pointer to FIFO data register is not 64-bit aligned 00563 if (!Test_align((U32)p_fifo_cur.u32ptr, sizeof(U64))) 00564 { 00565 // Write 32-bit data to reach 64-bit alignment 00566 if (p_fifo_cur.u32ptr < p_fifo_end.u32ptr) 00567 { 00568 *p_fifo_cur.u32ptr++ = txval.u32[0]; 00569 } 00570 } 00571 00572 // Write 64-bit-aligned data 00573 while (p_fifo_cur.u64ptr < p_fifo_end.u64ptr) 00574 { 00575 *p_fifo_cur.u64ptr++ = txval.u64; 00576 } 00577 00578 // Write remaining 32-bit data if some 00579 if (p_fifo_cur.u32ptr < p_fifo_end.u32ptr) 00580 { 00581 *p_fifo_cur.u32ptr++ = txval.u32[0]; 00582 } 00583 00584 // Write remaining 16-bit data if some 00585 if (p_fifo_cur.u16ptr < p_fifo_end.u16ptr) 00586 { 00587 *p_fifo_cur.u16ptr++ = txval.u16[0]; 00588 } 00589 00590 // Write remaining 8-bit data if some 00591 if (p_fifo_cur.u8ptr < p_fifo_end.u8ptr) 00592 { 00593 *p_fifo_cur.u8ptr++ = txval.u8[0]; 00594 } 00595 00596 #else 00597 00598 // Write remaining 8-bit data if some 00599 while (p_fifo_cur.u8ptr < p_fifo_end.u8ptr) 00600 { 00601 *p_fifo_cur.u8ptr++ = txval.u8[0]; 00602 } 00603 00604 #endif // !__OPTIMIZE_SIZE__ 00605 00606 // Compute the number of non-written bytes 00607 data_length -= p_fifo_cur.u8ptr - pep_fifo[p].u8ptr; 00608 00609 // Save current position in FIFO data register 00610 pep_fifo[p].u8ptr = p_fifo_cur.u8ptr; 00611 00612 // Return the number of non-written bytes 00613 return data_length; 00614 }
U32 host_write_p_txpacket | ( | U8 | p, | |
const void * | txbuf, | |||
U32 | data_length, | |||
const void ** | ptxbuf | |||
) |
host_write_p_txpacket
This function writes the buffer pointed to by txbuf to the selected pipe FIFO, using as few accesses as possible.
p | Number of the addressed pipe | |
txbuf | Address of buffer to read | |
data_length | Number of bytes to write | |
ptxbuf | NULL or pointer to the buffer address to update |
Do not mix calls to this function with calls to indexed macros.
Definition at line 636 of file usb_drv.c.
References Host_byte_count, Host_get_pipe_size, and pep_fifo.
Referenced by host_send_data(), host_send_data_interrupt(), host_transfer_control(), and usb_pipe_interrupt().
00637 { 00638 // Use aggregated pointers to have several alignments available for a same address 00639 UnionVPtr p_fifo; 00640 UnionCPtr txbuf_cur; 00641 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00642 StructCPtr txbuf_end; 00643 #else 00644 UnionCPtr txbuf_end; 00645 #endif // !__OPTIMIZE_SIZE__ 00646 00647 // Initialize pointers for copy loops and limit the number of bytes to copy 00648 p_fifo.u8ptr = pep_fifo[p].u8ptr; 00649 txbuf_cur.u8ptr = txbuf; 00650 txbuf_end.u8ptr = txbuf_cur.u8ptr + 00651 min(data_length, Host_get_pipe_size(p) - Host_byte_count(p)); 00652 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00653 txbuf_end.u16ptr = (U16 *)Align_down((U32)txbuf_end.u8ptr, sizeof(U16)); 00654 txbuf_end.u32ptr = (U32 *)Align_down((U32)txbuf_end.u16ptr, sizeof(U32)); 00655 txbuf_end.u64ptr = (U64 *)Align_down((U32)txbuf_end.u32ptr, sizeof(U64)); 00656 00657 // If all addresses are aligned the same way with respect to 16-bit boundaries 00658 if (Get_align((U32)txbuf_cur.u8ptr, sizeof(U16)) == Get_align((U32)p_fifo.u8ptr, sizeof(U16))) 00659 { 00660 // If pointer to transmission buffer is not 16-bit aligned 00661 if (!Test_align((U32)txbuf_cur.u8ptr, sizeof(U16))) 00662 { 00663 // Copy 8-bit data to reach 16-bit alignment 00664 if (txbuf_cur.u8ptr < txbuf_end.u8ptr) 00665 { 00666 // 8-bit accesses to FIFO data registers do require pointer post-increment 00667 *p_fifo.u8ptr++ = *txbuf_cur.u8ptr++; 00668 } 00669 } 00670 00671 // If all addresses are aligned the same way with respect to 32-bit boundaries 00672 if (Get_align((U32)txbuf_cur.u16ptr, sizeof(U32)) == Get_align((U32)p_fifo.u16ptr, sizeof(U32))) 00673 { 00674 // If pointer to transmission buffer is not 32-bit aligned 00675 if (!Test_align((U32)txbuf_cur.u16ptr, sizeof(U32))) 00676 { 00677 // Copy 16-bit data to reach 32-bit alignment 00678 if (txbuf_cur.u16ptr < txbuf_end.u16ptr) 00679 { 00680 // 16-bit accesses to FIFO data registers do require pointer post-increment 00681 *p_fifo.u16ptr++ = *txbuf_cur.u16ptr++; 00682 } 00683 } 00684 00685 // If pointer to transmission buffer is not 64-bit aligned 00686 if (!Test_align((U32)txbuf_cur.u32ptr, sizeof(U64))) 00687 { 00688 // Copy 32-bit data to reach 64-bit alignment 00689 if (txbuf_cur.u32ptr < txbuf_end.u32ptr) 00690 { 00691 // 32-bit accesses to FIFO data registers do not require pointer post-increment 00692 *p_fifo.u32ptr = *txbuf_cur.u32ptr++; 00693 } 00694 } 00695 00696 // Copy 64-bit-aligned data 00697 while (txbuf_cur.u64ptr < txbuf_end.u64ptr) 00698 { 00699 // 64-bit accesses to FIFO data registers do not require pointer post-increment 00700 *p_fifo.u64ptr = *txbuf_cur.u64ptr++; 00701 } 00702 00703 // Copy 32-bit-aligned data 00704 if (txbuf_cur.u32ptr < txbuf_end.u32ptr) 00705 { 00706 // 32-bit accesses to FIFO data registers do not require pointer post-increment 00707 *p_fifo.u32ptr = *txbuf_cur.u32ptr++; 00708 } 00709 } 00710 00711 // Copy remaining 16-bit data if some 00712 while (txbuf_cur.u16ptr < txbuf_end.u16ptr) 00713 { 00714 // 16-bit accesses to FIFO data registers do require pointer post-increment 00715 *p_fifo.u16ptr++ = *txbuf_cur.u16ptr++; 00716 } 00717 } 00718 00719 #endif // !__OPTIMIZE_SIZE__ 00720 00721 // Copy remaining 8-bit data if some 00722 while (txbuf_cur.u8ptr < txbuf_end.u8ptr) 00723 { 00724 // 8-bit accesses to FIFO data registers do require pointer post-increment 00725 *p_fifo.u8ptr++ = *txbuf_cur.u8ptr++; 00726 } 00727 00728 // Save current position in FIFO data register 00729 pep_fifo[p].u8ptr = p_fifo.u8ptr; 00730 00731 // Return the updated buffer address and the number of non-copied bytes 00732 if (ptxbuf) *ptxbuf = txbuf_cur.u8ptr; 00733 return data_length - (txbuf_cur.u8ptr - (U8 *)txbuf); 00734 }
Status_bool_t usb_init_device | ( | void | ) |
--------------------------------------------------------- ------------------ DEVICE ------------------------------- ---------------------------------------------------------
usb_init_device This function initializes the USB device controller and configures the Default Control Endpoint.
Definition at line 81 of file usb_drv.c.
References DIRECTION_OUT, EP_CONTROL, EP_CONTROL_LENGTH, Is_usb_endpoint_enabled, Is_usb_id_device, SINGLE_BANK, TYPE_CONTROL, and Usb_configure_endpoint.
Referenced by usb_general_interrupt_non_naked(), and usb_start_device().
00082 { 00083 return Is_usb_id_device() && !Is_usb_endpoint_enabled(EP_CONTROL) && 00084 Usb_configure_endpoint(EP_CONTROL, 00085 TYPE_CONTROL, 00086 DIRECTION_OUT, 00087 EP_CONTROL_LENGTH, 00088 SINGLE_BANK); 00089 }
U32 usb_read_ep_rxpacket | ( | U8 | ep, | |
void * | rxbuf, | |||
U32 | data_length, | |||
void ** | prxbuf | |||
) |
usb_read_ep_rxpacket
This function reads the selected endpoint FIFO to the buffer pointed to by rxbuf, using as few accesses as possible.
ep | Number of the addressed endpoint | |
rxbuf | Address of buffer to write | |
data_length | Number of bytes to read | |
prxbuf | NULL or pointer to the buffer address to update |
Do not mix calls to this function with calls to indexed macros.
Definition at line 354 of file usb_drv.c.
References pep_fifo, and Usb_byte_count.
Referenced by device_template_task().
00355 { 00356 // Use aggregated pointers to have several alignments available for a same address 00357 UnionCVPtr ep_fifo; 00358 UnionPtr rxbuf_cur; 00359 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00360 StructCPtr rxbuf_end; 00361 #else 00362 StructCPtr rxbuf_end; 00363 #endif // !__OPTIMIZE_SIZE__ 00364 00365 // Initialize pointers for copy loops and limit the number of bytes to copy 00366 ep_fifo.u8ptr = pep_fifo[ep].u8ptr; 00367 rxbuf_cur.u8ptr = rxbuf; 00368 rxbuf_end.u8ptr = rxbuf_cur.u8ptr + min(data_length, Usb_byte_count(ep)); 00369 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00370 rxbuf_end.u16ptr = (U16 *)Align_down((U32)rxbuf_end.u8ptr, sizeof(U16)); 00371 rxbuf_end.u32ptr = (U32 *)Align_down((U32)rxbuf_end.u16ptr, sizeof(U32)); 00372 rxbuf_end.u64ptr = (U64 *)Align_down((U32)rxbuf_end.u32ptr, sizeof(U64)); 00373 00374 // If all addresses are aligned the same way with respect to 16-bit boundaries 00375 if (Get_align((U32)rxbuf_cur.u8ptr, sizeof(U16)) == Get_align((U32)ep_fifo.u8ptr, sizeof(U16))) 00376 { 00377 // If pointer to reception buffer is not 16-bit aligned 00378 if (!Test_align((U32)rxbuf_cur.u8ptr, sizeof(U16))) 00379 { 00380 // Copy 8-bit data to reach 16-bit alignment 00381 if (rxbuf_cur.u8ptr < rxbuf_end.u8ptr) 00382 { 00383 // 8-bit accesses to FIFO data registers do require pointer post-increment 00384 *rxbuf_cur.u8ptr++ = *ep_fifo.u8ptr++; 00385 } 00386 } 00387 00388 // If all addresses are aligned the same way with respect to 32-bit boundaries 00389 if (Get_align((U32)rxbuf_cur.u16ptr, sizeof(U32)) == Get_align((U32)ep_fifo.u16ptr, sizeof(U32))) 00390 { 00391 // If pointer to reception buffer is not 32-bit aligned 00392 if (!Test_align((U32)rxbuf_cur.u16ptr, sizeof(U32))) 00393 { 00394 // Copy 16-bit data to reach 32-bit alignment 00395 if (rxbuf_cur.u16ptr < rxbuf_end.u16ptr) 00396 { 00397 // 16-bit accesses to FIFO data registers do require pointer post-increment 00398 *rxbuf_cur.u16ptr++ = *ep_fifo.u16ptr++; 00399 } 00400 } 00401 00402 // If pointer to reception buffer is not 64-bit aligned 00403 if (!Test_align((U32)rxbuf_cur.u32ptr, sizeof(U64))) 00404 { 00405 // Copy 32-bit data to reach 64-bit alignment 00406 if (rxbuf_cur.u32ptr < rxbuf_end.u32ptr) 00407 { 00408 // 32-bit accesses to FIFO data registers do not require pointer post-increment 00409 *rxbuf_cur.u32ptr++ = *ep_fifo.u32ptr; 00410 } 00411 } 00412 00413 // Copy 64-bit-aligned data 00414 while (rxbuf_cur.u64ptr < rxbuf_end.u64ptr) 00415 { 00416 // 64-bit accesses to FIFO data registers do not require pointer post-increment 00417 *rxbuf_cur.u64ptr++ = *ep_fifo.u64ptr; 00418 } 00419 00420 // Copy 32-bit-aligned data 00421 if (rxbuf_cur.u32ptr < rxbuf_end.u32ptr) 00422 { 00423 // 32-bit accesses to FIFO data registers do not require pointer post-increment 00424 *rxbuf_cur.u32ptr++ = *ep_fifo.u32ptr; 00425 } 00426 } 00427 00428 // Copy remaining 16-bit data if some 00429 while (rxbuf_cur.u16ptr < rxbuf_end.u16ptr) 00430 { 00431 // 16-bit accesses to FIFO data registers do require pointer post-increment 00432 *rxbuf_cur.u16ptr++ = *ep_fifo.u16ptr++; 00433 } 00434 } 00435 00436 #endif // !__OPTIMIZE_SIZE__ 00437 00438 // Copy remaining 8-bit data if some 00439 while (rxbuf_cur.u8ptr < rxbuf_end.u8ptr) 00440 { 00441 // 8-bit accesses to FIFO data registers do require pointer post-increment 00442 *rxbuf_cur.u8ptr++ = *ep_fifo.u8ptr++; 00443 } 00444 00445 // Save current position in FIFO data register 00446 pep_fifo[ep].u8ptr = (volatile U8 *)ep_fifo.u8ptr; 00447 00448 // Return the updated buffer address and the number of non-copied bytes 00449 if (prxbuf) *prxbuf = rxbuf_cur.u8ptr; 00450 return data_length - (rxbuf_cur.u8ptr - (U8 *)rxbuf); 00451 }
U32 usb_set_ep_txpacket | ( | U8 | ep, | |
U8 | txbyte, | |||
U32 | data_length | |||
) |
usb_set_ep_txpacket
This function fills the selected endpoint FIFO with a constant byte, using as few accesses as possible.
ep | Number of the addressed endpoint | |
txbyte | Byte to fill the endpoint with | |
data_length | Number of bytes to write |
Do not mix calls to this function with calls to indexed macros.
Definition at line 110 of file usb_drv.c.
References pep_fifo, Usb_byte_count, and Usb_get_endpoint_size.
00111 { 00112 // Use aggregated pointers to have several alignments available for a same address 00113 UnionVPtr ep_fifo_cur; 00114 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00115 StructCVPtr ep_fifo_end; 00116 Union64 txval; 00117 #else 00118 UnionCVPtr ep_fifo_end; 00119 union 00120 { 00121 U8 u8[1]; 00122 } txval; 00123 #endif // !__OPTIMIZE_SIZE__ 00124 00125 // Initialize pointers for write loops and limit the number of bytes to write 00126 ep_fifo_cur.u8ptr = pep_fifo[ep].u8ptr; 00127 ep_fifo_end.u8ptr = ep_fifo_cur.u8ptr + 00128 min(data_length, Usb_get_endpoint_size(ep) - Usb_byte_count(ep)); 00129 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00130 ep_fifo_end.u16ptr = (U16 *)Align_down((U32)ep_fifo_end.u8ptr, sizeof(U16)); 00131 ep_fifo_end.u32ptr = (U32 *)Align_down((U32)ep_fifo_end.u16ptr, sizeof(U32)); 00132 ep_fifo_end.u64ptr = (U64 *)Align_down((U32)ep_fifo_end.u32ptr, sizeof(U64)); 00133 #endif // !__OPTIMIZE_SIZE__ 00134 txval.u8[0] = txbyte; 00135 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00136 txval.u8[1] = txval.u8[0]; 00137 txval.u16[1] = txval.u16[0]; 00138 txval.u32[1] = txval.u32[0]; 00139 00140 // If pointer to FIFO data register is not 16-bit aligned 00141 if (!Test_align((U32)ep_fifo_cur.u8ptr, sizeof(U16))) 00142 { 00143 // Write 8-bit data to reach 16-bit alignment 00144 if (ep_fifo_cur.u8ptr < ep_fifo_end.u8ptr) 00145 { 00146 *ep_fifo_cur.u8ptr++ = txval.u8[0]; 00147 } 00148 } 00149 00150 // If pointer to FIFO data register is not 32-bit aligned 00151 if (!Test_align((U32)ep_fifo_cur.u16ptr, sizeof(U32))) 00152 { 00153 // Write 16-bit data to reach 32-bit alignment 00154 if (ep_fifo_cur.u16ptr < ep_fifo_end.u16ptr) 00155 { 00156 *ep_fifo_cur.u16ptr++ = txval.u16[0]; 00157 } 00158 } 00159 00160 // If pointer to FIFO data register is not 64-bit aligned 00161 if (!Test_align((U32)ep_fifo_cur.u32ptr, sizeof(U64))) 00162 { 00163 // Write 32-bit data to reach 64-bit alignment 00164 if (ep_fifo_cur.u32ptr < ep_fifo_end.u32ptr) 00165 { 00166 *ep_fifo_cur.u32ptr++ = txval.u32[0]; 00167 } 00168 } 00169 00170 // Write 64-bit-aligned data 00171 while (ep_fifo_cur.u64ptr < ep_fifo_end.u64ptr) 00172 { 00173 *ep_fifo_cur.u64ptr++ = txval.u64; 00174 } 00175 00176 // Write remaining 32-bit data if some 00177 if (ep_fifo_cur.u32ptr < ep_fifo_end.u32ptr) 00178 { 00179 *ep_fifo_cur.u32ptr++ = txval.u32[0]; 00180 } 00181 00182 // Write remaining 16-bit data if some 00183 if (ep_fifo_cur.u16ptr < ep_fifo_end.u16ptr) 00184 { 00185 *ep_fifo_cur.u16ptr++ = txval.u16[0]; 00186 } 00187 00188 // Write remaining 8-bit data if some 00189 if (ep_fifo_cur.u8ptr < ep_fifo_end.u8ptr) 00190 { 00191 *ep_fifo_cur.u8ptr++ = txval.u8[0]; 00192 } 00193 00194 #else 00195 00196 // Write remaining 8-bit data if some 00197 while (ep_fifo_cur.u8ptr < ep_fifo_end.u8ptr) 00198 { 00199 *ep_fifo_cur.u8ptr++ = txval.u8[0]; 00200 } 00201 00202 #endif // !__OPTIMIZE_SIZE__ 00203 00204 // Compute the number of non-written bytes 00205 data_length -= ep_fifo_cur.u8ptr - pep_fifo[ep].u8ptr; 00206 00207 // Save current position in FIFO data register 00208 pep_fifo[ep].u8ptr = ep_fifo_cur.u8ptr; 00209 00210 // Return the number of non-written bytes 00211 return data_length; 00212 }
U32 usb_write_ep_txpacket | ( | U8 | ep, | |
const void * | txbuf, | |||
U32 | data_length, | |||
const void ** | ptxbuf | |||
) |
usb_write_ep_txpacket
This function writes the buffer pointed to by txbuf to the selected endpoint FIFO, using as few accesses as possible.
ep | Number of the addressed endpoint | |
txbuf | Address of buffer to read | |
data_length | Number of bytes to write | |
ptxbuf | NULL or pointer to the buffer address to update |
Do not mix calls to this function with calls to indexed macros.
Definition at line 234 of file usb_drv.c.
References pep_fifo, Usb_byte_count, and Usb_get_endpoint_size.
Referenced by device_template_task(), usb_get_descriptor(), and usb_set_feature().
00235 { 00236 // Use aggregated pointers to have several alignments available for a same address 00237 UnionVPtr ep_fifo; 00238 UnionCPtr txbuf_cur; 00239 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00240 StructCPtr txbuf_end; 00241 #else 00242 UnionCPtr txbuf_end; 00243 #endif // !__OPTIMIZE_SIZE__ 00244 00245 // Initialize pointers for copy loops and limit the number of bytes to copy 00246 ep_fifo.u8ptr = pep_fifo[ep].u8ptr; 00247 txbuf_cur.u8ptr = txbuf; 00248 txbuf_end.u8ptr = txbuf_cur.u8ptr + 00249 min(data_length, Usb_get_endpoint_size(ep) - Usb_byte_count(ep)); 00250 #if (!defined __OPTIMIZE_SIZE__) || !__OPTIMIZE_SIZE__ // Auto-generated when GCC's -Os command option is used 00251 txbuf_end.u16ptr = (U16 *)Align_down((U32)txbuf_end.u8ptr, sizeof(U16)); 00252 txbuf_end.u32ptr = (U32 *)Align_down((U32)txbuf_end.u16ptr, sizeof(U32)); 00253 txbuf_end.u64ptr = (U64 *)Align_down((U32)txbuf_end.u32ptr, sizeof(U64)); 00254 00255 // If all addresses are aligned the same way with respect to 16-bit boundaries 00256 if (Get_align((U32)txbuf_cur.u8ptr, sizeof(U16)) == Get_align((U32)ep_fifo.u8ptr, sizeof(U16))) 00257 { 00258 // If pointer to transmission buffer is not 16-bit aligned 00259 if (!Test_align((U32)txbuf_cur.u8ptr, sizeof(U16))) 00260 { 00261 // Copy 8-bit data to reach 16-bit alignment 00262 if (txbuf_cur.u8ptr < txbuf_end.u8ptr) 00263 { 00264 // 8-bit accesses to FIFO data registers do require pointer post-increment 00265 *ep_fifo.u8ptr++ = *txbuf_cur.u8ptr++; 00266 } 00267 } 00268 00269 // If all addresses are aligned the same way with respect to 32-bit boundaries 00270 if (Get_align((U32)txbuf_cur.u16ptr, sizeof(U32)) == Get_align((U32)ep_fifo.u16ptr, sizeof(U32))) 00271 { 00272 // If pointer to transmission buffer is not 32-bit aligned 00273 if (!Test_align((U32)txbuf_cur.u16ptr, sizeof(U32))) 00274 { 00275 // Copy 16-bit data to reach 32-bit alignment 00276 if (txbuf_cur.u16ptr < txbuf_end.u16ptr) 00277 { 00278 // 16-bit accesses to FIFO data registers do require pointer post-increment 00279 *ep_fifo.u16ptr++ = *txbuf_cur.u16ptr++; 00280 } 00281 } 00282 00283 // If pointer to transmission buffer is not 64-bit aligned 00284 if (!Test_align((U32)txbuf_cur.u32ptr, sizeof(U64))) 00285 { 00286 // Copy 32-bit data to reach 64-bit alignment 00287 if (txbuf_cur.u32ptr < txbuf_end.u32ptr) 00288 { 00289 // 32-bit accesses to FIFO data registers do not require pointer post-increment 00290 *ep_fifo.u32ptr = *txbuf_cur.u32ptr++; 00291 } 00292 } 00293 00294 // Copy 64-bit-aligned data 00295 while (txbuf_cur.u64ptr < txbuf_end.u64ptr) 00296 { 00297 // 64-bit accesses to FIFO data registers do not require pointer post-increment 00298 *ep_fifo.u64ptr = *txbuf_cur.u64ptr++; 00299 } 00300 00301 // Copy 32-bit-aligned data 00302 if (txbuf_cur.u32ptr < txbuf_end.u32ptr) 00303 { 00304 // 32-bit accesses to FIFO data registers do not require pointer post-increment 00305 *ep_fifo.u32ptr = *txbuf_cur.u32ptr++; 00306 } 00307 } 00308 00309 // Copy remaining 16-bit data if some 00310 while (txbuf_cur.u16ptr < txbuf_end.u16ptr) 00311 { 00312 // 16-bit accesses to FIFO data registers do require pointer post-increment 00313 *ep_fifo.u16ptr++ = *txbuf_cur.u16ptr++; 00314 } 00315 } 00316 00317 #endif // !__OPTIMIZE_SIZE__ 00318 00319 // Copy remaining 8-bit data if some 00320 while (txbuf_cur.u8ptr < txbuf_end.u8ptr) 00321 { 00322 // 8-bit accesses to FIFO data registers do require pointer post-increment 00323 *ep_fifo.u8ptr++ = *txbuf_cur.u8ptr++; 00324 } 00325 00326 // Save current position in FIFO data register 00327 pep_fifo[ep].u8ptr = ep_fifo.u8ptr; 00328 00329 // Return the updated buffer address and the number of non-copied bytes 00330 if (ptxbuf) *ptxbuf = txbuf_cur.u8ptr; 00331 return data_length - (txbuf_cur.u8ptr - (U8 *)txbuf); 00332 }
UnionVPtr pep_fifo[MAX_PEP_NB] |
Pointers to the FIFO data registers of pipes/endpoints Use aggregated pointers to have several alignments available for a same address.
Definition at line 64 of file usb_drv.c.
Referenced by host_read_p_rxpacket(), host_set_p_txpacket(), host_write_p_txpacket(), usb_read_ep_rxpacket(), usb_set_ep_txpacket(), and usb_write_ep_txpacket().