Definition in file pm_uc3l.h.
#include <avr32/io.h>
#include "compiler.h"
Go to the source code of this file.
Sleep Functions | |
#define | pm_sleep(sleep_mode) {__asm__ __volatile__ ("sleep "STRINGZ(sleep_mode));} |
Sets the MCU in the specified sleep mode. | |
#define | SLEEP(sleep_mode) pm_sleep(sleep_mode) |
Sets the MCU in the specified sleep mode. | |
__inline__ void | pm_asyn_wake_up_disable (unsigned long awen_mask) |
Disable one or several asynchronous wake-up sources. | |
__inline__ void | pm_asyn_wake_up_enable (unsigned long awen_mask) |
Enable one or several asynchronous wake-up source. | |
__inline__ unsigned long | pm_get_wake_cause (void) |
Returns MCU wake cause. | |
Defines | |
#define | PM_NOT_SUPPORTED (-10000) |
Define "not supported" for the power manager features. | |
#define | PM_POLL_TIMEOUT 100000 |
The timeguard used for polling (expressed in ticks). | |
#define | PM_UNLOCK(reg) (AVR32_PM.unlock = (unsigned long)(AVR32_PM_UNLOCK_KEY_VALUE << AVR32_PM_UNLOCK_KEY_OFFSET)|(reg)) |
Unlock PM register macro. | |
Enumerations | |
enum | pm_clk_domain_t { PM_CLK_DOMAIN_0 = AVR32_PM_CLK_GRP_CPU, PM_CLK_DOMAIN_1 = AVR32_PM_CLK_GRP_HSB, PM_CLK_DOMAIN_2 = AVR32_PM_CLK_GRP_PBA, PM_CLK_DOMAIN_3 = AVR32_PM_CLK_GRP_PBB, PM_CLK_DOMAIN_4 = AVR32_PM_CLK_GRP_PBC, PM_CLK_DOMAIN_INVALID, PM_CLK_DOMAIN_0 = AVR32_PM_CLK_GRP_CPU, PM_CLK_DOMAIN_1 = AVR32_PM_CLK_GRP_HSB, PM_CLK_DOMAIN_2 = AVR32_PM_CLK_GRP_PBA, PM_CLK_DOMAIN_3 = AVR32_PM_CLK_GRP_PBB, PM_CLK_DOMAIN_INVALID } |
The clock domains of the power manager. More... | |
enum | pm_clk_src_t { PM_CLK_SRC_SLOW = AVR32_PM_MCSEL_SLOW, PM_CLK_SRC_OSC0 = AVR32_PM_MCSEL_OSC0, PM_CLK_SRC_OSC1 = AVR32_PM_MCSEL_OSC1, PM_CLK_SRC_PLL0 = AVR32_PM_MCSEL_PLL0, PM_CLK_SRC_PLL1 = AVR32_PM_MCSEL_PLL1, PM_CLK_SRC_RC8M = AVR32_PM_MCSEL_RCOSC8, PM_CLK_SRC_RCRIPOSC = AVR32_PM_MCSEL_CRIPOSC, PM_CLK_SRC_RC120M = AVR32_PM_MCSEL_RC120M, PM_CLK_SRC_INVALID, PM_CLK_SRC_SLOW = AVR32_PM_MCSEL_SLOW, PM_CLK_SRC_OSC0 = AVR32_PM_MCSEL_OSC0, PM_CLK_SRC_DFLL0 = AVR32_PM_MCSEL_DFLL0, PM_CLK_SRC_RC120M = AVR32_PM_MCSEL_RC120M, PM_CLK_SRC_INVALID } |
Device-specific data. More... | |
enum | pm_divratio_max_t { PM_CPUSEL_DIVRATIO_MAX = AVR32_PM_CPUSEL_CPUSEL_MASK >> AVR32_PM_CPUSEL_CPUSEL_OFFSET, PM_HSBSEL_DIVRATIO_MAX = AVR32_PM_HSBSEL_HSBSEL_MASK >> AVR32_PM_HSBSEL_HSBSEL_OFFSET, PM_PBASEL_DIVRATIO_MAX = AVR32_PM_PBASEL_PBSEL_MASK >> AVR32_PM_PBASEL_PBSEL_OFFSET, PM_PBBSEL_DIVRATIO_MAX = AVR32_PM_PBBSEL_PBSEL_MASK >> AVR32_PM_PBBSEL_PBSEL_OFFSET } |
The maximum synchronous clock division ratio for each clock domain. More... | |
enum | pm_divratio_t { PM_CKSEL_DIVRATIO_2 = 0, PM_CKSEL_DIVRATIO_4, PM_CKSEL_DIVRATIO_8, PM_CKSEL_DIVRATIO_16, PM_CKSEL_DIVRATIO_32, PM_CKSEL_DIVRATIO_64, PM_CKSEL_DIVRATIO_128, PM_CKSEL_DIVRATIO_256, PM_CKSEL_DIVRATIO_2 = 0, PM_CKSEL_DIVRATIO_4, PM_CKSEL_DIVRATIO_8, PM_CKSEL_DIVRATIO_16, PM_CKSEL_DIVRATIO_32, PM_CKSEL_DIVRATIO_64, PM_CKSEL_DIVRATIO_128, PM_CKSEL_DIVRATIO_256, PM_CKSEL_DIVRATIO_ERROR } |
The possible synchronous clock division ratio. More... | |
Functions | |
Interrupt Functions | |
__inline__ void | pm_clear_interrupt_status (unsigned long mask) |
Clear raised interrupts from the power manager. | |
__inline__ void | pm_disable_interrupts (unsigned long mask) |
Disable power manager interrupts. | |
__inline__ void | pm_enable_interrupts (unsigned long mask) |
Enable power manager interrupts. | |
__inline__ unsigned long | pm_get_enabled_interrupts (void) |
Read the enabled power manager interrupts. | |
__inline__ unsigned long | pm_get_interrupts_status (void) |
Read the interrupts status of the power manager. | |
Clock Functions | |
long | pm_config_mainclk_safety (bool cfd, bool ocp, bool final) |
Configure the main clock safety mechanisms. | |
long | pm_disable_clk_domain_div (pm_clk_domain_t clock_domain) |
Disable the division ratio for a clock domain. | |
void | pm_set_all_cksel (unsigned long main_clock_f_hz, unsigned long cpu_f_hz, unsigned long pba_f_hz, unsigned long pbb_f_hz) |
Enable or Disable the division ratio for each clock domain depending on the main source clock frequency and each clock domain target frequency. | |
long | pm_set_clk_domain_div (pm_clk_domain_t clock_domain, pm_divratio_t divratio) |
Set the division ratio for a clock domain. | |
long | pm_set_mclk_source (pm_clk_src_t src) |
Set the main clock. | |
long | pm_wait_for_clk_ready (void) |
Wait actively for the clock settings to be effective. | |
Module Functions | |
long | pm_disable_module (unsigned long module) |
Disable the clock of a module. | |
long | pm_enable_module (unsigned long module) |
Enable the clock of a module. | |
Reset Functions | |
__inline__ unsigned long | pm_get_reset_cause (void) |
Returns MCU last reset cause. | |
Misc Functions | |
__inline__ unsigned long | pm_get_status (void) |
Get the PM status. |
#define PM_NOT_SUPPORTED (-10000) |
#define PM_POLL_TIMEOUT 100000 |
#define pm_sleep | ( | sleep_mode | ) | {__asm__ __volatile__ ("sleep "STRINGZ(sleep_mode));} |
#define PM_UNLOCK | ( | reg | ) | (AVR32_PM.unlock = (unsigned long)(AVR32_PM_UNLOCK_KEY_VALUE << AVR32_PM_UNLOCK_KEY_OFFSET)|(reg)) |
#define SLEEP | ( | sleep_mode | ) | pm_sleep(sleep_mode) |
enum pm_clk_domain_t |
The clock domains of the power manager.
PM_CLK_DOMAIN_0 | |
PM_CLK_DOMAIN_1 | |
PM_CLK_DOMAIN_2 | |
PM_CLK_DOMAIN_3 | |
PM_CLK_DOMAIN_4 | |
PM_CLK_DOMAIN_INVALID | |
PM_CLK_DOMAIN_0 | |
PM_CLK_DOMAIN_1 | |
PM_CLK_DOMAIN_2 | |
PM_CLK_DOMAIN_3 | |
PM_CLK_DOMAIN_INVALID |
Definition at line 69 of file pm_uc3l.h.
00070 { 00071 PM_CLK_DOMAIN_0 = AVR32_PM_CLK_GRP_CPU, 00072 PM_CLK_DOMAIN_1 = AVR32_PM_CLK_GRP_HSB, 00073 PM_CLK_DOMAIN_2 = AVR32_PM_CLK_GRP_PBA, 00074 PM_CLK_DOMAIN_3 = AVR32_PM_CLK_GRP_PBB, 00075 PM_CLK_DOMAIN_INVALID 00076 } pm_clk_domain_t;
enum pm_clk_src_t |
Device-specific data.
The clock sources of the power manager.
Definition at line 59 of file pm_uc3l.h.
00060 { 00061 PM_CLK_SRC_SLOW = AVR32_PM_MCSEL_SLOW, 00062 PM_CLK_SRC_OSC0 = AVR32_PM_MCSEL_OSC0, 00063 PM_CLK_SRC_DFLL0 = AVR32_PM_MCSEL_DFLL0, 00064 PM_CLK_SRC_RC120M = AVR32_PM_MCSEL_RC120M, 00065 PM_CLK_SRC_INVALID 00066 } pm_clk_src_t;
enum pm_divratio_max_t |
The maximum synchronous clock division ratio for each clock domain.
PM_CPUSEL_DIVRATIO_MAX | |
PM_HSBSEL_DIVRATIO_MAX | |
PM_PBASEL_DIVRATIO_MAX | |
PM_PBBSEL_DIVRATIO_MAX |
Definition at line 94 of file pm_uc3l.h.
00095 { 00096 PM_CPUSEL_DIVRATIO_MAX = AVR32_PM_CPUSEL_CPUSEL_MASK >> AVR32_PM_CPUSEL_CPUSEL_OFFSET, 00097 PM_HSBSEL_DIVRATIO_MAX = AVR32_PM_HSBSEL_HSBSEL_MASK >> AVR32_PM_HSBSEL_HSBSEL_OFFSET, 00098 PM_PBASEL_DIVRATIO_MAX = AVR32_PM_PBASEL_PBSEL_MASK >> AVR32_PM_PBASEL_PBSEL_OFFSET, 00099 PM_PBBSEL_DIVRATIO_MAX = AVR32_PM_PBBSEL_PBSEL_MASK >> AVR32_PM_PBBSEL_PBSEL_OFFSET 00100 } pm_divratio_max_t;
enum pm_divratio_t |
The possible synchronous clock division ratio.
Definition at line 80 of file pm_uc3l.h.
00081 { 00082 PM_CKSEL_DIVRATIO_2 = 0, // Divide the main clock by 2^1 00083 PM_CKSEL_DIVRATIO_4, // Divide the main clock by 2^2 00084 PM_CKSEL_DIVRATIO_8, // Divide the main clock by 2^3 00085 PM_CKSEL_DIVRATIO_16, // Divide the main clock by 2^4 00086 PM_CKSEL_DIVRATIO_32, // Divide the main clock by 2^5 00087 PM_CKSEL_DIVRATIO_64, // Divide the main clock by 2^6 00088 PM_CKSEL_DIVRATIO_128, // Divide the main clock by 2^7 00089 PM_CKSEL_DIVRATIO_256, // Divide the main clock by 2^8 00090 PM_CKSEL_DIVRATIO_ERROR 00091 } pm_divratio_t;
__inline__ void pm_asyn_wake_up_disable | ( | unsigned long | awen_mask | ) |
__inline__ void pm_asyn_wake_up_enable | ( | unsigned long | awen_mask | ) |
__inline__ void pm_clear_interrupt_status | ( | unsigned long | mask | ) |
long pm_config_mainclk_safety | ( | bool | cfd, | |
bool | ocp, | |||
bool | final | |||
) |
Configure the main clock safety mechanisms.
cfd | Enable/disable the Clock Failure Detection mechanism | |
ocp | Enable/disable the Over Clock Protection mechanism | |
final | If true, make this configuration definitive |
=0 | Success. | |
<0 | An error occured. |
Definition at line 107 of file pm_uc3l.c.
References u_avr32_pm_cfdctrl_t::cfdctrl, u_avr32_pm_cfdctrl_t::CFDCTRL, and PM_UNLOCK.
00108 { 00109 u_avr32_pm_cfdctrl_t u_avr32_pm_cfdctrl = {AVR32_PM.cfdctrl}; 00110 00111 // Check if the CFDCTRL register is read-only. 00112 if(AVR32_PM.cfdctrl & AVR32_PM_CFDCTRL_SFV_MASK) 00113 return -1; 00114 00115 // Modify 00116 u_avr32_pm_cfdctrl.CFDCTRL.cfden = cfd; 00117 u_avr32_pm_cfdctrl.CFDCTRL.ocpen = ocp; 00118 u_avr32_pm_cfdctrl.CFDCTRL.sfv = final; 00119 AVR32_ENTER_CRITICAL_REGION( ); 00120 // Unlock the write-protected CFDCTRL register 00121 PM_UNLOCK(AVR32_PM_CFDCTRL); 00122 // Write back 00123 AVR32_PM.cfdctrl = u_avr32_pm_cfdctrl.cfdctrl; 00124 AVR32_LEAVE_CRITICAL_REGION( ); 00125 00126 return PASS; 00127 }
long pm_disable_clk_domain_div | ( | pm_clk_domain_t | clock_domain | ) |
Disable the division ratio for a clock domain.
clock_domain | The clock domain to alter. |
=0 | Success. | |
<0 | An error occured. |
Definition at line 162 of file pm_uc3c.c.
References u_avr32_pm_cpusel_t::cpusel, u_avr32_pm_cpusel_t::CPUSEL, and PM_UNLOCK.
Referenced by pm_set_all_cksel().
00163 { 00164 u_avr32_pm_cpusel_t u_avr32_pm_cpusel = {AVR32_PM.cpusel}; 00165 00166 //# Implementation note: the CPUSEL and PBASEL and PBBSEL and PBCSEL registers all have the 00167 //# same structure. 00168 00169 //# Implementation note: the ckSEL registers are contiguous and memory-mapped in 00170 //# that order: CPUSEL, HSBSEL, PBASEL, PBBSEL, PBCSEL. 00171 00172 // ckSEL must not be written while SR.CKRDY is 0. 00173 if(!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK)) 00174 return -1; 00175 00176 // Modify 00177 u_avr32_pm_cpusel.CPUSEL.cpudiv= DISABLE; 00178 AVR32_ENTER_CRITICAL_REGION( ); 00179 // Unlock the write-protected ckSEL register 00180 PM_UNLOCK(AVR32_PM_CPUSEL + clock_domain*sizeof(avr32_pm_cpusel_t)); 00181 // Update 00182 *(&(AVR32_PM.cpusel) + clock_domain)= u_avr32_pm_cpusel.cpusel; 00183 AVR32_LEAVE_CRITICAL_REGION( ); 00184 00185 return PASS; 00186 }
__inline__ void pm_disable_interrupts | ( | unsigned long | mask | ) |
long pm_disable_module | ( | unsigned long | module | ) |
Disable the clock of a module.
module | The module to shut down (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks") |
0 | Success. | |
<0 | An error occured. |
Definition at line 228 of file pm_uc3c.c.
References PM_UNLOCK.
00229 { 00230 unsigned long domain = module>>5; 00231 //# Implementation note: the ckMASK registers are contiguous and memory-mapped 00232 //# in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK. 00233 volatile unsigned long *regptr = (volatile unsigned long*)(&(AVR32_PM.cpumask) + domain); 00234 unsigned long regvalue; 00235 00236 00237 // Read 00238 regvalue = *regptr; 00239 // Modify 00240 regvalue &= ~(1<<(module%32)); 00241 AVR32_ENTER_CRITICAL_REGION( ); 00242 // Unlock the write-protected ckMASK register 00243 PM_UNLOCK(AVR32_PM_CPUMASK + domain*sizeof(avr32_pm_cpumask_t)); 00244 // Write 00245 *regptr = regvalue; 00246 AVR32_LEAVE_CRITICAL_REGION( ); 00247 00248 return PASS; 00249 }
__inline__ void pm_enable_interrupts | ( | unsigned long | mask | ) |
long pm_enable_module | ( | unsigned long | module | ) |
Enable the clock of a module.
module | The module to clock (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks") |
0 | Success. | |
<0 | An error occured. |
Definition at line 205 of file pm_uc3c.c.
References PM_UNLOCK.
00206 { 00207 unsigned long domain = module>>5; 00208 //# Implementation note: the ckMASK registers are contiguous and memory-mapped 00209 //# in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK. 00210 unsigned long *regptr = (unsigned long*)(&(AVR32_PM.cpumask) + domain); 00211 unsigned long regvalue; 00212 00213 00214 // Read 00215 regvalue = *regptr; 00216 // Modify 00217 regvalue |= (1<<(module%32)); 00218 AVR32_ENTER_CRITICAL_REGION( ); 00219 // Unlock the write-protected ckMASK register 00220 PM_UNLOCK(AVR32_PM_CPUMASK + domain*sizeof(avr32_pm_cpumask_t)); 00221 // Write 00222 *regptr = regvalue; 00223 AVR32_LEAVE_CRITICAL_REGION( ); 00224 00225 return PASS; 00226 }
__inline__ unsigned long pm_get_enabled_interrupts | ( | void | ) |
__inline__ unsigned long pm_get_interrupts_status | ( | void | ) |
__inline__ unsigned long pm_get_reset_cause | ( | void | ) |
__inline__ unsigned long pm_get_status | ( | void | ) |
__inline__ unsigned long pm_get_wake_cause | ( | void | ) |
void pm_set_all_cksel | ( | unsigned long | main_clock_f_hz, | |
unsigned long | cpu_f_hz, | |||
unsigned long | pba_f_hz, | |||
unsigned long | pbb_f_hz | |||
) |
Enable or Disable the division ratio for each clock domain depending on the main source clock frequency and each clock domain target frequency.
main_clock_f_hz | The main source clock frequency | |
cpu_f_hz | The target CPU clock domain frequency | |
pba_f_hz | The target PBA clock domain frequency | |
pbb_f_hz | The target PBB clock domain frequency |
Definition at line 186 of file pm_uc3l.c.
References PM_CKSEL_DIVRATIO_ERROR, pm_disable_clk_domain_div(), pm_find_divratio(), and pm_set_clk_domain_div().
00188 { 00189 pm_divratio_t div_ratio; 00190 00191 00192 // Find the divratio to apply to reach the target cpu_f frequency. 00193 div_ratio = pm_find_divratio(main_clock_f_hz, cpu_f_hz); 00194 // Apply the division ratio for the CPU clock domain. 00195 if(PM_CKSEL_DIVRATIO_ERROR == div_ratio) 00196 pm_disable_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU); 00197 else 00198 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, div_ratio); 00199 00200 // Find the divratio to apply to reach the target pba_f frequency. 00201 div_ratio = pm_find_divratio(main_clock_f_hz, pba_f_hz); 00202 // Apply the division ratio for the PBA clock domain. 00203 if(PM_CKSEL_DIVRATIO_ERROR == div_ratio) 00204 pm_disable_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA); 00205 else 00206 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, div_ratio); 00207 00208 // Find the divratio to apply to reach the target pbb_f frequency. 00209 div_ratio = pm_find_divratio(main_clock_f_hz, pbb_f_hz); 00210 // Apply the division ratio for the PBB clock domain. 00211 if(PM_CKSEL_DIVRATIO_ERROR == div_ratio) 00212 pm_disable_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB); 00213 else 00214 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, div_ratio); 00215 }
long pm_set_clk_domain_div | ( | pm_clk_domain_t | clock_domain, | |
pm_divratio_t | divratio | |||
) |
Set the division ratio for a clock domain.
clock_domain | The clock domain to alter. | |
divratio | The division ratio to set. |
=0 | Success. | |
<0 | An error occured. |
Definition at line 129 of file pm_uc3c.c.
References u_avr32_pm_cpusel_t::cpusel, u_avr32_pm_cpusel_t::CPUSEL, PM_CPUSEL_DIVRATIO_MAX, and PM_UNLOCK.
Referenced by pm_set_all_cksel().
00130 { 00131 u_avr32_pm_cpusel_t u_avr32_pm_cpusel = {AVR32_PM.cpusel}; 00132 00133 //# Implementation note: the CPUSEL and PBASEL and PBBSEL registers all have the 00134 //# same structure. 00135 00136 //# Implementation note: the ckSEL registers are contiguous and memory-mapped in 00137 //# that order: CPUSEL, HSBSEL, PBASEL, PBBSEL. 00138 00139 #ifdef AVR32SFW_INPUT_CHECK 00140 // Check the divratio 00141 if((divratio > PM_CPUSEL_DIVRATIO_MAX)||(divratio < 0)) 00142 return -1; 00143 #endif 00144 00145 // ckSEL must not be written while SR.CKRDY is 0. 00146 if(!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK)) 00147 return -1; 00148 00149 // Modify 00150 u_avr32_pm_cpusel.CPUSEL.cpudiv= 1; 00151 u_avr32_pm_cpusel.CPUSEL.cpusel = divratio; 00152 AVR32_ENTER_CRITICAL_REGION( ); 00153 // Unlock the write-protected ckSEL register 00154 PM_UNLOCK(AVR32_PM_CPUSEL + clock_domain*sizeof(avr32_pm_cpusel_t)); 00155 // Update 00156 *(&(AVR32_PM.cpusel) + clock_domain)= u_avr32_pm_cpusel.cpusel; 00157 AVR32_LEAVE_CRITICAL_REGION( ); 00158 00159 return PASS; 00160 }
long pm_set_mclk_source | ( | pm_clk_src_t | src | ) |
Set the main clock.
src | The clock to use as the main clock. |
0 | Success. | |
<0 | An error occured when trying to set the main clock. |
Definition at line 97 of file pm_uc3c.c.
References PM_UNLOCK.
Referenced by local_switch_to_osc0(), and pcl_switch_to_osc().
00098 { 00099 // Unlock the write-protected MCCTRL register 00100 AVR32_ENTER_CRITICAL_REGION( ); 00101 PM_UNLOCK(AVR32_PM_MCCTRL); 00102 AVR32_PM.mcctrl = src; 00103 AVR32_LEAVE_CRITICAL_REGION( ); 00104 00105 return PASS; 00106 }
long pm_wait_for_clk_ready | ( | void | ) |
Wait actively for the clock settings to be effective.
0 | Success. | |
<0 | Unable to reach a clock ready status within the polling limit. |
Definition at line 188 of file pm_uc3c.c.
References PM_POLL_TIMEOUT.
00189 { 00190 unsigned int timeout = PM_POLL_TIMEOUT; 00191 while (!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK)) 00192 { 00193 if(--timeout == 0) 00194 return -1; 00195 } 00196 return PASS; 00197 }