EMB Project Status (05/09/2010 - 14:15:34)
Project File: EMB.ise Implementation State: Synthesized
Module Name: memory_controller
  • Errors:
 
Target Device: xc3s500e-5pq208
  • Warnings:
 
Product Version:ISE 11.1
  • Routing Results:
 
Design Goal: Balanced
  • Timing Constraints:
 
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 55 4656 1%
Number of Slice Flip Flops 11 9312 0%
Number of 4 input LUTs 91 9312 0%
Number of bonded IOBs 144 232 62%
Number of GCLKs 1 24 4%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSun May 9 13:33:12 2010   
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 05/09/2010 - 14:15:34