scif_dfll_closedloop_conf_t | DFLL closed-loop mode settings |
scif_dfll_openloop_conf_t | DFLL open-loop mode settings |
scif_dfll_ssg_conf_t | DFLL SSG settings |
scif_gclk_opt_t | Generic clock generation settings |
scif_osc32_opt_t | OSC32 startup options |
scif_osc_opt_t | OSC0/OSC1 startup options |
scif_pll_opt_t | PLL0/PLL1 startup options |
u_avr32_scif_dfll0conf_t | |
u_avr32_scif_dfll0ssg_t | |
u_avr32_scif_oscctrl0_t | |
u_avr32_scif_oscctrl32_t | |
u_avr32_scif_oscctrl_t | |
u_avr32_scif_pll_t |