pm_example1.c File Reference


Detailed Description

Osc0 as Main clock source and Generic clock configuration and sleep mode example.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file pm_example1.c.

#include "board.h"
#include "gpio.h"
#include "pm.h"

Go to the source code of this file.

Defines

Generic Clock Configuration
#define EXAMPLE_GCLK_FUNCTION   AVR32_SCIF_GCLK_1_0_FUNCTION
#define EXAMPLE_GCLK_ID   AVR32_SCIF_GCLK_DFLL0_SSG
#define EXAMPLE_GCLK_PIN   AVR32_SCIF_GCLK_1_0_PIN

Functions

static void local_enable_gclk_on_gpio (volatile avr32_pm_t *pm)
static void local_switch_to_osc0 (volatile avr32_pm_t *pm)
int main (void)


Define Documentation

#define EXAMPLE_GCLK_FUNCTION   AVR32_SCIF_GCLK_1_0_FUNCTION

Definition at line 136 of file pm_example1.c.

Referenced by local_enable_gclk_on_gpio().

#define EXAMPLE_GCLK_ID   AVR32_SCIF_GCLK_DFLL0_SSG

Definition at line 134 of file pm_example1.c.

Referenced by local_enable_gclk_on_gpio().

#define EXAMPLE_GCLK_PIN   AVR32_SCIF_GCLK_1_0_PIN

Definition at line 135 of file pm_example1.c.

Referenced by local_enable_gclk_on_gpio().


Function Documentation

static void local_enable_gclk_on_gpio ( volatile avr32_pm_t *  pm  )  [static]

Definition at line 181 of file pm_example1.c.

References EXAMPLE_GCLK_FUNCTION, EXAMPLE_GCLK_ID, EXAMPLE_GCLK_PIN, pm_gc_enable(), and pm_gc_setup().

Referenced by main().

00182 {
00183   int gc = EXAMPLE_GCLK_ID;
00184 
00185 #if ( BOARD == STK600_RCUC3L0 ) || ( BOARD == UC3C_EK )
00186   // Note: for UC3L and UC3C devices, the generic clock configurations are handled by the
00187   // SCIF module.
00188   /* setup gc on Osc0, no divisor */
00189   scif_gc_setup(gc, SCIF_GCCTRL_OSC0, AVR32_SCIF_GC_NO_DIV_CLOCK, 0);
00190   
00191   /* Now enable the generic clock */
00192   scif_gc_enable(gc);
00193 #else
00194   /* setup gc on Osc0, no divisor */
00195   pm_gc_setup(pm, gc, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC0, AVR32_GC_NO_DIV_CLOCK, 0);
00196 
00197   /* Now enable the generic clock */
00198   pm_gc_enable(pm,gc);
00199 #endif
00200 
00201   /* Assign a GPIO to generic clock output */
00202   gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION);
00203   // Note that gclk0_1 is GPIO pin 51 pb19 on AT32UC3A0512 QFP144.
00204   // Note that gclk2 is GPIO pin 30 pa30 on AT32UC3B0256 QFP64.
00205   // Note that gclk1 is GPIO pin 43 pb11 on AT32UC3A3256 QFP144.
00206   // Note that gclk1 is GPIO pin 6 pa06 on AT32UC3L064 pin 10 on QFP48.
00207   // Note that gclk0 is GPIO pin 54 pb22 on AT32UC3C0512C QFP144.
00208 }

static void local_switch_to_osc0 ( volatile avr32_pm_t *  pm  )  [static]

Definition at line 152 of file pm_example1.c.

References PM_CLK_SRC_OSC0, pm_enable_clk0(), pm_enable_osc0_crystal(), pm_set_mclk_source(), and pm_switch_to_clock().

Referenced by main().

00153 {
00154 #if ( BOARD == STK600_RCUC3L0 ) || ( BOARD == UC3C_EK )
00155   // Note: for UC3L and UC3C devices, the osc configurations are handled by the SCIF module
00156   // and the synchronous clocks used to clock the main digital logic are handled
00157   // by the PM module.
00158   // 1) Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
00159   scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
00160   // 2) Enable the OSC0
00161   scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
00162   // 3) Set the main clock source as being OSC0.
00163   pm_set_mclk_source(PM_CLK_SRC_OSC0);
00164 #else
00165   // 1) Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
00166   pm_enable_osc0_crystal(pm, FOSC0);  // with Osc
00167   // 2) Enable the OSC0
00168   pm_enable_clk0(pm, OSC0_STARTUP);
00169   // 3) Set the main clock source as being OSC0.
00170   pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0);
00171 #endif
00172   // From now on, the CPU frequency is FOSC0 Hz.
00173 }

int main ( void   ) 

Definition at line 220 of file pm_example1.c.

References local_enable_gclk_on_gpio(), local_switch_to_osc0(), and SLEEP.

00221 {
00222   volatile avr32_pm_t* pm = &AVR32_PM;
00223   
00224   
00225   // By default, the main clock source is the slow clock. Switch the main clock
00226   // source to be OSC0:
00227   // - Configure OSC0
00228   // - Set the main clock to use OSC0 as input
00229   local_switch_to_osc0(pm);
00230   // From now on, the CPU frequency is FOSC0 Hz.
00231   
00232   // - Configure a generic clock GCLK to use OSC0 as input
00233   // - Output that generic clock to a pin
00234   local_enable_gclk_on_gpio(pm);
00235 
00236   //*** Sleep mode
00237   // If there is a chance that any PB write operations are incomplete, the CPU
00238   // should perform a read operation from any register on the PB bus before
00239   // executing the sleep instruction.
00240   AVR32_INTC.ipr[0];  // Dummy read
00241 
00242   // - Go into a sleep mode (while still maintaining GCLK output)
00243   SLEEP(AVR32_PM_SMODE_FROZEN);
00244 
00245   while(1);
00246 }


Generated on Fri Feb 19 02:25:45 2010 for AVR32 UC3 - Power Manager Driver Example 1 by  doxygen 1.5.5