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00047 #include "compiler.h"
00048 #include "scif_uc3l.h"
00049
00050
00053
00054
00055 typedef union
00056 {
00057 unsigned long oscctrl0;
00058 avr32_scif_oscctrl0_t OSCCTRL0;
00059 } u_avr32_scif_oscctrl0_t;
00060
00061 typedef union
00062 {
00063 unsigned long oscctrl32;
00064 avr32_scif_oscctrl32_t OSCCTRL32;
00065 } u_avr32_scif_oscctrl32_t;
00066
00067 typedef union
00068 {
00069 unsigned long dfll0conf;
00070 avr32_scif_dfll0conf_t DFLL0CONF;
00071 } u_avr32_scif_dfll0conf_t;
00072
00073 typedef union
00074 {
00075 unsigned long dfll0ssg;
00076 avr32_scif_dfll0ssg_t DFLL0SSG;
00077 } u_avr32_scif_dfll0ssg_t;
00078
00080
00081
00085
00086
00087
00091
00092
00093
00098 long int scif_start_osc(scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready)
00099 {
00100
00101
00102 u_avr32_scif_oscctrl0_t u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0};
00103
00104
00105 #ifdef AVR32SFW_INPUT_CHECK
00106
00107 if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ)
00108 || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ))
00109 {
00110 return -1;
00111 }
00112
00113 if( (opt->mode != SCIF_OSC_MODE_EXT_CLK)
00114 && (opt->mode != SCIF_OSC_MODE_2PIN_CRYSTAL))
00115 {
00116 return -1;
00117 }
00118
00119 if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC)
00120 {
00121 return -1;
00122 }
00123
00124 if(opt->gain > AVR32_SCIF_OSCCTRL0_GAIN_G3)
00125 {
00126 return -1;
00127 }
00128 #endif // AVR32SFW_INPUT_CHECK
00129
00130
00131 u_avr32_scif_oscctrl0.OSCCTRL0.mode = opt->mode;
00132 u_avr32_scif_oscctrl0.OSCCTRL0.gain = opt->gain;
00133 u_avr32_scif_oscctrl0.OSCCTRL0.startup = opt->startup;
00134 u_avr32_scif_oscctrl0.OSCCTRL0.oscen = ENABLE;
00135 AVR32_ENTER_CRITICAL_REGION( );
00136
00137 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
00138
00139 AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0;
00140 AVR32_LEAVE_CRITICAL_REGION( );
00141
00142 if(true == wait_for_ready)
00143 {
00144
00145 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK))
00146 return -1;
00147 }
00148
00149 return PASS;
00150 }
00151
00152
00153 bool scif_is_osc_ready(scif_osc_t osc)
00154 {
00155
00156
00157 return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC0RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC0RDY_OFFSET);
00158 }
00159
00160
00161 long int scif_stop_osc(scif_osc_t osc)
00162 {
00163
00164
00165 unsigned long temp = AVR32_SCIF.oscctrl0;
00166 temp &= ~AVR32_SCIF_OSCCTRL0_OSCEN_MASK;
00167
00168 AVR32_ENTER_CRITICAL_REGION( );
00169
00170 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
00171
00172 AVR32_SCIF.oscctrl0 = temp;
00173 AVR32_LEAVE_CRITICAL_REGION( );
00174
00175 return PASS;
00176 }
00177
00178
00179 long int scif_configure_osc_crystalmode(scif_osc_t osc, unsigned int fcrystal)
00180 {
00181
00182
00183 u_avr32_scif_oscctrl0_t u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0};
00184
00185
00186
00187 u_avr32_scif_oscctrl0.OSCCTRL0.mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
00188 u_avr32_scif_oscctrl0.OSCCTRL0.gain = (fcrystal < 900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
00189 (fcrystal < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
00190 (fcrystal < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
00191 AVR32_SCIF_OSCCTRL0_GAIN_G3;
00192 AVR32_ENTER_CRITICAL_REGION( );
00193
00194 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
00195
00196 AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0;
00197 AVR32_LEAVE_CRITICAL_REGION( );
00198
00199
00200 return PASS;
00201 }
00202
00203
00204 long int scif_enable_osc(scif_osc_t osc, unsigned int startup, bool wait_for_ready)
00205 {
00206
00207
00208 u_avr32_scif_oscctrl0_t u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0};
00209
00210
00211
00212 u_avr32_scif_oscctrl0.OSCCTRL0.startup = startup;
00213 u_avr32_scif_oscctrl0.OSCCTRL0.oscen = ENABLE;
00214 AVR32_ENTER_CRITICAL_REGION( );
00215
00216 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
00217
00218 AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0;
00219 AVR32_LEAVE_CRITICAL_REGION( );
00220
00221 if(true == wait_for_ready)
00222 {
00223
00224 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK))
00225 return -1;
00226 }
00227
00228 return PASS;
00229 }
00230
00231
00236 long int scif_start_osc32(const scif_osc32_opt_t *opt, bool wait_for_ready)
00237 {
00238 u_avr32_scif_oscctrl32_t u_avr32_scif_oscctrl32 = {AVR32_SCIF.oscctrl32};
00239
00240
00241 #ifdef AVR32SFW_INPUT_CHECK
00242
00243 if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ)
00244 || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ))
00245 {
00246 return -1;
00247 }
00248
00249 if( (opt->mode != SCIF_OSC_MODE_EXT_CLK)
00250 && (opt->mode != SCIF_OSC_MODE_2PIN_CRYSTAL)
00251 && (opt->mode != SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR)
00252 )
00253 {
00254 return -1;
00255 }
00256
00257 if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL32_STARTUP_524288_RCOSC)
00258 {
00259 return -1;
00260 }
00261 #endif // AVR32SFW_INPUT_CHECK
00262
00263 #if (defined(__GNUC__) \
00264 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00265 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00266 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00267
00268
00269
00270 scif_disable_rc32out();
00271 #endif
00272
00273
00274 u_avr32_scif_oscctrl32.OSCCTRL32.mode = opt->mode;
00275 u_avr32_scif_oscctrl32.OSCCTRL32.pinsel = opt->pinsel;
00276 u_avr32_scif_oscctrl32.OSCCTRL32.en32k = opt->en32k;
00277 u_avr32_scif_oscctrl32.OSCCTRL32.en1k = opt->en1k;
00278 u_avr32_scif_oscctrl32.OSCCTRL32.startup = opt->startup;
00279 u_avr32_scif_oscctrl32.OSCCTRL32.osc32en = ENABLE;
00280 #if (defined(__GNUC__) \
00281 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00282 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00283 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00284
00285 AVR32_ENTER_CRITICAL_REGION( );
00286
00287 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32);
00288 #endif
00289
00290 AVR32_SCIF.oscctrl32 = u_avr32_scif_oscctrl32.oscctrl32;
00291 #if (defined(__GNUC__) \
00292 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00293 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00294 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00295
00296 AVR32_LEAVE_CRITICAL_REGION( );
00297 #endif
00298
00299 if(true == wait_for_ready)
00300 {
00301
00302 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC32RDY_MASK))
00303 return -1;
00304 }
00305
00306 return PASS;
00307 }
00308
00309
00310 long scif_stop_osc32()
00311 {
00312 unsigned long temp = AVR32_SCIF.oscctrl32;
00313 temp &= ~AVR32_SCIF_OSCCTRL32_OSC32EN_MASK;
00314
00315 #if (defined(__GNUC__) \
00316 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00317 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00318 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00319
00320
00321 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32);
00322 #endif
00323
00324 AVR32_SCIF.oscctrl32 = temp;
00325
00326 return PASS;
00327 }
00328
00329
00330
00335
00336 typedef enum
00337 {
00338 SCIF_DFLL0_MODE_OPENLOOP = 0,
00339 SCIF_DFLL0_MODE_CLOSEDLOOP
00340 } scif_dfll_mode_t;
00341
00342 long int scif_dfll0_openloop_start(const scif_dfll_openloop_conf_t *pdfllconfig)
00343 {
00344 u_avr32_scif_dfll0conf_t u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00345
00346
00347 #ifdef AVR32SFW_INPUT_CHECK
00348 if((pdfllconfig->fine >> AVR32_SCIF_DFLL0CONF_FINE_SIZE))
00349 return -1;
00350 if((pdfllconfig->coarse >> AVR32_SCIF_DFLL0CONF_COARSE_SIZE))
00351 return -1;
00352 #endif
00353
00354
00355 u_avr32_scif_dfll0conf.DFLL0CONF.en = ENABLE;
00356 AVR32_ENTER_CRITICAL_REGION( );
00357 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00358 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00359 AVR32_LEAVE_CRITICAL_REGION( );
00360
00361
00362 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00363 return -1;
00364
00365
00366 u_avr32_scif_dfll0conf.DFLL0CONF.mode = SCIF_DFLL0_MODE_OPENLOOP;
00367 AVR32_ENTER_CRITICAL_REGION( );
00368 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00369 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00370 AVR32_LEAVE_CRITICAL_REGION( );
00371
00372
00373 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00374 return -1;
00375
00376
00377 u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse;
00378 u_avr32_scif_dfll0conf.DFLL0CONF.fine = pdfllconfig->fine;
00379 AVR32_ENTER_CRITICAL_REGION( );
00380 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00381 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00382 AVR32_LEAVE_CRITICAL_REGION( );
00383
00384
00385 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00386 return -1;
00387
00388 return PASS;
00389 }
00390
00391
00392 #define SCIF_DFLL_COARSE_MAX (AVR32_SCIF_COARSE_MASK >> AVR32_SCIF_COARSE_OFFSET)
00393 #define SCIF_DFLL_FINE_MAX (AVR32_SCIF_FINE_MASK >> AVR32_SCIF_FINE_OFFSET)
00394 #define SCIF_DFLL_FINE_HALF (1 << (AVR32_SCIF_DFLL0CONF_FINE_SIZE-1))
00395 long int scif_dfll0_openloop_start_auto(unsigned long TargetFreqkHz)
00396 {
00397 scif_dfll_openloop_conf_t Dfll0Conf;
00398 unsigned long Coarse;
00399 unsigned long Fine;
00400 unsigned long CoarseFreq;
00401 unsigned long DeltaFreq;
00402
00403
00404 #ifdef AVR32SFW_INPUT_CHECK
00405 if((TargetFreqkHz < SCIF_DFLL_MINFREQ_KHZ) || (TargetFreqkHz > SCIF_DFLL_MAXFREQ_KHZ))
00406 return -1;
00407 #endif
00408
00409
00410
00411
00412
00413
00414
00415 Coarse = ((TargetFreqkHz - SCIF_DFLL_MINFREQ_KHZ)*SCIF_DFLL_COARSE_MAX)/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ);
00416
00417 CoarseFreq = SCIF_DFLL_MINFREQ_KHZ + (((SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ)/SCIF_DFLL_COARSE_MAX)*Coarse);
00418
00419 DeltaFreq = TargetFreqkHz - CoarseFreq;
00420
00421
00422
00423
00424 Fine = ((DeltaFreq*SCIF_DFLL_FINE_MAX)*2/CoarseFreq*5) + SCIF_DFLL_FINE_HALF;
00425 Fine >>=2;
00426
00427 Dfll0Conf.coarse = Coarse;
00428 Dfll0Conf.fine = Fine;
00429 return(scif_dfll0_openloop_start(&Dfll0Conf));
00430 }
00431
00432 long int scif_dfll0_openloop_updatefreq(const scif_dfll_openloop_conf_t *pdfllconfig)
00433 {
00434 u_avr32_scif_dfll0conf_t u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00435
00436
00437 #ifdef AVR32SFW_INPUT_CHECK
00438 if((pdfllconfig->fine >> AVR32_SCIF_DFLL0CONF_FINE_SIZE))
00439 return -1;
00440 #endif
00441
00442
00443
00444
00445 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00446 return -1;
00447
00448
00449 u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse;
00450 u_avr32_scif_dfll0conf.DFLL0CONF.fine = pdfllconfig->fine;
00451 AVR32_ENTER_CRITICAL_REGION( );
00452 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00453 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00454 AVR32_LEAVE_CRITICAL_REGION( );
00455
00456
00457 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00458 return -1;
00459
00460 return PASS;
00461 }
00462
00463
00464 long int scif_dfll0_openloop_stop(void)
00465 {
00466 u_avr32_scif_dfll0conf_t u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00467
00468
00469
00470
00471
00472
00473 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00474 return -1;
00475
00476
00477 u_avr32_scif_dfll0conf.DFLL0CONF.coarse = 0;
00478 AVR32_ENTER_CRITICAL_REGION( );
00479 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00480 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00481 AVR32_LEAVE_CRITICAL_REGION( );
00482
00483
00484 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00485 return -1;
00486
00487
00488 u_avr32_scif_dfll0conf.DFLL0CONF.en = 0;
00489 AVR32_ENTER_CRITICAL_REGION( );
00490 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00491 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00492 AVR32_LEAVE_CRITICAL_REGION( );
00493
00494
00495 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00496 return -1;
00497
00498 return PASS;
00499 }
00500
00501
00502 long int scif_dfll0_ssg_enable(scif_dfll_ssg_conf_t *pssg_conf)
00503 {
00504 u_avr32_scif_dfll0ssg_t u_avr32_scif_dfll0ssg = {AVR32_SCIF.dfll0ssg};
00505
00506
00507 u_avr32_scif_dfll0ssg.DFLL0SSG.en = ENABLE;
00508 u_avr32_scif_dfll0ssg.DFLL0SSG.prbs = pssg_conf->use_random;
00509 u_avr32_scif_dfll0ssg.DFLL0SSG.amplitude = pssg_conf->amplitude;
00510 u_avr32_scif_dfll0ssg.DFLL0SSG.stepsize = pssg_conf->step_size;
00511 AVR32_ENTER_CRITICAL_REGION( );
00512 SCIF_UNLOCK(AVR32_SCIF_DFLL0SSG);
00513 AVR32_SCIF.dfll0ssg = u_avr32_scif_dfll0ssg.dfll0ssg;
00514 AVR32_LEAVE_CRITICAL_REGION( );
00515
00516 return PASS;
00517 }
00518
00519
00520 long int scif_dfll0_closedloop_start(const scif_dfll_closedloop_conf_t *pdfllconfig)
00521 {
00522 u_avr32_scif_dfll0conf_t u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00523 #if (defined(__GNUC__) \
00524 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00525 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00526 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00527 volatile unsigned long tempo;
00528 #endif
00529
00530
00531 #ifdef AVR32SFW_INPUT_CHECK
00532 if((pdfllconfig->coarse >> AVR32_SCIF_DFLL0CONF_COARSE_SIZE))
00533 return -1;
00534 #if (defined(__GNUC__) \
00535 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00536 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00537 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00538
00539 if( (pdfllconfig->finemaxstep >> AVR32_SCIF_DFLL0STEP_FSTEP_SIZE)
00540 || (pdfllconfig->coarsemaxstep >> AVR32_SCIF_DFLL0STEP_CSTEP_SIZE) )
00541 return -1;
00542 #else
00543
00544 if((pdfllconfig->maxstep >> AVR32_SCIF_DFLL0STEP_MAXSTEP_SIZE))
00545 return -1;
00546 #endif
00547 #endif
00548
00549
00550 u_avr32_scif_dfll0conf.DFLL0CONF.en = ENABLE;
00551 AVR32_ENTER_CRITICAL_REGION( );
00552 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00553 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00554 AVR32_LEAVE_CRITICAL_REGION( );
00555
00556
00557 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00558 return -1;
00559
00560
00561 #if (defined(__GNUC__) \
00562 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00563 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00564 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00565
00566 tempo = ((pdfllconfig->coarsemaxstep << AVR32_SCIF_DFLL0STEP_CSTEP_OFFSET)&AVR32_SCIF_DFLL0STEP_CSTEP_MASK)
00567 | ((pdfllconfig->finemaxstep << AVR32_SCIF_DFLL0STEP_FSTEP_OFFSET)&AVR32_SCIF_DFLL0STEP_FSTEP_MASK);
00568 AVR32_ENTER_CRITICAL_REGION( );
00569 SCIF_UNLOCK(AVR32_SCIF_DFLL0STEP);
00570 AVR32_SCIF.dfll0step = tempo;
00571 AVR32_LEAVE_CRITICAL_REGION( );
00572 #else
00573
00574 AVR32_ENTER_CRITICAL_REGION( );
00575 SCIF_UNLOCK(AVR32_SCIF_DFLL0STEP);
00576 AVR32_SCIF.dfll0step = (pdfllconfig->maxstep << AVR32_SCIF_DFLL0STEP_MAXSTEP_OFFSET)&AVR32_SCIF_DFLL0STEP_MAXSTEP_MASK;
00577 AVR32_LEAVE_CRITICAL_REGION( );
00578 #endif
00579
00580
00581 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00582 return -1;
00583
00584
00585 AVR32_ENTER_CRITICAL_REGION( );
00586 SCIF_UNLOCK(AVR32_SCIF_DFLL0FMUL);
00587 AVR32_SCIF.dfll0fmul = (pdfllconfig->fmul << AVR32_SCIF_DFLL0FMUL_FMUL_OFFSET)&AVR32_SCIF_DFLL0FMUL_FMUL_MASK;
00588 AVR32_LEAVE_CRITICAL_REGION( );
00589
00590
00591 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00592 return -1;
00593
00594
00595 u_avr32_scif_dfll0conf.DFLL0CONF.mode = SCIF_DFLL0_MODE_CLOSEDLOOP;
00596 u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse;
00597 AVR32_ENTER_CRITICAL_REGION( );
00598 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00599 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00600 AVR32_LEAVE_CRITICAL_REGION( );
00601
00602
00603 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00604 return -1;
00605
00606
00607
00608 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0LOCKF_MASK))
00609 return -1;
00610
00611 return PASS;
00612 }
00613
00614
00615 long int scif_dfll0_closedloop_configure_and_start( const scif_gclk_opt_t *gc_dfllif_ref_opt,
00616 unsigned long long target_freq_hz,
00617 bool enable_ssg)
00618 {
00619 scif_dfll_closedloop_conf_t DfllConfig;
00620 int gc_source_clock_freq_hz;
00621
00622
00623
00624
00625 if(SCIF_GCCTRL_SLOWCLOCK == gc_dfllif_ref_opt->clock_source)
00626 gc_source_clock_freq_hz = SCIF_SLOWCLOCK_FREQ_HZ;
00627 else if((SCIF_GCCTRL_OSC32K == gc_dfllif_ref_opt->clock_source) || (SCIF_GCCTRL_RC32K == gc_dfllif_ref_opt->clock_source))
00628 gc_source_clock_freq_hz = SCIF_RC32K_FREQ_HZ;
00629 else if(SCIF_GCCTRL_OSC0 == gc_dfllif_ref_opt->clock_source)
00630 gc_source_clock_freq_hz = gc_dfllif_ref_opt->extosc_f;
00631 else if(SCIF_GCCTRL_RC120M == gc_dfllif_ref_opt->clock_source)
00632 gc_source_clock_freq_hz = SCIF_RC120M_FREQ_HZ;
00633 else if(SCIF_GCCTRL_CLK1K == gc_dfllif_ref_opt->clock_source)
00634 gc_source_clock_freq_hz = 1000;
00635 else
00636 return -1;
00637
00638
00639 if(scif_dfll0_closedloop_mainref_gc_enable(gc_dfllif_ref_opt))
00640 return(-1);
00641
00642
00643
00644 DfllConfig.coarse = ((unsigned long long)(target_freq_hz - SCIF_DFLL_MINFREQ_HZ)*255)/(SCIF_DFLL_MAXFREQ_HZ - SCIF_DFLL_MINFREQ_HZ);
00645
00646
00647
00648 if(0 == gc_dfllif_ref_opt->diven)
00649 DfllConfig.fmul = ((unsigned long long)target_freq_hz<<16)/gc_source_clock_freq_hz;
00650 else
00651 DfllConfig.fmul = ((((unsigned long long)target_freq_hz<<16)/gc_source_clock_freq_hz)<<1)*(1+gc_dfllif_ref_opt->divider);
00652
00653
00654 #if (defined(__GNUC__) \
00655 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00656 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00657 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00658
00659 DfllConfig.finemaxstep = 0x0000004;
00660 DfllConfig.coarsemaxstep = 0x0000004;
00661 #else
00662
00663
00664
00665
00666
00667
00668 DfllConfig.maxstep = 0x0040004;
00669 #endif
00670
00671
00672
00673
00674
00675
00676
00677
00678 if(scif_dfll0_closedloop_start(&DfllConfig))
00679 return -1;
00680
00681
00682
00683 if(TRUE == enable_ssg)
00684 {
00685 ;
00686 }
00687 return PASS;
00688 }
00689
00704 void scif_start_rc120M(void)
00705 {
00706 AVR32_ENTER_CRITICAL_REGION( );
00707
00708 SCIF_UNLOCK(AVR32_SCIF_RC120MCR);
00709 AVR32_SCIF.rc120mcr = AVR32_SCIF_RC120MCR_EN_MASK;
00710 AVR32_LEAVE_CRITICAL_REGION( );
00711 }
00712
00713 void scif_stop_rc120M(void)
00714 {
00715 unsigned long temp = AVR32_SCIF.rc120mcr;
00716
00717 temp &= ~AVR32_SCIF_RC120MCR_EN_MASK;
00718 AVR32_ENTER_CRITICAL_REGION( );
00719
00720 SCIF_UNLOCK(AVR32_SCIF_RC120MCR);
00721 AVR32_SCIF.rc120mcr = temp;
00722 AVR32_LEAVE_CRITICAL_REGION( );
00723 }
00724
00725
00726
00730 void scif_start_rc32k(void)
00731 {
00732 AVR32_ENTER_CRITICAL_REGION( );
00733
00734 SCIF_UNLOCK(AVR32_SCIF_RC32KCR);
00735 AVR32_SCIF.rc32kcr = AVR32_SCIF_RC32KCR_EN_MASK;
00736 AVR32_LEAVE_CRITICAL_REGION( );
00737 }
00738
00739 void scif_stop_rc32k(void)
00740 {
00741 unsigned long temp = AVR32_SCIF.rc32kcr;
00742
00743 temp &= ~AVR32_SCIF_RC32KCR_EN_MASK;
00744 AVR32_ENTER_CRITICAL_REGION( );
00745
00746 SCIF_UNLOCK(AVR32_SCIF_RC32KCR);
00747 AVR32_SCIF.rc32kcr = temp;
00748 AVR32_LEAVE_CRITICAL_REGION( );
00749 }
00750
00751 void scif_disable_rc32out(void)
00752 {
00753 unsigned long temp;
00754 AVR32_ENTER_CRITICAL_REGION( );
00755 temp = AVR32_PM.ppcr & (~AVR32_PM_PPCR_FRC32_MASK);
00756
00757 AVR32_PM.unlock = 0xAA000000 | AVR32_PM_PPCR;
00758 AVR32_PM.ppcr = temp;
00759 AVR32_LEAVE_CRITICAL_REGION( );
00760 }
00761
00766 long int scif_start_gclk(unsigned int gclk, const scif_gclk_opt_t *opt)
00767 {
00768 #ifdef AVR32SFW_INPUT_CHECK
00769
00770 if( gclk > AVR32_SCIF_GCLK_NUM )
00771 {
00772 return -1;
00773 }
00774
00775 if(( opt->clock_source >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( opt->clock_source < 0 ))
00776 {
00777 return -1;
00778 }
00779 #endif // AVR32SFW_INPUT_CHECK
00780
00781
00782 if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00783 return -1;
00784
00785
00786 AVR32_SCIF.gcctrl[gclk] = ((opt->divider << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK)
00787 |((opt->diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK)
00788 |((opt->clock_source << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK)
00789 |(AVR32_SCIF_GCCTRL_CEN_MASK);
00790
00791 return PASS;
00792 }
00793
00794
00795 long int scif_stop_gclk(unsigned int gclk)
00796 {
00797 unsigned int timeout = SCIF_POLL_TIMEOUT;
00798
00799 #ifdef AVR32SFW_INPUT_CHECK
00800
00801 if( gclk > AVR32_SCIF_GCLK_NUM )
00802 {
00803 return -1;
00804 }
00805 #endif // AVR32SFW_INPUT_CHECK
00806
00807
00808 AVR32_SCIF.gcctrl[gclk] &= ~AVR32_SCIF_GCCTRL_CEN_MASK;
00809
00810
00811 while(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00812 {
00813 if(--timeout == 0)
00814 return -1;
00815 }
00816
00817 return PASS;
00818 }
00819
00820
00821 long int scif_gc_setup(unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor)
00822 {
00823 int restart_gc = false;
00824
00825
00826
00827 divfactor = (divfactor>>1) -1;
00828
00829 #ifdef AVR32SFW_INPUT_CHECK
00830
00831 if( gclk > AVR32_SCIF_GCLK_NUM )
00832 {
00833 return -1;
00834 }
00835
00836 if(( clk_src >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( clk_src < 0 ))
00837 {
00838 return -1;
00839 }
00840
00841 if(diven)
00842 {
00843 if(divfactor >= (1<<AVR32_SCIF_GCCTRL_DIV_SIZE))
00844 return -1;
00845 }
00846 #endif // AVR32SFW_INPUT_CHECK
00847
00848
00849 if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00850 {
00851 restart_gc = true;
00852 if(scif_stop_gclk(gclk) < 0)
00853 return -1;
00854 }
00855
00856
00857 AVR32_SCIF.gcctrl[gclk] = ((divfactor << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK)
00858 |((diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK)
00859 |((clk_src << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK);
00860
00861
00862 if(true == restart_gc)
00863 AVR32_SCIF.gcctrl[gclk] |= (AVR32_SCIF_GCCTRL_CEN_MASK);
00864
00865 return PASS;
00866 }
00867
00868
00869 long int scif_gc_enable(unsigned int gclk)
00870 {
00871 #ifdef AVR32SFW_INPUT_CHECK
00872
00873 if( gclk > AVR32_SCIF_GCLK_NUM )
00874 {
00875 return -1;
00876 }
00877 #endif // AVR32SFW_INPUT_CHECK
00878
00879
00880 if(!(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK))
00881 AVR32_SCIF.gcctrl[gclk] |= (AVR32_SCIF_GCCTRL_CEN_MASK);
00882
00883 return PASS;
00884 }
00885
00903 long int scif_pclksr_statushigh_wait(unsigned long statusMask)
00904 {
00905 unsigned int timeout = SCIF_POLL_TIMEOUT;
00906
00907 while(!(AVR32_SCIF.pclksr & statusMask))
00908 {
00909 if(--timeout == 0)
00910 return -1;
00911 }
00912 return PASS;
00913 }