| Property | Value |
| Project Name: | d:\documents\ntnu\crayxd1\!fpwmv3\src\80-0037_vhdl\par\xc2vp50 |
| Target Device: | xc2vp50 |
| Report Generated: | Monday 12/04/06 at 15:27 |
| Printable Summary (View as HTML) | buf_summary.html |
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slices: | 499 | 23616 | 2% | |
| Number of Slice Flip Flops: | 653 | 47232 | 1% | |
| Number of 4 input LUTs: | 349 | 47232 | 0% | |
| Number of bonded IOBs: | 139 | 692 | 20% | |
| Number of GCLKs: | 8 | 16 | 50% |
| Property | Value |
| Data Not Yet Available |
| Constraint(s) | Requested | Actual | Logic Levels |
| Data Not Yet Available |
| Report Name | Status | Last Date Modified |
| Synthesis Report | Current | Monday 12/04/06 at 15:27 |