Property | Value |
Project Name: | d:\documents\ntnu\crayxd1\!fpwmv3\src\80-0037_vhdl\par\xc2vp50 |
Target Device: | xc2vp50 |
Report Generated: | Tuesday 10/31/06 at 15:33 |
Printable Summary (View as HTML) | pwm_summary.html |
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slices: | 219 | 23616 | 0% | |
Number of Slice Flip Flops: | 363 | 47232 | 0% | |
Number of 4 input LUTs: | 235 | 47232 | 0% | |
Number of bonded IOBs: | 354 | 692 | 51% |
Property | Value |
Data Not Yet Available |
Constraint(s) | Requested | Actual | Logic Levels |
Data Not Yet Available |
Report Name | Status | Last Date Modified |
Synthesis Report | Current | Tuesday 10/31/06 at 15:33 |