Design Overview for buf

PropertyValue
Project Name:d:\documents\ntnu\crayxd1\!fpwmv3\src\80-0037_vhdl\par\xc2vp50
Target Device:xc2vp50
Report Generated:Monday 12/04/06 at 15:27
Printable Summary (View as HTML)buf_summary.html

Device Utilization Summary (estimated values)

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slices:499236162% 
Number of Slice Flip Flops:653472321% 
Number of 4 input LUTs:349472320% 
Number of bonded IOBs:13969220% 
Number of GCLKs:81650% 

Performance Summary

PropertyValue
Data Not Yet Available  

Failing Constraints

Constraint(s)RequestedActualLogic Levels
Data Not Yet Available   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentMonday 12/04/06 at 15:27