00001
00002 #ifndef __INTERCONNECT_MASTER_HH__
00003 #define __INTERCONNECT_MASTER_HH__
00004
00005 #include <iostream>
00006
00007 #include "base/range.hh"
00008 #include "targetarch/isa_traits.hh"
00009 #include "mem/bus/base_interface.hh"
00010
00011 #include "interconnect_interface.hh"
00012 #include "interconnect.hh"
00013
00014 class Interconnect;
00015
00026 template <class MemType>
00027 class InterconnectMaster : public InterconnectInterface
00028 {
00029 private:
00030
00031 MemType* thisCache;
00032
00033 Addr currentAddr;
00034 int currentToCpuId;
00035 bool currentValsValid;
00036
00037
00038 std::vector<std::pair<Addr, Tick>* > outstandingRequestAddrs;
00039
00040 public:
00051 InterconnectMaster(const std::string &name,
00052 Interconnect* interconnect,
00053 MemType* cache,
00054 HierParams *hier);
00055
00063 MemAccessResult access(MemReqPtr &req);
00064
00070 void request(Tick time);
00071
00080 void respond(MemReqPtr &req, Tick time){
00081 fatal("CrossbarMaster respond method not implemented");
00082 }
00083
00091 bool grantData();
00092
00098 void deliver(MemReqPtr &req);
00099
00106 bool isMaster(){
00107 return true;
00108 }
00109
00123 std::pair<Addr, int> getTargetAddr();
00124
00131 int getTargetId(){
00132 fatal("getTargetId() not valid for a MasterInterface");
00133 return -1;
00134 }
00135
00141 std::string getCacheName(){
00142 return thisCache->name();
00143 }
00144
00145
00146
00147
00148
00149
00150
00151 };
00152
00153 #endif // __INTERCONNECT_MASTER_HH__