interconnect_master.cc

00001 
00002 #include <iostream>
00003 #include <vector>
00004 
00005 // Template instantiation includes
00006 #include "mem/config/cache.hh"
00007 #include "mem/config/compression.hh"
00008 
00009 #include "mem/cache/cache.hh"
00010 
00011 #include "mem/cache/tags/cache_tags.hh"
00012 
00013 #if defined(USE_CACHE_LRU)
00014 #include "mem/cache/tags/lru.hh"
00015 #endif
00016 
00017 #if defined(USE_CACHE_FALRU)
00018 #include "mem/cache/tags/fa_lru.hh"
00019 #endif
00020 
00021 #if defined(USE_CACHE_IIC)
00022 #include "mem/cache/tags/iic.hh"
00023 #endif
00024 
00025 #if defined(USE_CACHE_SPLIT)
00026 #include "mem/cache/tags/split.hh"
00027 #endif
00028 
00029 #if defined(USE_CACHE_SPLIT_LIFO)
00030 #include "mem/cache/tags/split_lifo.hh"
00031 #endif
00032 
00033 #include "base/compression/null_compression.hh"
00034 #if defined(USE_LZSS_COMPRESSION)
00035 #include "base/compression/lzss_compression.hh"
00036 #endif
00037 
00038 #include "mem/cache/miss/blocking_buffer.hh"
00039 #include "mem/cache/miss/miss_queue.hh"
00040 
00041 #include "mem/cache/coherence/simple_coherence.hh"
00042 #include "mem/cache/coherence/uni_coherence.hh"
00043 
00044 #include "interconnect_master_impl.hh"
00045 
00046 #ifndef DOXYGEN_SHOULD_SKIP_THIS
00047 
00048 #if defined(USE_CACHE_FALRU)
00049 template class InterconnectMaster<Cache<CacheTags<FALRU,NullCompression>, BlockingBuffer, SimpleCoherence> >;
00050 template class InterconnectMaster<Cache<CacheTags<FALRU,NullCompression>, BlockingBuffer, UniCoherence> >;
00051 template class InterconnectMaster<Cache<CacheTags<FALRU,NullCompression>, MissQueue, SimpleCoherence> >;
00052 template class InterconnectMaster<Cache<CacheTags<FALRU,NullCompression>, MissQueue, UniCoherence> >;
00053 #if defined(USE_LZSS_COMPRESSION)
00054 template class InterconnectMaster<Cache<CacheTags<FALRU,LZSSCompression>, BlockingBuffer, SimpleCoherence> >;
00055 template class InterconnectMaster<Cache<CacheTags<FALRU,LZSSCompression>, BlockingBuffer, UniCoherence> >;
00056 template class InterconnectMaster<Cache<CacheTags<FALRU,LZSSCompression>, MissQueue, SimpleCoherence> >;
00057 template class InterconnectMaster<Cache<CacheTags<FALRU,LZSSCompression>, MissQueue, UniCoherence> >;
00058 #endif
00059 #endif
00060 
00061 #if defined(USE_CACHE_IIC)
00062 template class InterconnectMaster<Cache<CacheTags<IIC,NullCompression>, BlockingBuffer, SimpleCoherence> >;
00063 template class InterconnectMaster<Cache<CacheTags<IIC,NullCompression>, BlockingBuffer, UniCoherence> >;
00064 template class InterconnectMaster<Cache<CacheTags<IIC,NullCompression>, MissQueue, SimpleCoherence> >;
00065 template class InterconnectMaster<Cache<CacheTags<IIC,NullCompression>, MissQueue, UniCoherence> >;
00066 #if defined(USE_LZSS_COMPRESSION)
00067 template class InterconnectMaster<Cache<CacheTags<IIC,LZSSCompression>, BlockingBuffer, SimpleCoherence> >;
00068 template class InterconnectMaster<Cache<CacheTags<IIC,LZSSCompression>, BlockingBuffer, UniCoherence> >;
00069 template class InterconnectMaster<Cache<CacheTags<IIC,LZSSCompression>, MissQueue, SimpleCoherence> >;
00070 template class InterconnectMaster<Cache<CacheTags<IIC,LZSSCompression>, MissQueue, UniCoherence> >;
00071 #endif
00072 #endif
00073 
00074 #if defined(USE_CACHE_LRU)
00075 template class InterconnectMaster<Cache<CacheTags<LRU,NullCompression>, BlockingBuffer, SimpleCoherence> >;
00076 template class InterconnectMaster<Cache<CacheTags<LRU,NullCompression>, BlockingBuffer, UniCoherence> >;
00077 template class InterconnectMaster<Cache<CacheTags<LRU,NullCompression>, MissQueue, SimpleCoherence> >;
00078 template class InterconnectMaster<Cache<CacheTags<LRU,NullCompression>, MissQueue, UniCoherence> >;
00079 #if defined(USE_LZSS_COMPRESSION)
00080 template class InterconnectMaster<Cache<CacheTags<LRU,LZSSCompression>, BlockingBuffer, SimpleCoherence> >;
00081 template class InterconnectMaster<Cache<CacheTags<LRU,LZSSCompression>, BlockingBuffer, UniCoherence> >;
00082 template class InterconnectMaster<Cache<CacheTags<LRU,LZSSCompression>, MissQueue, SimpleCoherence> >;
00083 template class InterconnectMaster<Cache<CacheTags<LRU,LZSSCompression>, MissQueue, UniCoherence> >;
00084 #endif
00085 #endif
00086 
00087 #if defined(USE_CACHE_SPLIT)
00088 template class InterconnectMaster<Cache<CacheTags<Split,NullCompression>, BlockingBuffer, SimpleCoherence> >;
00089 template class InterconnectMaster<Cache<CacheTags<Split,NullCompression>, BlockingBuffer, UniCoherence> >;
00090 template class InterconnectMaster<Cache<CacheTags<Split,NullCompression>, MissQueue, SimpleCoherence> >;
00091 template class InterconnectMaster<Cache<CacheTags<Split,NullCompression>, MissQueue, UniCoherence> >;
00092 #if defined(USE_LZSS_COMPRESSION)
00093 template class InterconnectMaster<Cache<CacheTags<Split,LZSSCompression>, BlockingBuffer, SimpleCoherence> >;
00094 template class InterconnectMaster<Cache<CacheTags<Split,LZSSCompression>, BlockingBuffer, UniCoherence> >;
00095 template class InterconnectMaster<Cache<CacheTags<Split,LZSSCompression>, MissQueue, SimpleCoherence> >;
00096 template class InterconnectMaster<Cache<CacheTags<Split,LZSSCompression>, MissQueue, UniCoherence> >;
00097 #endif
00098 #endif
00099 
00100 #if defined(USE_CACHE_SPLIT_LIFO)
00101 template class InterconnectMaster<Cache<CacheTags<SplitLIFO,NullCompression>, BlockingBuffer, SimpleCoherence> >;
00102 template class InterconnectMaster<Cache<CacheTags<SplitLIFO,NullCompression>, BlockingBuffer, UniCoherence> >;
00103 template class InterconnectMaster<Cache<CacheTags<SplitLIFO,NullCompression>, MissQueue, SimpleCoherence> >;
00104 template class InterconnectMaster<Cache<CacheTags<SplitLIFO,NullCompression>, MissQueue, UniCoherence> >;
00105 #if defined(USE_LZSS_COMPRESSION)
00106 template class InterconnectMaster<Cache<CacheTags<SplitLIFO,LZSSCompression>, BlockingBuffer, SimpleCoherence> >;
00107 template class InterconnectMaster<Cache<CacheTags<SplitLIFO,LZSSCompression>, BlockingBuffer, UniCoherence> >;
00108 template class InterconnectMaster<Cache<CacheTags<SplitLIFO,LZSSCompression>, MissQueue, SimpleCoherence> >;
00109 template class InterconnectMaster<Cache<CacheTags<SplitLIFO,LZSSCompression>, MissQueue, UniCoherence> >;
00110 #endif
00111 #endif
00112 
00113 
00114 #endif // DOXYGEN_SHOULD_SKIP_THIS

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