00001
00002 #ifndef __IDEAL_INTERCONNECT_HH__
00003 #define __IDEAL_INTERCONNECT_HH__
00004
00005 #include <iostream>
00006 #include <vector>
00007 #include <list>
00008
00009 #include "interconnect.hh"
00010
00011 #define DEBUG_IDEAL_INTERCONNECT
00012
00022 class IdealInterconnect : public Interconnect
00023 {
00024
00025 private:
00026
00027 std::list<InterconnectRequest* > requestQueue;
00028 std::list<InterconnectDelivery* > grantQueue;
00029 std::vector<int> blockedInterfaces;
00030
00031 void scheduleArbitrationEvent(Tick cycle);
00032
00033 #ifdef DEBUG_IDEAL_INTERCONNECT
00034 void printRequestQueue();
00035 void printGrantQueue();
00036 #endif //DEBUG_IDEAL_INTERCONNECT
00037
00038 public:
00039
00060 IdealInterconnect(const std::string &_name,
00061 int _width,
00062 int _clock,
00063 int _transDelay,
00064 int _arbDelay,
00065 int _cpu_count,
00066 HierParams *_hier)
00067 : Interconnect(_name,
00068 _width,
00069 _clock,
00070 _transDelay,
00071 _arbDelay,
00072 _cpu_count,
00073 _hier){
00074
00075 if(_width <= 0){
00076 fatal("The idealInterconnect must have a finite width, "
00077 "or else the cache implementation won't work");
00078 }
00079
00080 transferDelay = _transDelay;
00081 arbitrationDelay = _arbDelay;
00082
00083 }
00084
00088 ~IdealInterconnect(){ }
00089
00098 void request(Tick time, int fromID);
00099
00100
00111 void send(MemReqPtr& req, Tick time, int fromID);
00112
00121 void arbitrate(Tick cycle);
00122
00138 void deliver(MemReqPtr& req, Tick cycle, int toID, int fromID);
00139
00146 void setBlocked(int fromInterface);
00147
00155 void clearBlocked(int fromInterface);
00156
00165 int getChannelCount(){
00166 return -1;
00167 }
00168
00175 std::vector<int> getChannelSample(){
00176 fatal("Ideal Interconnect has no channels");
00177 std::vector<int> retval;
00178 return retval;
00179 }
00180
00187 void writeChannelDecriptor(std::ofstream &stream){
00188 fatal("Ideal Interconnect has no channel descriptor");
00189 }
00190 };
00191
00192 #endif // __IDEAL_INTERCONNECT_HH__