split_trans_bus.hh

00001 
00002 #ifndef __SPLIT_TRANS_BUS_HH__
00003 #define __SPLIT_TRANS_BUS_HH__
00004 
00005 #include <iostream>
00006 #include <vector>
00007 #include <queue>
00008 
00009 #include "interconnect.hh"
00010 
00011 #define DEBUG_SPLIT_TRANS_BUS
00012 
00025 class SplitTransBus : public Interconnect
00026 {
00027     private:
00028 
00029         std::list<InterconnectRequest* > requestQueue;
00030         std::list<InterconnectDelivery* > deliverQueue;
00031         
00032         /* in a pipelined, bi-directional bus we can issue one request 
00033            in each direction each clock cycle */
00034         std::list<InterconnectRequest* >* slaveRequestQueue;
00035         
00036         bool pipelined;
00037         
00038         void addToList(std::list<InterconnectRequest*>* inList,
00039                        InterconnectRequest* icReq);
00040         
00041         typedef enum{STB_MASTER, STB_SLAVE, STB_NOT_PIPELINED} grant_type;
00042         void grantInterface(grant_type gt, Tick cycle);
00043         
00044         void scheduleArbitrationEvent(Tick possibleArbCycle);
00045         void scheduleDeliverEvent(Tick possibleArbCycle);
00046         
00047         bool doProfile;
00048         int useCycleSample;
00049         
00050 #ifdef DEBUG_SPLIT_TRANS_BUS
00051         void checkIfSorted(std::list<InterconnectRequest*>* inList);
00052         void printRequestQueue();
00053         void printDeliverQueue();
00054 #endif //DEBUG_SPLIT_TRANS_BUS
00055         
00056     public:
00057         
00073         SplitTransBus(const std::string &_name,
00074                       int _width, 
00075                       int _clock,
00076                       int _transDelay,
00077                       int _arbDelay,
00078                       int _cpu_count,
00079                       bool _pipelined,
00080                       HierParams *_hier)
00081             : Interconnect(_name,
00082                            _width, 
00083                            _clock, 
00084                            _transDelay, 
00085                            _arbDelay,
00086                            _cpu_count,
00087                            _hier){
00088             
00089             pipelined = _pipelined;
00090             
00091             if(arbitrationDelay < transferDelay && !pipelined){
00092                 fatal("This bus implementation requires the arbitration "
00093                       "delay to be longer than or equal to the transfer "
00094                       "delay");
00095             }
00096             
00097             doProfile = false;
00098             useCycleSample = 0;
00099             
00100             if(pipelined){
00101                 slaveRequestQueue = new std::list<InterconnectRequest*>;
00102             }
00103         }
00104         
00109         ~SplitTransBus(){
00110             if(pipelined){
00111                 delete slaveRequestQueue;
00112             }
00113         }
00114         
00125         void request(Tick time, int fromID);
00126 
00141         void send(MemReqPtr& req, Tick time, int fromID);
00142         
00154         void arbitrate(Tick cycle);
00155         
00169         void deliver(MemReqPtr& req, Tick cycle, int toID, int fromID);
00170         
00178         void setBlocked(int fromInterface);
00179         
00185         void clearBlocked(int fromInterface);
00186         
00187         
00196         int getChannelCount(){
00197             return 1;
00198         }
00199         
00210         std::vector<int> getChannelSample();
00211         
00218         void writeChannelDecriptor(std::ofstream &stream){
00219             stream << "0: The shared bus\n";
00220         }
00221 
00222 };
00223 #endif // SPLIT_TRANS_BUS_HH

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