Synopsys Altera Technology Mapper, Version maprc, Build 3214R, Built Feb 25 2016 17:00:03 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.03 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) @N:MF807 : | Advanced Synthesis is enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 123MB) @N:MO111 : | Tristate driver tri_inst (in view: endat22.ENDAT22_S(behav)) on net D[0] (in view: endat22.ENDAT22_S(behav)) has its enable tied to GND. Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 123MB) @N: : spi_if.vhd(90) | Found counter in view:endat22.spi_if(behav) inst cnt_data_byte[3:0] @N: : endat22_kernel.vhd(1196) | Found counter in view:endat22.ENDAT22_INTAPB(behav) inst U_INTREG.KERNEL.start_pulse_ct[3:0] @N: : eclkgen.vhd(1137) | Found updn counter in view:endat22.eclkgen(behav) inst delay_ct[7:0] @N: : eclkgen.vhd(1401) | Found counter in view:endat22.eclkgen(behav) inst sb_ct[12:0] @N: : eclkgen.vhd(1565) | Found counter in view:endat22.eclkgen(behav) inst ct_30us[4:0] Encoding state machine rq_bit[0:3] (in view: endat22.eclkgen(behav)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N: : timer_1us.vhd(200) | Found counter in view:endat22.timer_1us(behav) inst Q[6:0] @N: : timer_50ms.vhd(70) | Found counter in view:endat22.timer_1(behav) inst rq[6:0] @N: : timer_50ms.vhd(70) | Found counter in view:endat22.timer_0(behav) inst rq[6:0] @N: : counter_par.vhd(63) | Found counter in view:endat22.counter_par(behav) inst rq[7:0] @N: : digfilt_par2.vhd(79) | Found counter in view:endat22.digfilt_par2(behav) inst rq[5:0] Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 126MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 129MB peak: 129MB) Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 130MB peak: 134MB) Auto Dissolve of STA (inst of view:endat22.statreg_8x(behav)) Auto Dissolve of U_INTREG.KERNEL.sp_w (inst of view:endat22.spw(behav)) Auto Dissolve of port_1_2\.io1 (inst of view:endat22.SYNC_PORT_DEC(rtl)) Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 142MB peak: 142MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 149MB peak: 170MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 170MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 150MB peak: 170MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 149MB peak: 170MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 147MB peak: 170MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 147MB peak: 170MB) Finished preparing to map (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 147MB peak: 170MB) Finished technology mapping (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 196MB peak: 214MB) @N:MF321 : | 18 registers to be packed into RAMs/DSPs blocks U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1[0] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1[1] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1[2] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1[3] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1[4] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1[5] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1[6] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1[7] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1[8] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.time_tst[0] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.time_tst[1] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.time_tst[2] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.time_tst[3] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.time_tst[4] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.time_tst[5] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.time_tst[6] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.time_tst[7] U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.time_tst[8] New registers created by packing : U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1_ret U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1_ret_1 U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1_ret_2 U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1_ret_3 U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1_ret_4 U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1_ret_5 U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1_ret_6 U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1_ret_7 U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1_ret_8 U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1_ret_9 U_INTAPB.U_INTREG.KERNEL.eclk.Frequ.dfreq_1_ret_10_0 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 196MB peak: 214MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 198MB peak: 214MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 972 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId0001 clk port 972 qcfg29 ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 177MB peak: 214MB) Writing Analyst data base C:\Users\anders\Desktop\Mazet\synplify\E22_spi_altera_Cyclone4_enc\rev_2\synwork\ENDAT22_S_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 197MB peak: 214MB) Writing Verilog Netlist and constraint files Writing .vqm output for Quartus Writing scf file... (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:16s; Memory used current: 199MB peak: 214MB) @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Netlist and constraint files (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:16s; Memory used current: 197MB peak: 214MB) Start final timing analysis (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:16s; Memory used current: 191MB peak: 214MB) @W:MT420 : | Found inferred clock ENDAT22_S|clk with period 20.00ns. Please declare a user-defined clock on object "p:clk" ##### START OF TIMING REPORT #####[ # Timing Report written on Mon Apr 25 17:26:24 2016 # Top view: ENDAT22_S Requested Frequency: 50.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 5.494 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------- ENDAT22_S|clk 50.0 MHz 68.9 MHz 20.000 14.506 5.494 inferred Inferred_clkgroup_0 ===================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------- ENDAT22_S|clk ENDAT22_S|clk | 20.000 5.494 | No paths - | No paths - | No paths - ==================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: ENDAT22_S|clk ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------- U_INTAPB.U_INTREG.KERNEL.eclk.qautomat[2] ENDAT22_S|clk dffeas q qautomat_2 0.884 5.494 U_INTAPB.U_INTREG.KERNEL.eclk.qautomat[5] ENDAT22_S|clk dffeas q qautomat_5 0.884 5.548 U_INTAPB.U_INTREG.KERNEL.eclk.qautomat[4] ENDAT22_S|clk dffeas q qautomat_4 0.884 5.899 U_INTAPB.U_INTREG.KERNEL.eclk.qautomat[3] ENDAT22_S|clk dffeas q qautomat_3 0.884 5.953 U_INTAPB.U_INTREG.KERNEL.eclk.qautomat[1] ENDAT22_S|clk dffeas q qautomat_1 0.884 6.074 U_INTAPB.U_INTREG.KERNEL.eclk.qautomat[0] ENDAT22_S|clk dffeas q qautomat_0 0.884 6.284 U_INTAPB.U_INTREG.KERNEL.eclk.issi_flag ENDAT22_S|clk dffeas q issi_flag 0.884 6.950 U_INTAPB.U_INTREG.KERNEL.TEST2.rq[7] ENDAT22_S|clk dffeas q rq_7 0.884 7.179 U_INTAPB.U_INTREG.KERNEL.eclk.delay_flag2 ENDAT22_S|clk dffeas q delay_flag2 0.884 7.255 port_1_2\.SPI1\.SPI_1.id_byte[6] ENDAT22_S|clk dffeas q id_byte_0 0.884 7.340 ==================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------- U_INTAPB.U_INTREG.KERNEL.eclk.qautomat[2] ENDAT22_S|clk dffeas d qautomat_72[2] 20.551 5.494 U_INTAPB.U_INTREG.KERNEL.eclk.qautomat[5] ENDAT22_S|clk dffeas ena G_3507 19.912 6.002 U_INTAPB.U_INTREG.KERNEL.eclk.qfreq[1] ENDAT22_S|clk dffeas sclr qfreq_4_0_0__g1 19.988 6.289 U_INTAPB.U_INTREG.KERNEL.eclk.qfreq[2] ENDAT22_S|clk dffeas sclr qfreq_4_0_0__g1 19.988 6.289 U_INTAPB.U_INTREG.KERNEL.eclk.qfreq[3] ENDAT22_S|clk dffeas sclr qfreq_4_0_0__g1 19.988 6.289 U_INTAPB.U_INTREG.KERNEL.eclk.qfreq[4] ENDAT22_S|clk dffeas sclr qfreq_4_0_0__g1 19.988 6.289 U_INTAPB.U_INTREG.KERNEL.eclk.qfreq[5] ENDAT22_S|clk dffeas sclr qfreq_4_0_0__g1 19.988 6.289 U_INTAPB.U_INTREG.KERNEL.eclk.qfreq[6] ENDAT22_S|clk dffeas sclr qfreq_4_0_0__g1 19.988 6.289 U_INTAPB.U_INTREG.KERNEL.eclk.qfreq[7] ENDAT22_S|clk dffeas sclr qfreq_4_0_0__g1 19.988 6.289 U_INTAPB.U_INTREG.KERNEL.eclk.qfreq[8] ENDAT22_S|clk dffeas sclr qfreq_4_0_0__g1 19.988 6.289 ========================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.088 + Intrinsic clock delay: 0.639 + Clock delay at ending point: 0.000 (ideal) = Required time: 20.551 - Propagation time: 14.418 - Intrinsic clock delay: 0.639 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 5.494 Number of logic level(s): 19 Starting point: U_INTAPB.U_INTREG.KERNEL.eclk.qautomat[2] / q Ending point: U_INTAPB.U_INTREG.KERNEL.eclk.qautomat[2] / d The start point is clocked by ENDAT22_S|clk [rising] on pin clk The end point is clocked by ENDAT22_S|clk [rising] on pin clk Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------- U_INTAPB.U_INTREG.KERNEL.eclk.qautomat[2] dffeas q Out 0.245 0.884 - qautomat_2 Net - - 1.421 - 72 U_INTAPB.U_INTREG.KERNEL.eclk.automat\.qautomat212_2 fiftyfivenm_lcell_comb datab In - 2.305 - U_INTAPB.U_INTREG.KERNEL.eclk.automat\.qautomat212_2 fiftyfivenm_lcell_comb combout Out 0.466 2.772 - qautomat212_2 Net - - 0.637 - 20 U_INTAPB.U_INTREG.KERNEL.eclk.automat\.qautomat215 fiftyfivenm_lcell_comb datac In - 3.409 - U_INTAPB.U_INTREG.KERNEL.eclk.automat\.qautomat215 fiftyfivenm_lcell_comb combout Out 0.453 3.862 - qautomat215 Net - - 0.355 - 5 U_INTAPB.U_INTREG.KERNEL.eclk.automat\.qautomat215_RNI76IK1 fiftyfivenm_lcell_comb datad In - 4.217 - U_INTAPB.U_INTREG.KERNEL.eclk.automat\.qautomat215_RNI76IK1 fiftyfivenm_lcell_comb combout Out 0.166 4.383 - un1_ddfreq_121_640_0 Net - - 0.326 - 1 U_INTAPB.U_INTREG.KERNEL.eclk.automat\.qautomat237_RNI7C9D2 fiftyfivenm_lcell_comb datac In - 4.709 - U_INTAPB.U_INTREG.KERNEL.eclk.automat\.qautomat237_RNI7C9D2 fiftyfivenm_lcell_comb combout Out 0.453 5.162 - un1_ddfreq_121_640 Net - - 0.333 - 2 U_INTAPB.U_INTREG.KERNEL.eclk.un1_qautomat216_122_1 fiftyfivenm_lcell_comb datad In - 5.495 - U_INTAPB.U_INTREG.KERNEL.eclk.un1_qautomat216_122_1 fiftyfivenm_lcell_comb combout Out 0.166 5.661 - un1_qautomat216_122_1 Net - - 0.326 - 1 U_INTAPB.U_INTREG.KERNEL.eclk.ddfreq_1 fiftyfivenm_lcell_comb datac In - 5.987 - U_INTAPB.U_INTREG.KERNEL.eclk.ddfreq_1 fiftyfivenm_lcell_comb combout Out 0.453 6.440 - ddfreq_1 Net - - 0.414 - 9 U_INTAPB.U_INTREG.KERNEL.eclk.ddfreq_1[4] fiftyfivenm_lcell_comb datad In - 6.854 - U_INTAPB.U_INTREG.KERNEL.eclk.ddfreq_1[4] fiftyfivenm_lcell_comb combout Out 0.166 7.020 - ddfreq_1[4] Net - - 0.326 - 1 U_INTAPB.U_INTREG.KERNEL.eclk.ddfreq[4] fiftyfivenm_lcell_comb datad In - 7.346 - U_INTAPB.U_INTREG.KERNEL.eclk.ddfreq[4] fiftyfivenm_lcell_comb combout Out 0.166 7.512 - ddfreq[4] Net - - 0.348 - 4 U_INTAPB.U_INTREG.KERNEL.eclk.un15_qsstop2_4 fiftyfivenm_lcell_comb datab In - 7.860 - U_INTAPB.U_INTREG.KERNEL.eclk.un15_qsstop2_4 fiftyfivenm_lcell_comb combout Out 0.466 8.326 - un15_qsstop2_4 Net - - 0.326 - 1 U_INTAPB.U_INTREG.KERNEL.eclk.un15_qsstop2_NE_5 fiftyfivenm_lcell_comb datac In - 8.652 - U_INTAPB.U_INTREG.KERNEL.eclk.un15_qsstop2_NE_5 fiftyfivenm_lcell_comb combout Out 0.453 9.105 - un15_qsstop2_NE_5 Net - - 0.326 - 1 U_INTAPB.U_INTREG.KERNEL.eclk.un15_qsstop2_NE fiftyfivenm_lcell_comb datad In - 9.430 - U_INTAPB.U_INTREG.KERNEL.eclk.un15_qsstop2_NE fiftyfivenm_lcell_comb combout Out 0.166 9.597 - un15_qsstop2_NE Net - - 0.355 - 5 U_INTAPB.U_INTREG.KERNEL.eclk.qautomat_3_sqmuxa_171_a1 fiftyfivenm_lcell_comb datac In - 9.952 - U_INTAPB.U_INTREG.KERNEL.eclk.qautomat_3_sqmuxa_171_a1 fiftyfivenm_lcell_comb combout Out 0.453 10.405 - qautomat_3_sqmuxa_171_a1 Net - - 0.326 - 1 U_INTAPB.U_INTREG.KERNEL.eclk.qautomat_3_sqmuxa_171_a1_RNI4MJ11 fiftyfivenm_lcell_comb datad In - 10.730 - U_INTAPB.U_INTREG.KERNEL.eclk.qautomat_3_sqmuxa_171_a1_RNI4MJ11 fiftyfivenm_lcell_comb combout Out 0.166 10.897 - qautomat_3_sqmuxa_0 Net - - 0.340 - 3 U_INTAPB.U_INTREG.KERNEL.eclk.NoName_cnst_1_0_o8[0] fiftyfivenm_lcell_comb datab In - 11.237 - U_INTAPB.U_INTREG.KERNEL.eclk.NoName_cnst_1_0_o8[0] fiftyfivenm_lcell_comb combout Out 0.466 11.703 - NoName_cnst_1_0_o8[0] Net - - 0.333 - 2 U_INTAPB.U_INTREG.KERNEL.eclk.NoName_cnst_1_i[2] fiftyfivenm_lcell_comb datad In - 12.036 - U_INTAPB.U_INTREG.KERNEL.eclk.NoName_cnst_1_i[2] fiftyfivenm_lcell_comb combout Out 0.166 12.203 - NoName_cnst_1_i[2] Net - - 0.326 - 1 U_INTAPB.U_INTREG.KERNEL.eclk.un1_mode_0_188[2] fiftyfivenm_lcell_comb datad In - 12.528 - U_INTAPB.U_INTREG.KERNEL.eclk.un1_mode_0_188[2] fiftyfivenm_lcell_comb combout Out 0.166 12.695 - un1_mode_0_188[2] Net - - 0.326 - 1 U_INTAPB.U_INTREG.KERNEL.eclk.un1_qautomat_45_sqmuxa_189[2] fiftyfivenm_lcell_comb datab In - 13.020 - U_INTAPB.U_INTREG.KERNEL.eclk.un1_qautomat_45_sqmuxa_189[2] fiftyfivenm_lcell_comb combout Out 0.466 13.486 - un1_qautomat_45_sqmuxa_189[2] Net - - 0.326 - 1 U_INTAPB.U_INTREG.KERNEL.eclk.automat\.qautomat_72_0[2] fiftyfivenm_lcell_comb datab In - 13.812 - U_INTAPB.U_INTREG.KERNEL.eclk.automat\.qautomat_72_0[2] fiftyfivenm_lcell_comb combout Out 0.466 14.278 - qautomat_72_0[2] Net - - 0.326 - 1 U_INTAPB.U_INTREG.KERNEL.eclk.automat\.qautomat_72[2] fiftyfivenm_lcell_comb datac In - 14.604 - U_INTAPB.U_INTREG.KERNEL.eclk.automat\.qautomat_72[2] fiftyfivenm_lcell_comb combout Out 0.453 15.057 - qautomat_72[2] Net - - 0.000 - 1 U_INTAPB.U_INTREG.KERNEL.eclk.qautomat[2] dffeas d In - 15.057 - =================================================================================================================================================== Total path delay (propagation time + ICD at startpoint + setup - ICD at endpoint) of 14.506 is 6.713(46.3%) logic and 7.793(53.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value *Arrival time includes intrinsic clock delay at start point and clock delay at startpoint ##### END OF TIMING REPORT #####] Constraints that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 191MB peak: 214MB) Finished timing report (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 191MB peak: 214MB) ##### START OF AREA REPORT #####[ Design view:endat22.ENDAT22_S(behav) Selecting part 10M25SAE144C8G @N:FA174 : | The following device usage report estimates place and route data. Please look at the place and route report for final resource usage. @W:FA395 : | Internal tristates present in the design, Quartus may convert tristates to AND gates. Total combinational functions 2159 of 24960 ( 8%) Logic element usage by number of inputs 4 input functions 1230 3 input functions 458 [=2 input functions 471 Logic elements by mode normal mode 1919 arithmetic mode 240 Total registers 972 of 25426 ( 3%) I/O pins 20 of 101 (20%), total I/O based on largest package of this part. Number of I/O registers Input DDRs :0 Output DDRs :0 DSP Blocks: 0 (0 nine-bit DSP elements). DSP Utilization: 0.00% of available 55 blocks (110 nine-bit). ShiftTap: 0 (0 registers) Ena: 555 Sload: 174 Sclr: 150 Total ESB: 0 bits ##### END OF AREA REPORT #####] Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 35MB peak: 214MB) Process took 0h:00m:17s realtime, 0h:00m:17s cputime # Mon Apr 25 17:26:25 2016 ###########################################################]