#Build: Synplify Premier L-2016.03, Build 2034R, Feb 25 2016 #install: C:\Synopsys\fpga_L-2016.03 #OS: Windows 8 6.2 #Hostname: LAPTOP # Tue Apr 26 12:42:55 2016 #Implementation: rev_2 Synopsys HDL Compiler, version comp201603rc, Build 022R, built Feb 25 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys VHDL Compiler, version comp201603rc, Build 022R, built Feb 25 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @N:CD720 : std.vhd(123) | Setting time resolution to ns @N: : endat22_spi_ent.vhd(44) | Top entity is set to ENDAT22_S. File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\regist.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\regist2.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\regist_8x.vhd changed - recompiling File C:\Synopsys\fpga_L-2016.03\lib\vhd\misc.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\statreg_8x.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\spw.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\timer_1us.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\endat5_pkg.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\timer_50ms.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\inpff.vhd changed - recompiling File C:\Synopsys\fpga_L-2016.03\lib\vhd\signed.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\regist_8x1.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\statreg2_8x.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\spi_if.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\resource_pkg_b.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\digfilt_par2.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\counter_par.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\uc16_if_rtl.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\sync_port_dec_rtl.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\psw.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\time_table.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\eclkgen.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\control.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\counter_tm_time.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\endat22_kernel.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\endat22_intreg.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\endat22_intapb.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\spi\endat22_spi_ent.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\endat22_s_behav.vhd changed - recompiling File C:\Users\anders\Desktop\Mazet\dsgn\vhdlsource_encrypt\spi\endat22_spi_cfg.vhd changed - recompiling VHDL syntax check successful! Compiler output is up to date. No re-compile necessary At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Apr 26 12:42:56 2016 ###########################################################] Synopsys Netlist Linker, version comp201603rc, Build 022R, built Feb 25 2016 @N: : | Running in 64-bit mode Linker output is up to date. No re-linking necessary At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Apr 26 12:42:56 2016 ###########################################################] Finished Containment srs generation. (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 4MB peak: 4MB) Divided design in to 1 groups Log file for distribution node endat22.ENDAT22_S.behav distcomp0.log Compiling endat22_ENDAT22_S_behav as a separate process Compilation of node endat22.ENDAT22_S.behav finished successfully.Real start time 0h:00m:01s, Real end time = 0h:00m:01s, Total real run time = 0h:00m:00s Distributed Compiler Report *************************** DP Name Status Start time End Time Total Real Time Log File ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ endat22.ENDAT22_S.behav Success 0h:00m:01s 0h:00m:01s 0h:00m:00s C:\Users\anders\Desktop\Mazet\synplify\E22_spi_altera_Cyclone4_enc\rev_2\synwork\\distcomp\distcomp0\distcomp0.log ============================================================================================================================================================================================================ Synopsys Netlist Linker, version comp201603rc, Build 022R, built Feb 25 2016 @N: : | Running in 64-bit mode Linker output is up to date. No re-linking necessary At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 74MB peak: 75MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Apr 26 12:42:58 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 9MB peak: 10MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime Process completed successfully. # Tue Apr 26 12:42:58 2016 ###########################################################] @A: : | multi_srs_gen output is up to date. No run necessary. To force a re-synthesis, select [Resynthesize All] in menu [Run]. Click link to view previous log file. Multi-srs Generator Report Linked File: ENDAT22_S_multi_srs_gen.srr @A: : | premap output is up to date. No run necessary. To force a re-synthesis, select [Resynthesize All] in menu [Run]. Click link to view previous log file. Premap Report Linked File: ENDAT22_S_premap.srr @A: : | fpga_mapper output is up to date. No run necessary. To force a re-synthesis, select [Resynthesize All] in menu [Run]. Click link to view previous log file. Map & Optimize Report Linked File: ENDAT22_S_fpga_mapper.srr