Synopsys Altera Technology Pre-mapping, Version maprc, Build 3214R, Built Feb 25 2016 17:00:03 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.03 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) @A:MF827 : | No constraint file specified. Linked File: ENDAT22_S_scck.rpt Printing clock summary report in "C:\Users\anders\Desktop\Mazet\synplify\E22_spi_altera_Cyclone4_enc\rev_2\ENDAT22_S_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) @N:MF807 : | Advanced Synthesis is enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB) @N:BN133 : | Ignoring syn_hier=hard property on top-level design. Finished Clear Box Flow. (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 125MB peak: 127MB) Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 127MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------- ENDAT22_S|clk 50.0 MHz 20.000 inferred Inferred_clkgroup_0 1007 ======================================================================================== Finished Pre Mapping Phase. @N:MO111 : | Tristate driver tri_inst (in view: endat22.ENDAT22_S(behav)) on net D[0] (in view: endat22.ENDAT22_S(behav)) has its enable tied to GND. @N:BN225 : | Writing default property annotation file C:\Users\anders\Desktop\Mazet\synplify\E22_spi_altera_Cyclone4_enc\rev_2\ENDAT22_S.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 125MB peak: 127MB) Encoding state machine rq_bit[0:3] (in view: endat22.eclkgen(behav)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 None None Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 126MB peak: 128MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 40MB peak: 128MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Apr 25 17:26:07 2016 ###########################################################]