vga_controller_800_60 Project Status (04/13/2014 - 04:42:05)
Project File: fpga.xise Parser Errors: No Errors
Module Name: vga_controller_800_60 Implementation State: Programming File Not Generated
Target Device: xc3s1200e-4fg320
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentfr 11. apr 20:52:04 2014   
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentsų 13. apr 04:41:55 2014
WebTalk Log FileCurrentsų 13. apr 04:42:02 2014

Date Generated: 04/13/2014 - 04:42:05