vga_draw Project Status (04/19/2014 - 14:28:08)
Project File: fpga.xise Parser Errors: No Errors
Module Name: vga_draw Implementation State: Synthesized (Failed)
Target Device: xc3s1200e-4fg320
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers 233 17,344 1%  
    Number used as Flip Flops 227      
    Number used as Latches 6      
Number of 4 input LUTs 494 17,344 2%  
Number of occupied Slices 341 8,672 3%  
    Number of Slices containing only related logic 341 341 100%  
    Number of Slices containing unrelated logic 0 341 0%  
Total Number of 4 input LUTs 602 17,344 3%  
    Number used as logic 494      
    Number used as a route-thru 108      
Number of bonded IOBs 29 250 11%  
Number of RAMB16s 19 28 67%  
Number of BUFGMUXs 2 24 8%  
Average Fanout of Non-Clock Nets 3.33      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentfr 18. apr 20:12:33 2014   
Translation ReportCurrentfr 18. apr 20:12:42 2014   
Map ReportCurrentfr 18. apr 20:12:49 2014   
Place and Route ReportCurrentfr 18. apr 20:13:22 2014   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentfr 18. apr 20:13:28 2014   
Bitgen ReportCurrentfr 18. apr 20:13:40 2014   
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of Datefr 18. apr 22:17:00 2014
WebTalk Log FileOut of Datefr 18. apr 22:17:07 2014

Date Generated: 04/19/2014 - 14:31:08