| ev_ctrl_storage_byte Project Status (04/19/2014 - 16:07:49) | |||
| Project File: | fpga.xise | Parser Errors: | No Errors |
| Module Name: | delay_cell | Implementation State: | Synthesized |
| Target Device: | xc3s1200e-4fg320 |
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| Product Version: | ISE 14.7 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: |
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| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | ||||||
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Report | Out of Date | lø 19. apr 15:55:08 2014 | |
| WebTalk Log File | Out of Date | lø 19. apr 15:55:16 2014 | |