ev_ctrl_storage_byte Project Status (04/19/2014 - 16:07:49)
Project File: fpga.xise Parser Errors: No Errors
Module Name: delay_cell Implementation State: Synthesized
Target Device: xc3s1200e-4fg320
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of Datelø 19. apr 15:55:08 2014
WebTalk Log FileOut of Datelø 19. apr 15:55:16 2014

Date Generated: 04/19/2014 - 16:07:49