test



2010.04.20.14:54:57 Datasheet
Overview
  clk  test
   sdram
 zs_addr  
 zs_ba  
 zs_cas_n  
 zs_cke  
 zs_cs_n  
 zs_dq  
 zs_dqm  
 zs_ras_n  
 zs_we_n  
   LCD
 LCD_data  
 LCD_E  
 LCD_RS  
 LCD_RW  
Processor

   cpu Nios II 9.1

Peripherals

   cpu altera_nios2 9.1

   onchip_memory2_0 altera_avalon_onchip_memory2 9.1

   jtag_uart_0 altera_avalon_jtag_uart 9.1

   sdram altera_avalon_new_sdram_controller 9.1

   LCD altera_avalon_lcd_16207 9.1

   tri_state_bridge_0 altera_avalon_tri_state_bridge 9.1

   sysid altera_avalon_sysid 9.1
Memory Map
cpu alt_vip_vfb_0
 instruction_master  data_master  read_master  write_master
  cpu
jtag_debug_module  0x00420800 0x00420800
  onchip_memory2_0
s1  0x00410000 0x00410000
  jtag_uart_0
avalon_jtag_slave  0x00421080
  sdram
s1  0x01000000 0x01000000 0x01000000 0x01000000
  LCD
control_slave  0x00421000
  cfi_flash_0
s1  0x00000000 0x00000000
  sysid
control_slave  0x00421090

clk

clock_source v9.1





Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cpu

altera_nios2 v9.1

clk clk   cpu
  clk
instruction_master   onchip_memory2_0
  s1
data_master  
  s1
data_master   jtag_uart_0
  avalon_jtag_slave
d_irq  
  irq
instruction_master   sdram
  s1
data_master  
  s1
data_master   LCD
  control_slave
instruction_master   tri_state_bridge_0
  avalon_slave
data_master  
  avalon_slave
data_master   sysid
  control_slave




Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSets 0
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_interruptControllerType Internal
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave cfi_flash_0.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _8
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
impl Fast
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave onchip_memory2_0.s1
exceptionOffset 32
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
cpuReset false
cpuID 0
clockFrequency 100000000
breakSlave cpu.jtag_debug_module
breakOffset 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CPU_IMPLEMENTATION "fast"
BIG_ENDIAN 0
CPU_FREQ 100000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
INITDA_SUPPORTED
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x410020
RESET_ADDR 0x0
BREAK_ADDR 0x420820
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
INST_ADDR_WIDTH 25
DATA_ADDR_WIDTH 25
NUM_OF_SHADOW_REG_SETS 0

onchip_memory2_0

altera_avalon_onchip_memory2 v9.1

cpu instruction_master   onchip_memory2_0
  s1
data_master  
  s1
clk clk  
  clk1




Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
deviceFamily Cyclone II
dualPort false
initMemContent true
initializationFileName onchip_memory2_0
instanceID NONE
memorySize 40960
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "onchip_memory2_0"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SIZE_VALUE 40960u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

jtag_uart_0

altera_avalon_jtag_uart v9.1

clk clk   jtag_uart_0
  clk
cpu data_master  
  avalon_jtag_slave
d_irq  
  irq




Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

sdram

altera_avalon_new_sdram_controller v9.1

clk clk   sdram
  clk
cpu instruction_master  
  s1
data_master  
  s1
alt_vip_vfb_0 read_master  
  s1
write_master  
  s1




Parameters

TAC 5.5
TMRD 3
TRCD 20.0
TRFC 70.0
TRP 20.0
TWR 14.0
casLatency 3
clockRate 100000000
columnWidth 8
dataWidth 16
generateSimulationModel false
initNOPDelay 0.0
initRefreshCommands 2
masteredTristateBridgeSlave
model custom
numberOfBanks 4
numberOfChipSelects 1
pinsSharedViaTriState false
powerUpDelay 100.0
refreshPeriod 15.625
registerDataIn true
rowWidth 12
size 8388608
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

REGISTER_DATA_IN 1
SIM_MODEL_BASE 0
SDRAM_DATA_WIDTH 16
SDRAM_ADDR_WIDTH 22
SDRAM_ROW_WIDTH 12
SDRAM_COL_WIDTH 8
SDRAM_NUM_CHIPSELECTS 1
SDRAM_NUM_BANKS 4
REFRESH_PERIOD 15.625
POWERUP_DELAY 100.0
CAS_LATENCY 3
T_RFC 70.0
T_RP 20.0
T_MRD 3
T_RCD 20.0
T_AC 5.5
T_WR 14.0
INIT_REFRESH_COMMANDS 2
INIT_NOP_DELAY 0.0
SHARED_DATA 0
STARVATION_INDICATOR 0
TRISTATE_BRIDGE_SLAVE ""
IS_INITIALIZED 1
SDRAM_BANK_WIDTH 2
CONTENTS_INFO ""

LCD

altera_avalon_lcd_16207 v9.1

clk clk   LCD
  clk
cpu data_master  
  control_slave




Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cfi_flash_0

altera_avalon_cfi_flash v9.1

tri_state_bridge_0 tristate_master   cfi_flash_0
  s1
clk clk  
  clk




Parameters

actualHoldTime 40.0
actualSetupTime 40.0
actualWaitTime 160.0
addressWidth 22
clockRate 100000000
corePreset CUSTOM
dataWidth 8
holdTime 40
setupTime 40
sharedPorts
timingUnits NS
waitTime 160
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

SETUP_VALUE 40
WAIT_VALUE 160
HOLD_VALUE 40
TIMING_UNITS "ns"
SIZE 4194304u

tri_state_bridge_0

altera_avalon_tri_state_bridge v9.1

clk clk   tri_state_bridge_0
  clk
cpu instruction_master  
  avalon_slave
data_master  
  avalon_slave
tristate_master   cfi_flash_0
  s1




Parameters

registerIncomingSignals true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

sysid

altera_avalon_sysid v9.1

clk clk   sysid
  clk
cpu data_master  
  control_slave




Parameters

id 1698508140
timestamp 1271768091
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ID 1698508140u
TIMESTAMP 1271768091u

alt_vip_tpg_0

alt_vip_tpg v9.1

clk clk   alt_vip_tpg_0
  clock
dout   alt_vip_vfb_0
  din




Parameters

AUTO_CONTROL_CLOCKS_SAME 0
CHANNELS_IN_PAR 3
CTRL_INTERFACE_DEPTH 10
PARAMETERISATION MyPatternGenerator08800600COLORSPACE_RGBSAMPLE_444PROGRESSIVE_FRAMEStrueTPG_PATTERN_COLORBARS128128128]]>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_vfb_0

alt_vip_vfb v9.1

clk clk   alt_vip_vfb_0
  clock
alt_vip_tpg_0 dout  
  din
read_master   sdram
  s1
write_master  
  s1
dout   alt_vip_itc_0
  din




Parameters

AUTO_READ_MASTER_INTERRUPT_USED_MASK 0
AUTO_WRITE_MASTER_MAX_READ_LATENCY 2
AUTO_WRITE_MASTER_INTERRUPT_USED_MASK 0
AUTO_WRITE_MASTER_CLOCKS_SAME 2
AUTO_READ_MASTER_MAX_READ_LATENCY 2
AUTO_WRITE_MASTER_NEED_ADDR_WIDTH 25
AUTO_READ_MASTER_NEED_ADDR_WIDTH 25
AUTO_WRITER_CONTROL_CLOCKS_SAME 0
AUTO_READ_MASTER_CLOCKS_SAME 2
AUTO_READER_CONTROL_CLOCKS_SAME 0
PARAMETERISATION MyFrameBuffer800600813010101900000640643264320100000]]>
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_vip_itc_0

alt_vip_itc v9.1

clk clk   alt_vip_itc_0
  is_clk_rst
alt_vip_vfb_0 dout  
  din




Parameters

USE_EMBEDDED_SYNCS 0
H_BACK_PORCH 152
F_FALLING_EDGE 0
H_SYNC_LENGTH 62
V_ACTIVE_LINES 600
CLOCKS_ARE_SAME 0
FIELD0_V_SYNC_LENGTH 0
BPS 8
GENERATE_SYNC 0
STD_WIDTH 1
AP_LINE 0
FIELD0_V_BLANK 0
V_SYNC_LENGTH 3
INTERLACED 0
V_BLANK 0
USE_CONTROL 0
NUMBER_OF_COLOUR_PLANES 3
V_FRONT_PORCH 1
THRESHOLD 600
H_FRONT_PORCH 33
FIELD0_V_RISING_EDGE 0
FIELD0_V_FRONT_PORCH 0
NO_OF_MODES 1
FIELD0_V_BACK_PORCH 0
H_ACTIVE_PIXELS 800
ACCEPT_COLOURS_IN_SEQ 0
H_BLANK 0
COLOUR_PLANES_ARE_IN_PARALLEL 1
F_RISING_EDGE 0
V_BACK_PORCH 27
FIFO_DEPTH 800
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
generation took 0,01 seconds rendering took 4,66 seconds