nios_system



2010.05.18.13:46:58 Datasheet
Overview
  clk  nios_system
   LCD
 LCD_data  
 LCD_E  
 LCD_RS  
 LCD_RW  
   NIOS_G
 out_port  
 out_port  
   spi_0
 MISO  
 MOSI  
 SCLK  
 SS_n  
   LEDG
 out_port  
 out_port  
 out_port  
 in_port  
 out_port  
 out_port  
 out_port  
Processor

   cpu Nios II 9.1

Peripherals

   cpu altera_nios2 9.1

   onchip_memory2_0 altera_avalon_onchip_memory2 9.1

   jtag_uart_0 altera_avalon_jtag_uart 9.1

   LCD altera_avalon_lcd_16207 9.1

   tri_state_bridge_0 altera_avalon_tri_state_bridge 9.1

   sysid altera_avalon_sysid 9.1

   NIOS_G altera_avalon_pio 9.1

   fifo_req altera_avalon_pio 9.1

   spi_0 altera_avalon_spi 9.1

   LEDG altera_avalon_pio 9.1

   NIOS_R altera_avalon_pio 9.1

   NIOS_B altera_avalon_pio 9.1

   SW altera_avalon_pio 9.1

   SEG7_ADDR altera_avalon_pio 9.1

   SEG7_DATA altera_avalon_pio 9.1

   LEDR altera_avalon_pio 9.1
Memory Map
cpu
 instruction_master  data_master
  cpu
jtag_debug_module  0x00820800 0x00820800
  onchip_memory2_0
s1  0x00810000 0x00810000
  jtag_uart_0
avalon_jtag_slave  0x008210c0
  LCD
control_slave  0x00821020
  cfi_flash_0
s1  0x00400000 0x00400000
  sysid
control_slave  0x008210c8
  NIOS_G
s1  0x00821030
  fifo_req
s1  0x00821040
  spi_0
spi_control_port  0x00821000
  LEDG
s1  0x00821050
  NIOS_R
s1  0x00821060
  NIOS_B
s1  0x00821070
  SW
s1  0x00821080
  SEG7_ADDR
s1  0x00821090
  SEG7_DATA
s1  0x008210a0
  LEDR
s1  0x008210b0

clk

clock_source v9.1





Parameters

clockFrequency 100000000
clockFrequencyKnown true
inputClockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cpu

altera_nios2 v9.1

clk clk   cpu
  clk
instruction_master   onchip_memory2_0
  s1
data_master  
  s1
data_master   jtag_uart_0
  avalon_jtag_slave
d_irq  
  irq
data_master   LCD
  control_slave
instruction_master   tri_state_bridge_0
  avalon_slave
data_master  
  avalon_slave
data_master   sysid
  control_slave
data_master   NIOS_G
  s1
data_master   fifo_req
  s1
data_master   spi_0
  spi_control_port
d_irq  
  irq
data_master   LEDG
  s1
data_master   NIOS_R
  s1
data_master   NIOS_B
  s1
data_master   SW
  s1
d_irq  
  irq
data_master   SEG7_ADDR
  s1
data_master   SEG7_DATA
  s1
data_master   LEDR
  s1




Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSets 0
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_interruptControllerType Internal
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave cfi_flash_0.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _8
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
impl Fast
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave onchip_memory2_0.s1
exceptionOffset 32
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
cpuReset false
cpuID 0
clockFrequency 100000000
breakSlave cpu.jtag_debug_module
breakOffset 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CPU_IMPLEMENTATION "fast"
BIG_ENDIAN 0
CPU_FREQ 100000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
INITDA_SUPPORTED
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x810020
RESET_ADDR 0x400000
BREAK_ADDR 0x820820
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
INST_ADDR_WIDTH 24
DATA_ADDR_WIDTH 24
NUM_OF_SHADOW_REG_SETS 0

onchip_memory2_0

altera_avalon_onchip_memory2 v9.1

cpu instruction_master   onchip_memory2_0
  s1
data_master  
  s1
clk clk  
  clk1




Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
deviceFamily Cyclone II
dualPort false
initMemContent true
initializationFileName onchip_memory2_0
instanceID NONE
memorySize 36768
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "onchip_memory2_0"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SIZE_VALUE 36768u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

jtag_uart_0

altera_avalon_jtag_uart v9.1

clk clk   jtag_uart_0
  clk
cpu data_master  
  avalon_jtag_slave
d_irq  
  irq




Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

LCD

altera_avalon_lcd_16207 v9.1

clk clk   LCD
  clk
cpu data_master  
  control_slave




Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cfi_flash_0

altera_avalon_cfi_flash v9.1

clk clk   cfi_flash_0
  clk
tri_state_bridge_0 tristate_master  
  s1




Parameters

actualHoldTime 40.0
actualSetupTime 40.0
actualWaitTime 160.0
addressWidth 22
clockRate 100000000
corePreset CUSTOM
dataWidth 8
holdTime 40
setupTime 40
sharedPorts ,s1/data
timingUnits NS
waitTime 160
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

SETUP_VALUE 40
WAIT_VALUE 160
HOLD_VALUE 40
TIMING_UNITS "ns"
SIZE 4194304u

tri_state_bridge_0

altera_avalon_tri_state_bridge v9.1

clk clk   tri_state_bridge_0
  clk
cpu instruction_master  
  avalon_slave
data_master  
  avalon_slave
tristate_master   cfi_flash_0
  s1




Parameters

registerIncomingSignals true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

sysid

altera_avalon_sysid v9.1

clk clk   sysid
  clk
cpu data_master  
  control_slave




Parameters

id 1799899977
timestamp 1274183205
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ID 1799899977u
TIMESTAMP 1274183205u

NIOS_G

altera_avalon_pio v9.1

clk clk   NIOS_G
  clk
cpu data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

fifo_req

altera_avalon_pio v9.1

clk clk   fifo_req
  clk
cpu data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

spi_0

altera_avalon_spi v9.1

clk clk   spi_0
  clk
cpu data_master  
  spi_control_port
d_irq  
  irq




Parameters

actualClockRate 3846153.0
actualSlaveSelectToSClkDelay 0.0
clockPhase 0
clockPolarity 0
dataWidth 8
disableAvalonFlowControl false
inputClockRate 100000000
insertDelayBetweenSlaveSelectAndSClk false
insertSync false
lsbOrderedFirst false
masterSPI true
numberOfSlaves 1
syncRegDepth 2
targetClockRate 4000000
targetSlaveSelectToSClkDelay 0.0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DATABITS 8
DATAWIDTH 16
TARGETCLOCK 4000000u
CLOCKUNITS "Hz"
CLOCKMULT 1
NUMSLAVES 1
ISMASTER 1
CLOCKPOLARITY 0
CLOCKPHASE 0
LSBFIRST 0
EXTRADELAY 0
INSERT_SYNC 0
SYNC_REG_DEPTH 2
TARGETSSDELAY "0.0"
DELAYUNITS "ns"
DELAYMULT "1.0E-9"
PREFIX "spi_"

LEDG

altera_avalon_pio v9.1

clk clk   LEDG
  clk
cpu data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

NIOS_R

altera_avalon_pio v9.1

clk clk   NIOS_R
  clk
cpu data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

NIOS_B

altera_avalon_pio v9.1

clk clk   NIOS_B
  clk
cpu data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

SW

altera_avalon_pio v9.1

clk clk   SW
  clk
cpu data_master  
  s1
d_irq  
  irq




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 100000000
direction Input
edgeType RISING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "RISING"
IRQ_TYPE "EDGE"
FREQ 100000000u

SEG7_ADDR

altera_avalon_pio v9.1

clk clk   SEG7_ADDR
  clk
cpu data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

SEG7_DATA

altera_avalon_pio v9.1

clk clk   SEG7_DATA
  clk
cpu data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u

LEDR

altera_avalon_pio v9.1

clk clk   LEDR
  clk
cpu data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 100000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 18
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 18
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 100000000u
generation took 0,02 seconds rendering took 9,00 seconds