Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
inst7 10 0 0 0 56 0 0 0 0 0 0 0 0
inst4 0 101 0 101 101 101 101 101 0 0 0 0 0
inst9 32 0 0 0 35 0 0 0 0 0 0 0 0
inst1|nios_system_reset_clk_domain_synch 3 1 0 1 1 1 1 1 0 0 0 0 0
inst1|the_tri_state_bridge_0_avalon_slave 73 0 4 0 52 0 0 0 8 0 0 0 0
inst1|the_sysid 1 18 0 18 32 18 18 18 0 0 0 0 0
inst1|the_sysid_control_slave 62 0 2 0 38 0 0 0 0 0 0 0 0
inst1|the_spi_0 25 0 0 0 23 0 0 0 0 0 0 0 0
inst1|the_spi_0_spi_control_port 82 3 18 3 48 3 3 3 0 0 0 0 0
inst1|the_onchip_memory2_0|the_altsyncram|auto_generated|mux2 98 0 0 0 32 0 0 0 0 0 0 0 0
inst1|the_onchip_memory2_0|the_altsyncram|auto_generated|deep_decode 3 0 0 0 3 0 0 0 0 0 0 0 0
inst1|the_onchip_memory2_0|the_altsyncram|auto_generated|decode3 3 0 0 0 3 0 0 0 0 0 0 0 0
inst1|the_onchip_memory2_0|the_altsyncram|auto_generated 53 0 0 0 32 0 0 0 0 0 0 0 0
inst1|the_onchip_memory2_0 54 0 0 0 32 0 0 0 0 0 0 0 0
inst1|the_onchip_memory2_0_s1 125 1 4 1 94 1 1 1 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram2 24 0 0 0 8 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_r 13 0 1 0 16 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram2 24 0 0 0 8 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0|the_jtag_uart_0_scfifo_w 12 0 0 0 16 0 0 0 0 0 0 0 0
inst1|the_jtag_uart_0 38 9 23 9 36 9 9 9 0 0 0 0 0
inst1|the_jtag_uart_0_avalon_jtag_slave 98 2 2 2 78 2 2 2 0 0 0 0 0
inst1|the_fifo_req 7 0 0 0 2 0 0 0 0 0 0 0 0
inst1|the_fifo_req_s1 63 0 33 0 12 0 0 0 0 0 0 0 0
inst1|the_cpu 151 2 29 2 121 2 2 2 0 0 0 0 0
inst1|the_cpu_instruction_master 115 0 1 0 62 0 0 0 0 0 0 0 0
inst1|the_cpu_data_master 378 29 6 29 102 29 29 29 0 0 0 0 0
inst1|the_cpu_jtag_debug_module 127 0 4 0 92 0 0 0 0 0 0 0 0
inst1|the_SW 22 0 0 0 9 0 0 0 0 0 0 0 0
inst1|the_SW_s1 75 0 29 0 27 0 0 0 0 0 0 0 0
inst1|the_SEG7_DATA 10 0 0 0 8 0 0 0 0 0 0 0 0
inst1|the_SEG7_DATA_s1 66 0 30 0 18 0 0 0 0 0 0 0 0
inst1|the_SEG7_ADDR 10 0 0 0 8 0 0 0 0 0 0 0 0
inst1|the_SEG7_ADDR_s1 66 0 30 0 18 0 0 0 0 0 0 0 0
inst1|the_NIOS_R 14 0 0 0 16 0 0 0 0 0 0 0 0
inst1|the_NIOS_R_s1 74 0 29 0 26 0 0 0 0 0 0 0 0
inst1|the_NIOS_G 14 0 0 0 16 0 0 0 0 0 0 0 0
inst1|the_NIOS_G_s1 74 0 29 0 26 0 0 0 0 0 0 0 0
inst1|the_NIOS_B 14 0 0 0 16 0 0 0 0 0 0 0 0
inst1|the_NIOS_B_s1 74 0 29 0 26 0 0 0 0 0 0 0 0
inst1|the_LEDR 24 0 0 0 36 0 0 0 0 0 0 0 0
inst1|the_LEDR_s1 80 0 16 0 46 0 0 0 0 0 0 0 0
inst1|the_LEDG 14 0 0 0 16 0 0 0 0 0 0 0 0
inst1|the_LEDG_s1 74 0 29 0 26 0 0 0 0 0 0 0 0
inst1|the_LCD 13 0 1 0 11 0 0 0 8 0 0 0 0
inst1|the_LCD_control_slave 74 0 29 0 27 0 0 0 0 0 0 0 0
inst1 11 0 0 0 90 0 0 0 16 0 0 0 0
inst12 2 0 0 0 1 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp 20 0 0 0 1 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp 20 0 0 0 1 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe19 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|ws_dgrp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|ws_bwp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|ws_brp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe15 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|rs_dgwp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|rs_bwp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|rs_brp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|rdaclr 3 1 0 1 1 1 1 1 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|fifo_ram|altsyncram11 58 17 0 17 16 17 17 17 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|fifo_ram 40 0 0 0 16 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|wrptr_gp 3 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|wrptr_g1p 3 0 0 0 0 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo2|dcfifo_component|auto_generated 21 0 0 0 36 0 0 0 0 0 0 0 0
inst5|read_fifo2 21 0 0 0 35 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp 20 0 0 0 1 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp 20 0 0 0 1 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe19 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|ws_dgrp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|ws_bwp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|ws_brp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe15 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|rs_dgwp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|rs_bwp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|rs_brp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|rdaclr 3 1 0 1 1 1 1 1 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|fifo_ram|altsyncram11 58 17 0 17 16 17 17 17 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|fifo_ram 40 0 0 0 16 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|wrptr_gp 3 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|wrptr_g1p 3 0 0 0 0 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|read_fifo1|dcfifo_component|auto_generated 21 0 0 0 36 0 0 0 0 0 0 0 0
inst5|read_fifo1 21 0 0 0 35 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|wrfull_eq_comp 20 0 0 0 1 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|rdempty_eq_comp 20 0 0 0 1 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|ws_dgrp|dffpipe19 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|ws_dgrp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|ws_bwp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|ws_brp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|rs_dgwp|dffpipe15 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|rs_dgwp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|rs_bwp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|rs_brp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|rdaclr 3 1 0 1 1 1 1 1 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|fifo_ram|altsyncram11 58 17 0 17 16 17 17 17 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|fifo_ram 40 0 0 0 16 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|wrptr_gp 3 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|wrptr_g1p 3 0 0 0 0 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|ws_dgrp_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|wrptr_g_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|rs_dgwp_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated|rdptr_g_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo2|dcfifo_component|auto_generated 21 0 0 0 36 0 0 0 0 0 0 0 0
inst5|write_fifo2 21 0 0 0 35 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|wrfull_eq_comp 20 0 0 0 1 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|rdempty_eq_comp 20 0 0 0 1 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|ws_dgrp|dffpipe19 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|ws_dgrp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|ws_bwp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|ws_brp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|rs_dgwp|dffpipe15 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|rs_dgwp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|rs_bwp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|rs_brp 12 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|rdaclr 3 1 0 1 1 1 1 1 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|fifo_ram|altsyncram11 58 17 0 17 16 17 17 17 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|fifo_ram 40 0 0 0 16 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|wrptr_gp 3 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|wrptr_g1p 3 0 0 0 0 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|rdptr_g1p 3 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|ws_dgrp_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|wrptr_g_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|rs_dgwp_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated|rdptr_g_gray2bin 10 0 0 0 10 0 0 0 0 0 0 0 0
inst5|write_fifo1|dcfifo_component|auto_generated 21 0 0 0 36 0 0 0 0 0 0 0 0
inst5|write_fifo1 21 0 0 0 35 0 0 0 0 0 0 0 0
inst5|data_path1 20 2 0 2 18 2 2 2 0 0 0 0 0
inst5|command1 35 0 2 0 23 0 0 0 0 0 0 0 0
inst5|control1 30 1 0 1 32 1 1 1 0 0 0 0 0
inst5 267 45 93 45 94 45 45 45 16 0 0 0 0
inst 1 0 0 0 3 0 0 0 0 0 0 0 0