Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
inst26|nios_system_reset_clk_domain_synch 3 1 0 1 1 1 1 1 0 0 0 0 0
inst26|the_tri_state_bridge_0_avalon_slave 70 0 4 0 54 0 0 0 8 0 0 0 0
inst26|the_sysid 1 12 0 12 32 12 12 12 0 0 0 0 0
inst26|the_sysid_control_slave 60 0 2 0 38 0 0 0 0 0 0 0 0
inst26|the_pio_0 9 0 0 0 5 0 0 0 0 0 0 0 0
inst26|the_pio_0_s1 33 0 2 0 13 0 0 0 0 0 0 0 0
inst26|the_onchip_memory2_0|the_altsyncram|auto_generated|mux2 65 0 0 0 32 0 0 0 0 0 0 0 0
inst26|the_onchip_memory2_0|the_altsyncram|auto_generated|decode3 2 0 0 0 2 0 0 0 0 0 0 0 0
inst26|the_onchip_memory2_0|the_altsyncram|auto_generated 52 0 0 0 32 0 0 0 0 0 0 0 0
inst26|the_onchip_memory2_0 53 0 0 0 32 0 0 0 0 0 0 0 0
inst26|the_onchip_memory2_0_s1 122 1 4 1 94 1 1 1 0 0 0 0 0
inst26|the_lcd_0 13 0 1 0 11 0 0 0 8 0 0 0 0
inst26|the_lcd_0_control_slave 72 0 29 0 28 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 24 0 0 0 8 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_r|rfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_r 13 0 1 0 16 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr 4 0 0 0 6 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 6 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 24 0 0 0 8 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram 24 0 0 0 8 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 6 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state 5 0 0 0 8 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated|dpfifo 13 0 0 0 16 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_w|wfifo|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0|the_jtag_uart_0_scfifo_w 12 0 0 0 16 0 0 0 0 0 0 0 0
inst26|the_jtag_uart_0 38 9 23 9 36 9 9 9 0 0 0 0 0
inst26|the_jtag_uart_0_avalon_jtag_slave 97 2 2 2 78 2 2 2 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_jtag_debug_module_wrapper|the_cpu_0_jtag_debug_module_sysclk 43 0 0 0 51 0 0 0 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_jtag_debug_module_wrapper|the_cpu_0_jtag_debug_module_tck 130 1 1 1 43 1 1 1 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_jtag_debug_module_wrapper 123 0 0 0 53 0 0 0 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component|the_altsyncram|auto_generated 92 0 0 0 72 0 0 0 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_im|cpu_0_traceram_lpm_dram_bdp_component 92 74 0 74 72 74 74 74 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_im 97 36 17 36 48 36 36 36 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_pib 39 20 38 20 19 20 20 20 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_fifo|the_cpu_0_oci_test_bench 36 0 36 0 0 0 0 0 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifocount_inc_fifocount 5 0 0 0 5 0 0 0 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_fifowp_inc_fifowp 4 4 0 4 4 4 4 4 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_fifo|cpu_0_nios2_oci_compute_tm_count_tm_count 3 0 0 0 2 0 0 0 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_fifo 151 0 65 0 36 0 0 0 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_dtrace|cpu_0_nios2_oci_trc_ctrl_td_mode 9 4 6 4 4 4 4 4 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_dtrace 109 0 98 0 72 0 0 0 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_itrace 25 17 23 17 87 17 17 17 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_dbrk 94 1 0 1 98 1 1 1 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_xbrk 60 5 57 5 6 5 5 5 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_break 52 36 6 36 71 36 36 36 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_avalon_reg 49 0 29 0 68 0 0 0 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component|the_altsyncram|auto_generated 90 0 0 0 64 0 0 0 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_ocimem|cpu_0_ociram_lpm_dram_bdp_component 90 2 0 2 64 2 2 2 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_ocimem 93 0 6 0 64 0 0 0 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci|the_cpu_0_nios2_oci_debug 50 1 30 1 7 1 1 1 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_nios2_oci 170 31 0 31 68 31 31 31 0 0 0 0 0
inst26|the_cpu_0|cpu_0_rf|the_altsyncram|auto_generated 80 0 0 0 64 0 0 0 0 0 0 0 0
inst26|the_cpu_0|cpu_0_rf 80 2 0 2 64 2 2 2 0 0 0 0 0
inst26|the_cpu_0|the_cpu_0_test_bench 451 5 412 5 34 5 5 5 0 0 0 0 0
inst26|the_cpu_0 149 2 31 2 121 2 2 2 0 0 0 0 0
inst26|the_cpu_0_instruction_master 116 0 5 0 59 0 0 0 0 0 0 0 0
inst26|the_cpu_0_data_master 253 31 17 31 100 31 31 31 0 0 0 0 0
inst26|the_cpu_0_jtag_debug_module 124 0 4 0 92 0 0 0 0 0 0 0 0
inst26 7 0 0 0 28 0 0 0 16 0 0 0 0
inst3 1 0 0 0 2 0 0 0 0 0 0 0 0
inst4 5 8 0 8 26 8 8 8 0 0 0 0 0
inst 27 0 0 0 2 0 0 0 1 0 0 0 0
inst25 2 0 0 0 1 0 0 0 0 0 0 0 0
inst19|lpm_mux_component|auto_generated 49 0 0 0 24 0 0 0 0 0 0 0 0
inst19 49 0 0 0 24 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Usc 3 0 0 0 11 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Urnd 45 0 0 0 24 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Usscx 50 0 0 0 47 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Usershft 4 1 0 1 24 1 1 1 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Usa 26 0 0 0 23 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Umtl 23 0 1 0 22 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Uaddl_3_n_0_n 44 0 0 0 22 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Uaddl_2_n_1_n 42 20 0 20 21 20 20 20 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Uaddl_2_n_0_n 42 0 0 0 21 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Uaddl_1_n_2_n 40 19 0 19 20 19 19 19 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Uaddl_1_n_1_n 40 0 0 0 20 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Uaddl_1_n_0_n 40 0 0 0 20 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Uaddl_0_n_4_n 38 18 0 18 19 18 18 18 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Uaddl_0_n_3_n 38 0 0 0 19 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Uaddl_0_n_2_n 38 0 0 0 19 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Uaddl_0_n_1_n 38 0 0 0 19 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Uaddl_0_n_0_n 38 0 0 0 19 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Ur8_n 6 1 0 1 18 1 1 1 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Ur7_n 6 0 0 0 18 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Ur6_n 6 0 0 0 18 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Ur5_n 6 0 0 0 18 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Ur4_n 6 0 0 0 18 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Ur3_n 6 0 0 0 17 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Ur2_n 6 0 0 0 16 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Ur1_n 6 0 0 0 16 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Ur0_n 6 0 0 0 15 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_34_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_33_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_32_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_31_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_30_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_29_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_28_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_27_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_26_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_25_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_24_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_23_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_22_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_21_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_20_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_19_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_18_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_17_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_16_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_15_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_14_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_13_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_12_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_11_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_10_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_9_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_8_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_7_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_6_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_5_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_4_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_3_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_2_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_1_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|sym_0_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Utdl_4_n 5 0 0 0 17 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Utdl_3_n 5 0 0 0 17 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Utdl_2_n 5 0 0 0 17 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Utdl_1_n 5 0 0 0 17 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Utdl_0_n 5 0 0 0 17 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore|Utdl_0_a 29 0 0 0 1 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|fircore 27 1 0 1 28 1 1 1 0 0 0 0 0
inst1|hw_filter_ast_inst|intf_ctrl 9 1 0 1 6 1 1 1 0 0 0 0 0
inst1|hw_filter_ast_inst|source 32 0 0 0 31 0 0 0 0 0 0 0 0
inst1|hw_filter_ast_inst|sink 32 2 0 2 30 2 2 2 0 0 0 0 0
inst1|hw_filter_ast_inst 32 0 0 0 31 0 0 0 0 0 0 0 0
inst1 32 3 0 3 31 3 3 3 0 0 0 0 0
inst7 5 0 0 0 27 0 0 0 0 0 0 0 0
inst17 3 0 0 0 2 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Usc 3 0 0 0 11 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Urnd 42 0 0 0 24 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Usscx 48 0 0 0 45 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Usershft 4 1 0 1 24 1 1 1 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Usa 24 0 0 0 21 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Umtl 21 0 1 0 20 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Uaddl_2_n_0_n 40 0 0 0 20 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Uaddl_1_n_1_n 38 18 0 18 19 18 18 18 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Uaddl_1_n_0_n 38 0 0 0 19 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Uaddl_0_n_2_n 36 17 0 17 18 17 17 17 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Uaddl_0_n_1_n 36 0 0 0 18 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Uaddl_0_n_0_n 36 0 0 0 18 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Ur4_n 6 0 0 0 17 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Ur3_n 6 0 0 0 15 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Ur2_n 6 0 0 0 14 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Ur1_n 6 0 0 0 14 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Ur0_n 6 0 0 0 13 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_19_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_18_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_17_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_16_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_15_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_14_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_13_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_12_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_11_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_10_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_9_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_8_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_7_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_6_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_5_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_4_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_3_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_2_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_1_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|sym_0_n 5 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Utdl_2_n 5 0 0 0 17 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Utdl_1_n 5 0 0 0 17 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Utdl_0_n 5 0 0 0 17 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore|Utdl_0_a 29 0 0 0 1 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|fircore 27 1 0 1 28 1 1 1 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|intf_ctrl 9 1 0 1 6 1 1 1 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|source 32 0 0 0 31 0 0 0 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst|sink 32 2 0 2 30 2 2 2 0 0 0 0 0
inst5|hw_filter_high_pass_ast_inst 32 0 0 0 31 0 0 0 0 0 0 0 0
inst5 32 3 0 3 31 3 3 3 0 0 0 0 0
inst10 28 0 0 0 1 0 0 0 0 0 0 0 0