---

clk

clock_source v9.1

Parameters clockFrequency 150000000 clockFrequencyKnown true inputClockFrequency 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

cpu_0

altera_nios2 v9.1

Parameters userDefinedSettings setting_showUnpublishedSettings false setting_showInternalSettings false setting_shadowRegisterSets 0 setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_perfCounterWidth _32 setting_interruptControllerType Internal setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_branchPredictionType Automatic setting_bit31BypassDCache true setting_bigEndian false setting_bhtPtrSz _8 setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTestEndChecker false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false resetSlave onchip_memory2_0.s1 resetOffset 0 muldiv_multiplierType EmbeddedMulFast muldiv_divider false mpu_useLimit false mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mpu_minInstRegionSize _12 mpu_minDataRegionSize _12 mpu_enabled false mmu_uitlbNumEntries _4 mmu_udtlbNumEntries _6 mmu_tlbPtrSz _7 mmu_tlbNumWays _16 mmu_processIDNumBits _8 mmu_enabled false mmu_autoAssignTlbPtrSz true mmu_TLBMissExcSlave mmu_TLBMissExcOffset 0 manuallyAssignCpuID false impl Fast icache_size _4096 icache_ramBlockType Automatic icache_numTCIM _0 icache_burstType None exceptionSlave onchip_memory2_0.s1 exceptionOffset 32 debug_triggerArming true debug_level Level1 debug_jtagInstanceID 0 debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false debug_OCIOnchipTrace _128 dcache_size _2048 dcache_ramBlockType Automatic dcache_omitDataMaster false dcache_numTCDM _0 dcache_lineSize _32 dcache_bursts false cpuReset false cpuID 0 clockFrequency 150000000 breakSlave cpu_0.jtag_debug_module breakOffset 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CPU_IMPLEMENTATION "fast" BIG_ENDIAN 0 CPU_FREQ 150000000u ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 4096 DCACHE_LINE_SIZE 32 DCACHE_LINE_SIZE_LOG2 5 DCACHE_SIZE 2048 INITDA_SUPPORTED FLUSHDA_SUPPORTED HAS_JMPI_INSTRUCTION EXCEPTION_ADDR 0x8020 RESET_ADDR 0x8000 BREAK_ADDR 0x10820 HAS_DEBUG_STUB HAS_DEBUG_CORE 1 CPU_ID_SIZE 1 CPU_ID_VALUE 0x0 HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 0 INST_ADDR_WIDTH 17 DATA_ADDR_WIDTH 17 NUM_OF_SHADOW_REG_SETS 0

---

onchip_memory2_0

altera_avalon_onchip_memory2 v9.1

Parameters allowInSystemMemoryContentEditor false blockType AUTO dataWidth 32 deviceFamily Cyclone II dualPort false initMemContent true initializationFileName onchip_memory2_0 instanceID NONE memorySize 32768 readDuringWriteMode DONT_CARE simAllowMRAMContentsFile false slave1Latency 1 slave2Latency 1 useNonDefaultInitFile false useShallowMemBlocks false writable true generateLegacySim false

  

Software Assignments ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 INIT_CONTENTS_FILE "onchip_memory2_0" NON_DEFAULT_INIT_FILE_ENABLED 0 GUI_RAM_BLOCK_TYPE "Automatic" WRITABLE 1 DUAL_PORT 0 SIZE_VALUE 32768u SIZE_MULTIPLE 1 CONTENTS_INFO "" RAM_BLOCK_TYPE "Auto" INIT_MEM_CONTENT 1 ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 INSTANCE_ID "NONE" READ_DURING_WRITE_MODE "DONT_CARE"

---

jtag_uart_0

altera_avalon_jtag_uart v9.1

Parameters allowMultipleConnections false hubInstanceID 0 readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions INTERACTIVE_ASCII_OUTPUT useRegistersForReadBuffer false useRegistersForWriteBuffer false useRelativePathForSimFile false writeBufferDepth 64 writeIRQThreshold 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments WRITE_DEPTH 64 READ_DEPTH 64 WRITE_THRESHOLD 8 READ_THRESHOLD 8

---

LEDs

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 150000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 8 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 150000000u

---

SWint

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 150000000 direction Input edgeType FALLING generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring true simDrivenValue 0 width 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 1 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 8 RESET_VALUE 0x0 EDGE_TYPE "FALLING" IRQ_TYPE "EDGE" FREQ 150000000u

---

timer_0

altera_avalon_timer v9.1

Parameters alwaysRun false counterSize 32 fixedPeriod false period 1 periodUnits MSEC resetOutput false snapshot true systemFrequency 150000000 timeoutPulseOutput false timerPreset FULL_FEATURED deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALWAYS_RUN 0 FIXED_PERIOD 0 SNAPSHOT 1 PERIOD 1 PERIOD_UNITS "ms" RESET_OUTPUT 0 TIMEOUT_PULSE_OUTPUT 0 FREQ 150000000u LOAD_VALUE 149999ULL COUNTER_SIZE 32 MULT 0.0010 TICKS_PER_SEC 1000u

---

SWint2

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 150000000 direction Input edgeType FALLING generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 8 RESET_VALUE 0x0 EDGE_TYPE "FALLING" IRQ_TYPE "EDGE" FREQ 150000000u

---

sysid

altera_avalon_sysid v9.1

Parameters id 1068063236 timestamp 1274544834 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ID 1068063236u TIMESTAMP 1274544834u

---

LUT_INDEX

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 150000000 direction Input edgeType ANY generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 6 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 6 RESET_VALUE 0x0 EDGE_TYPE "ANY" IRQ_TYPE "EDGE" FREQ 150000000u

---

LUT_DATA

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 150000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 24 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 24 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 150000000u

---

performance_counter_0

altera_avalon_performance_counter v9.1

Parameters numberOfSections 3 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments HOW_MANY_SECTIONS 3

---

CCD_XY

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 150000000 direction Input edgeType ANY generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 2 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 2 RESET_VALUE 0x0 EDGE_TYPE "ANY" IRQ_TYPE "EDGE" FREQ 150000000u

---

RED

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 150000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 12 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 12 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 150000000u

---

BLUE

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 150000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 12 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 12 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 150000000u

---

RESET_OUT

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 150000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 1 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 150000000u

---

IN_mDATA_0

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 150000000 direction Input edgeType ANY generateIRQ false irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 12 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 12 RESET_VALUE 0x0 EDGE_TYPE "ANY" IRQ_TYPE "NONE" FREQ 150000000u

---

IN_mDATA_1

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 150000000 direction Input edgeType ANY generateIRQ false irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 12 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 12 RESET_VALUE 0x0 EDGE_TYPE "ANY" IRQ_TYPE "NONE" FREQ 150000000u

---

RAW2RGB_CONTROL_OUT

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg true captureEdge false clockRate 150000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 4 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 1 DATA_WIDTH 4 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 150000000u

---

LCD_0

altera_avalon_lcd_16207 v9.1

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

cpu_0_fpoint

altera_nios_custom_instr_floating_point v6.1

Parameters useDivider true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

GREEN

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 150000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 12 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 12 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 150000000u

---

DVAL

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 150000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 1 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 150000000u

---

IN_mDATAd_0

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 150000000 direction Input edgeType ANY generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 12 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 12 RESET_VALUE 0x0 EDGE_TYPE "ANY" IRQ_TYPE "NONE" FREQ 150000000u

---

IN_mDATAd_1

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 150000000 direction Input edgeType ANY generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 12 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 12 RESET_VALUE 0x0 EDGE_TYPE "ANY" IRQ_TYPE "NONE" FREQ 150000000u

---

PIX_VALCLK

altera_avalon_pio v9.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge true clockRate 150000000 direction Input edgeType RISING generateIRQ true irqType EDGE resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 0 HAS_IN 1 CAPTURE 1 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 1 RESET_VALUE 0x0 EDGE_TYPE "RISING" IRQ_TYPE "EDGE" FREQ 150000000u