niosii



2010.05.22.18:14:21 Datasheet
Overview
  clk  niosii
   LEDs
 out_port  
 in_port  
 in_port  
 in_port  
 out_port  
 in_port  
 out_port  
 out_port  
 out_port  
 in_port  
 in_port  
 out_port  
   LCD_0
 LCD_data  
 LCD_E  
 LCD_RS  
 LCD_RW  
   GREEN
 out_port  
 out_port  
 in_port  
 in_port  
 in_port  
Processor

   cpu_0 Nios II 9.1

Peripherals

   cpu_0 altera_nios2 9.1

   onchip_memory2_0 altera_avalon_onchip_memory2 9.1

   jtag_uart_0 altera_avalon_jtag_uart 9.1

   LEDs altera_avalon_pio 9.1

   SWint altera_avalon_pio 9.1

   timer_0 altera_avalon_timer 9.1

   SWint2 altera_avalon_pio 9.1

   sysid altera_avalon_sysid 9.1

   LUT_INDEX altera_avalon_pio 9.1

   LUT_DATA altera_avalon_pio 9.1

   performance_counter_0 altera_avalon_performance_counter 9.1

   CCD_XY altera_avalon_pio 9.1

   RED altera_avalon_pio 9.1

   BLUE altera_avalon_pio 9.1

   RESET_OUT altera_avalon_pio 9.1

   IN_mDATA_0 altera_avalon_pio 9.1

   IN_mDATA_1 altera_avalon_pio 9.1

   RAW2RGB_CONTROL_OUT altera_avalon_pio 9.1

   LCD_0 altera_avalon_lcd_16207 9.1

   GREEN altera_avalon_pio 9.1

   DVAL altera_avalon_pio 9.1

   IN_mDATAd_0 altera_avalon_pio 9.1

   IN_mDATAd_1 altera_avalon_pio 9.1

   PIX_VALCLK altera_avalon_pio 9.1
Memory Map
cpu_0
 instruction_master  data_master
  cpu_0
jtag_debug_module  0x00010800 0x00010800
  onchip_memory2_0
s1  0x00008000 0x00008000
  jtag_uart_0
avalon_jtag_slave  0x00011190
  LEDs
s1  0x00011080
  SWint
s1  0x00011090
  timer_0
s1  0x00011040
  SWint2
s1  0x000110a0
  sysid
control_slave  0x00011198
  LUT_INDEX
s1  0x000110b0
  LUT_DATA
s1  0x000110c0
  performance_counter_0
control_slave  0x00011000
  CCD_XY
s1  0x000110d0
  RED
s1  0x000110e0
  BLUE
s1  0x000110f0
  RESET_OUT
s1  0x00011100
  IN_mDATA_0
s1  0x00011110
  IN_mDATA_1
s1  0x00011120
  RAW2RGB_CONTROL_OUT
s1  0x00011060
  LCD_0
control_slave  0x00011130
  GREEN
s1  0x00011140
  DVAL
s1  0x00011150
  IN_mDATAd_0
s1  0x00011160
  IN_mDATAd_1
s1  0x00011170
  PIX_VALCLK
s1  0x00011180

clk

clock_source v9.1





Parameters

clockFrequency 150000000
clockFrequencyKnown true
inputClockFrequency 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cpu_0

altera_nios2 v9.1

clk clk   cpu_0
  clk
instruction_master   onchip_memory2_0
  s1
data_master  
  s1
data_master   jtag_uart_0
  avalon_jtag_slave
d_irq  
  irq
data_master   LEDs
  s1
data_master   SWint
  s1
d_irq  
  irq
data_master   timer_0
  s1
d_irq  
  irq
data_master   SWint2
  s1
d_irq  
  irq
data_master   sysid
  control_slave
data_master   LUT_INDEX
  s1
d_irq  
  irq
data_master   LUT_DATA
  s1
data_master   performance_counter_0
  control_slave
data_master   CCD_XY
  s1
d_irq  
  irq
data_master   RED
  s1
data_master   BLUE
  s1
data_master   RESET_OUT
  s1
data_master   IN_mDATA_0
  s1
data_master   IN_mDATA_1
  s1
data_master   RAW2RGB_CONTROL_OUT
  s1
data_master   LCD_0
  control_slave
custom_instruction_master   cpu_0_fpoint
  s1
data_master   GREEN
  s1
data_master   DVAL
  s1
data_master   IN_mDATAd_0
  s1
data_master   IN_mDATAd_1
  s1
data_master   PIX_VALCLK
  s1
d_irq  
  irq




Parameters

userDefinedSettings
setting_showUnpublishedSettings false
setting_showInternalSettings false
setting_shadowRegisterSets 0
setting_preciseSlaveAccessErrorException false
setting_preciseIllegalMemAccessException false
setting_preciseDivisionErrorException false
setting_performanceCounter false
setting_perfCounterWidth _32
setting_interruptControllerType Internal
setting_illegalMemAccessDetection false
setting_illegalInstructionsTrap false
setting_fullWaveformSignals false
setting_extraExceptionInfo false
setting_exportPCB false
setting_debugSimGen false
setting_clearXBitsLDNonBypass true
setting_branchPredictionType Automatic
setting_bit31BypassDCache true
setting_bigEndian false
setting_bhtPtrSz _8
setting_bhtIndexPcOnly false
setting_avalonDebugPortPresent false
setting_alwaysEncrypt true
setting_allowFullAddressRange false
setting_activateTrace true
setting_activateTestEndChecker false
setting_activateMonitors true
setting_activateModelChecker false
setting_HDLSimCachesCleared true
setting_HBreakTest false
resetSlave onchip_memory2_0.s1
resetOffset 0
muldiv_multiplierType EmbeddedMulFast
muldiv_divider false
mpu_useLimit false
mpu_numOfInstRegion 8
mpu_numOfDataRegion 8
mpu_minInstRegionSize _12
mpu_minDataRegionSize _12
mpu_enabled false
mmu_uitlbNumEntries _4
mmu_udtlbNumEntries _6
mmu_tlbPtrSz _7
mmu_tlbNumWays _16
mmu_processIDNumBits _8
mmu_enabled false
mmu_autoAssignTlbPtrSz true
mmu_TLBMissExcSlave
mmu_TLBMissExcOffset 0
manuallyAssignCpuID false
impl Fast
icache_size _4096
icache_ramBlockType Automatic
icache_numTCIM _0
icache_burstType None
exceptionSlave onchip_memory2_0.s1
exceptionOffset 32
debug_triggerArming true
debug_level Level1
debug_jtagInstanceID 0
debug_embeddedPLL true
debug_debugReqSignals false
debug_assignJtagInstanceID false
debug_OCIOnchipTrace _128
dcache_size _2048
dcache_ramBlockType Automatic
dcache_omitDataMaster false
dcache_numTCDM _0
dcache_lineSize _32
dcache_bursts false
cpuReset false
cpuID 0
clockFrequency 150000000
breakSlave cpu_0.jtag_debug_module
breakOffset 32
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

CPU_IMPLEMENTATION "fast"
BIG_ENDIAN 0
CPU_FREQ 150000000u
ICACHE_LINE_SIZE 32
ICACHE_LINE_SIZE_LOG2 5
ICACHE_SIZE 4096
DCACHE_LINE_SIZE 32
DCACHE_LINE_SIZE_LOG2 5
DCACHE_SIZE 2048
INITDA_SUPPORTED
FLUSHDA_SUPPORTED
HAS_JMPI_INSTRUCTION
EXCEPTION_ADDR 0x8020
RESET_ADDR 0x8000
BREAK_ADDR 0x10820
HAS_DEBUG_STUB
HAS_DEBUG_CORE 1
CPU_ID_SIZE 1
CPU_ID_VALUE 0x0
HARDWARE_DIVIDE_PRESENT 0
HARDWARE_MULTIPLY_PRESENT 1
HARDWARE_MULX_PRESENT 0
INST_ADDR_WIDTH 17
DATA_ADDR_WIDTH 17
NUM_OF_SHADOW_REG_SETS 0

onchip_memory2_0

altera_avalon_onchip_memory2 v9.1

clk clk   onchip_memory2_0
  clk1
cpu_0 instruction_master  
  s1
data_master  
  s1




Parameters

allowInSystemMemoryContentEditor false
blockType AUTO
dataWidth 32
deviceFamily Cyclone II
dualPort false
initMemContent true
initializationFileName onchip_memory2_0
instanceID NONE
memorySize 32768
readDuringWriteMode DONT_CARE
simAllowMRAMContentsFile false
slave1Latency 1
slave2Latency 1
useNonDefaultInitFile false
useShallowMemBlocks false
writable true
generateLegacySim false
  

Software Assignments

ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
INIT_CONTENTS_FILE "onchip_memory2_0"
NON_DEFAULT_INIT_FILE_ENABLED 0
GUI_RAM_BLOCK_TYPE "Automatic"
WRITABLE 1
DUAL_PORT 0
SIZE_VALUE 32768u
SIZE_MULTIPLE 1
CONTENTS_INFO ""
RAM_BLOCK_TYPE "Auto"
INIT_MEM_CONTENT 1
ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
INSTANCE_ID "NONE"
READ_DURING_WRITE_MODE "DONT_CARE"

jtag_uart_0

altera_avalon_jtag_uart v9.1

clk clk   jtag_uart_0
  clk
cpu_0 data_master  
  avalon_jtag_slave
d_irq  
  irq




Parameters

allowMultipleConnections false
hubInstanceID 0
readBufferDepth 64
readIRQThreshold 8
simInputCharacterStream
simInteractiveOptions INTERACTIVE_ASCII_OUTPUT
useRegistersForReadBuffer false
useRegistersForWriteBuffer false
useRelativePathForSimFile false
writeBufferDepth 64
writeIRQThreshold 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

WRITE_DEPTH 64
READ_DEPTH 64
WRITE_THRESHOLD 8
READ_THRESHOLD 8

LEDs

altera_avalon_pio v9.1

cpu_0 data_master   LEDs
  s1
clk clk  
  clk




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 150000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 150000000u

SWint

altera_avalon_pio v9.1

clk clk   SWint
  clk
cpu_0 data_master  
  s1
d_irq  
  irq




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 150000000
direction Input
edgeType FALLING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring true
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 1
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "FALLING"
IRQ_TYPE "EDGE"
FREQ 150000000u

timer_0

altera_avalon_timer v9.1

clk clk   timer_0
  clk
cpu_0 data_master  
  s1
d_irq  
  irq




Parameters

alwaysRun false
counterSize 32
fixedPeriod false
period 1
periodUnits MSEC
resetOutput false
snapshot true
systemFrequency 150000000
timeoutPulseOutput false
timerPreset FULL_FEATURED
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ALWAYS_RUN 0
FIXED_PERIOD 0
SNAPSHOT 1
PERIOD 1
PERIOD_UNITS "ms"
RESET_OUTPUT 0
TIMEOUT_PULSE_OUTPUT 0
FREQ 150000000u
LOAD_VALUE 149999ULL
COUNTER_SIZE 32
MULT 0.0010
TICKS_PER_SEC 1000u

SWint2

altera_avalon_pio v9.1

clk clk   SWint2
  clk
cpu_0 data_master  
  s1
d_irq  
  irq




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 150000000
direction Input
edgeType FALLING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 8
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 8
RESET_VALUE 0x0
EDGE_TYPE "FALLING"
IRQ_TYPE "EDGE"
FREQ 150000000u

sysid

altera_avalon_sysid v9.1

clk clk   sysid
  clk
cpu_0 data_master  
  control_slave




Parameters

id 1068063236
timestamp 1274544834
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

ID 1068063236u
TIMESTAMP 1274544834u

LUT_INDEX

altera_avalon_pio v9.1

clk clk   LUT_INDEX
  clk
cpu_0 data_master  
  s1
d_irq  
  irq




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 150000000
direction Input
edgeType ANY
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 6
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 6
RESET_VALUE 0x0
EDGE_TYPE "ANY"
IRQ_TYPE "EDGE"
FREQ 150000000u

LUT_DATA

altera_avalon_pio v9.1

clk clk   LUT_DATA
  clk
cpu_0 data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 150000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 24
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 24
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 150000000u

performance_counter_0

altera_avalon_performance_counter v9.1

clk clk   performance_counter_0
  clk
cpu_0 data_master  
  control_slave




Parameters

numberOfSections 3
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

HOW_MANY_SECTIONS 3

CCD_XY

altera_avalon_pio v9.1

clk clk   CCD_XY
  clk
cpu_0 data_master  
  s1
d_irq  
  irq




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 150000000
direction Input
edgeType ANY
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 2
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 2
RESET_VALUE 0x0
EDGE_TYPE "ANY"
IRQ_TYPE "EDGE"
FREQ 150000000u

RED

altera_avalon_pio v9.1

clk clk   RED
  clk
cpu_0 data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 150000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 12
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 12
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 150000000u

BLUE

altera_avalon_pio v9.1

clk clk   BLUE
  clk
cpu_0 data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 150000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 12
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 12
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 150000000u

RESET_OUT

altera_avalon_pio v9.1

clk clk   RESET_OUT
  clk
cpu_0 data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 150000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 150000000u

IN_mDATA_0

altera_avalon_pio v9.1

clk clk   IN_mDATA_0
  clk
cpu_0 data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 150000000
direction Input
edgeType ANY
generateIRQ false
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 12
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 12
RESET_VALUE 0x0
EDGE_TYPE "ANY"
IRQ_TYPE "NONE"
FREQ 150000000u

IN_mDATA_1

altera_avalon_pio v9.1

clk clk   IN_mDATA_1
  clk
cpu_0 data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 150000000
direction Input
edgeType ANY
generateIRQ false
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 12
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 12
RESET_VALUE 0x0
EDGE_TYPE "ANY"
IRQ_TYPE "NONE"
FREQ 150000000u

RAW2RGB_CONTROL_OUT

altera_avalon_pio v9.1

clk clk   RAW2RGB_CONTROL_OUT
  clk
cpu_0 data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg true
captureEdge false
clockRate 150000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 4
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 1
DATA_WIDTH 4
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 150000000u

LCD_0

altera_avalon_lcd_16207 v9.1

clk clk   LCD_0
  clk
cpu_0 data_master  
  control_slave




Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

cpu_0_fpoint

altera_nios_custom_instr_floating_point v6.1

cpu_0 custom_instruction_master   cpu_0_fpoint
  s1




Parameters

useDivider true
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

GREEN

altera_avalon_pio v9.1

clk clk   GREEN
  clk
cpu_0 data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 150000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 12
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 12
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 150000000u

DVAL

altera_avalon_pio v9.1

clk clk   DVAL
  clk
cpu_0 data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge false
clockRate 150000000
direction Output
edgeType RISING
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 1
HAS_IN 0
CAPTURE 0
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "NONE"
IRQ_TYPE "NONE"
FREQ 150000000u

IN_mDATAd_0

altera_avalon_pio v9.1

clk clk   IN_mDATAd_0
  clk
cpu_0 data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 150000000
direction Input
edgeType ANY
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 12
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 12
RESET_VALUE 0x0
EDGE_TYPE "ANY"
IRQ_TYPE "NONE"
FREQ 150000000u

IN_mDATAd_1

altera_avalon_pio v9.1

clk clk   IN_mDATAd_1
  clk
cpu_0 data_master  
  s1




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 150000000
direction Input
edgeType ANY
generateIRQ false
irqType LEVEL
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 12
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 12
RESET_VALUE 0x0
EDGE_TYPE "ANY"
IRQ_TYPE "NONE"
FREQ 150000000u

PIX_VALCLK

altera_avalon_pio v9.1

clk clk   PIX_VALCLK
  clk
cpu_0 data_master  
  s1
d_irq  
  irq




Parameters

bitClearingEdgeCapReg false
bitModifyingOutReg false
captureEdge true
clockRate 150000000
direction Input
edgeType RISING
generateIRQ true
irqType EDGE
resetValue 0
simDoTestBenchWiring false
simDrivenValue 0
width 1
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

DO_TEST_BENCH_WIRING 0
DRIVEN_SIM_VALUE 0x0
HAS_TRI 0
HAS_OUT 0
HAS_IN 1
CAPTURE 1
BIT_CLEARING_EDGE_REGISTER 0
BIT_MODIFYING_OUTPUT_REGISTER 0
DATA_WIDTH 1
RESET_VALUE 0x0
EDGE_TYPE "RISING"
IRQ_TYPE "EDGE"
FREQ 150000000u
generation took 0,08 seconds rendering took 21,25 seconds